Module: Mesa
Branch: master
Commit: 51e23d34190076159129dd7b449b95a1ac3d4949
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51e23d34190076159129dd7b449b95a1ac3d4949
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Wed Jun 13 20:19:23 2018 +0200
radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8
This causes rendering issues in Shadow Warrior 2 with DXVK.
Cc: mesa-sta...@lists.freedesktop.org
Fixes: ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on
GFX8")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/amd/vulkan/radv_meta_clear.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index fae441ceb6..373072dd36 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -717,6 +717,14 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT))
goto fail;
+ /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
+ * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
+ * fast HTILE clears don't seem to work.
+ */
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
+ iview->image->vk_format == VK_FORMAT_D16_UNORM)
+ goto fail;
+
if (vk_format_aspects(iview->image->vk_format) &
VK_IMAGE_ASPECT_STENCIL_BIT) {
if (clear_value.stencil != 0 || !(aspects &
VK_IMAGE_ASPECT_STENCIL_BIT))
goto fail;
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