[Mesa-dev] [PATCH] [rfc] spirv/nir: handle casting in OpSampledImage

2017-09-25 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

%9903 = OpImageSampleDrefExplicitLod %float %14616 %14315 %16081 Lod %float_0
%14616 = OpSampledImage %510 %8499 %13137

%278 = OpTypeImage %float 2D 1 0 0 1 Unknown
%510 = OpTypeSampledImage %278

%8499 = OpLoad %150 %4159
%150 = OpTypeImage %float 2D 0 0 0 1 Unknown

Is being generated by a hlsl->spirv convertor.

So it appears that the 510 return type from sampledimage is a shadow sampler,
however the descriptor it's loading is for a 2D non-shadow image, which
makes it seems like OpSampledImage should cast appropriately.

Now I'm not sure enough to know if this is valid spir-v in the first place,
and I don't think this patch is good enough to fix it even if it is, but
let's use it to open discussions.
---
 src/compiler/spirv/spirv_to_nir.c | 6 +-
 src/compiler/spirv/vtn_private.h  | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 6ce9d1a..d962e93 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1490,6 +1490,8 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
   struct vtn_value *val =
  vtn_push_value(b, w[2], vtn_value_type_sampled_image);
   val->sampled_image = ralloc(b, struct vtn_sampled_image);
+  val->sampled_image->ret_type =
+ vtn_value(b, w[1], vtn_value_type_type)->type;
   val->sampled_image->image =
  vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
   val->sampled_image->sampler =
@@ -1521,7 +1523,9 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
}
 
const struct glsl_type *image_type;
-   if (sampled.image) {
+   if (sampled.ret_type) {
+  image_type = sampled.ret_type->type;
+   } else if (sampled.image) {
   image_type = sampled.image->var->var->interface_type;
} else {
   image_type = sampled.sampler->var->var->interface_type;
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 8458462..ce26326 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -413,6 +413,7 @@ struct vtn_image_pointer {
 struct vtn_sampled_image {
struct vtn_pointer *image; /* Image or array of images */
struct vtn_pointer *sampler; /* Sampler */
+   struct vtn_type *ret_type;
 };
 
 struct vtn_value {
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] radv: copy the number of viewports/scissors at pipeline bind time

2017-09-20 Thread Dave Airlie
R-b

On 20 Sep. 2017 22:07, "Samuel Pitoiset"  wrote:

> The number of viewports/scissors can only be specified at pipeline
> creation time, so make sure to copy them when binding a new one
> because the dynamic state is cleared in BeginCommandBuffer().
>
> Fixes: dcf46e995d ("radv: do not update the number of scissors in
> vkCmdSetScissor()")
> Fixes: 60878dd00c ("radv: do not update the number of viewports in
> vkCmdSetViewport()")
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_
> buffer.c
> index 0c3a5c6ffc..78b235fa22 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -83,14 +83,18 @@ radv_dynamic_state_copy(struct radv_dynamic_state
> *dest,
> const struct radv_dynamic_state *src,
> uint32_t copy_mask)
>  {
> +   /* Make sure to copy the number of viewports/scissors because they
> can
> +* only be specified at pipeline creation time.
> +*/
> +   dest->viewport.count = src->viewport.count;
> +   dest->scissor.count = src->scissor.count;
> +
> if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
> -   dest->viewport.count = src->viewport.count;
> typed_memcpy(dest->viewport.viewports,
> src->viewport.viewports,
>  src->viewport.count);
> }
>
> if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
> -   dest->scissor.count = src->scissor.count;
> typed_memcpy(dest->scissor.scissors,
> src->scissor.scissors,
>  src->scissor.count);
> }
> --
> 2.14.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] ac/nir: fixup layer/viewport export for GFX9.

2017-09-20 Thread Dave Airlie
On 20 Sep. 2017 18:13, "Juan A. Suarez Romero" <jasua...@igalia.com> wrote:

On Wed, 2017-08-23 at 22:07 +0300, Andres Gomez wrote:
> Hi Dave,
>
> This patch landed tagged for 17.2 only. Was it, then, not nominated for
> 17.1 intentionally ?
>

As we are preparing a new 17.1 release, gently pinging.


Gfx9 fixups are 17.2 only.

Dave.



J.A.

> Br.
>
> On Thu, 2017-08-17 at 14:27 +1000, Dave Airlie wrote:
> > From: Dave Airlie <airl...@redhat.com>
> >
> > GFX9 moved where the viewport index export goes.
> >
> > Signed-off-by: Dave Airlie <airl...@redhat.com>
> > ---
> >  src/amd/common/ac_nir_to_llvm.c | 32 +---
> >  1 file changed, 25 insertions(+), 7 deletions(-)
> >
> > diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_
llvm.c
> > index 7aa7567..a17a232 100644
> > --- a/src/amd/common/ac_nir_to_llvm.c
> > +++ b/src/amd/common/ac_nir_to_llvm.c
> > @@ -5518,11 +5518,11 @@ handle_vs_outputs_post(struct
nir_to_llvm_context *ctx,
> >
ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
> > }
> >
> > -   uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
> > -(outinfo->writes_layer == true ? 4 : 0) |
> > -(outinfo->writes_viewport_index == true ? 8 : 0));
> > -   if (mask) {
> > -   pos_args[1].enabled_channels = mask;
> > +   if (outinfo->writes_pointsize ||
> > +   outinfo->writes_layer ||
> > +   outinfo->writes_viewport_index) {
> > +   pos_args[1].enabled_channels = ((outinfo->writes_pointsize
== true ? 1 : 0) |
> > +   (outinfo->writes_layer ==
true ? 4 : 0));
> > pos_args[1].valid_mask = 0;
> > pos_args[1].done = 0;
> > pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
> > @@ -5536,8 +5536,26 @@ handle_vs_outputs_post(struct
nir_to_llvm_context *ctx,
> > pos_args[1].out[0] = psize_value;
> > if (outinfo->writes_layer == true)
> > pos_args[1].out[2] = layer_value;
> > -   if (outinfo->writes_viewport_index == true)
> > -   pos_args[1].out[3] = viewport_index_value;
> > +   if (outinfo->writes_viewport_index == true) {
> > +   if (ctx->options->chip_class >= GFX9) {
> > +   /* GFX9 has the layer in out.z[10:0] and
the viewport
> > +* index in out.z[19:16].
> > +*/
> > +   LLVMValueRef v = viewport_index_value;
> > +   v = to_integer(>ac, v);
> > +   v = LLVMBuildShl(ctx->builder, v,
> > +LLVMConstInt(ctx->i32, 16,
false),
> > +"");
> > +   v = LLVMBuildOr(ctx->builder, v,
> > +   to_integer(>ac,
pos_args[1].out[2]), "");
> > +
> > +   pos_args[1].out[2] = to_float(>ac, v);
> > +   pos_args[1].enabled_channels |= 1 << 2;
> > +   } else {
> > +   pos_args[1].out[3] = viewport_index_value;
> > +   pos_args[1].enabled_channels |= 1 << 3;
> > +   }
> > +   }
> > }
> > for (i = 0; i < 4; i++) {
> > if (pos_args[i].out[0])
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi: set MIP_POINT_PRECLAMP to 0

2017-09-19 Thread Dave Airlie
On 19 September 2017 at 02:38, Marek Olšák <mar...@gmail.com> wrote:
> I commented on patch 1. Other than that, the series is:
>
> Reviewed-by: Marek Olšák <marek.ol...@amd.com>

d81bd2f75462646d3803d683a28f6682a2ce3078
Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Mar 7 05:08:42 2017 +

radv: disable mip point pre clamping.

Effectively ported from radv :-P

Reviewed-by: Dave Airlie <airl...@redhat.com>

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: only bind specified layer subset to color/depth buffers.

2017-09-19 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This just fixes something I saw while reading vega traces, but
since we never bind a 3D texture for rendering, we only ever
want to bind the sublevels here.

This causes no regressions on cts on tahiti.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e6d595d..a16472c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3016,9 +3016,8 @@ radv_initialise_color_surface(struct radv_device *device,
cb->cb_dcc_base = va >> 8;
cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
 
-   uint32_t max_slice = radv_surface_layer_count(iview);
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
-   S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
+   S_028C6C_SLICE_MAX(iview->base_layer + iview->layer_count - 1);
 
if (iview->image->info.samples > 1) {
unsigned log_samples = 
util_logbase2(iview->image->info.samples);
@@ -3166,9 +3165,8 @@ radv_initialise_ds_surface(struct radv_device *device,
stencil_format = iview->image->surface.has_stencil ?
V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
 
-   uint32_t max_slice = radv_surface_layer_count(iview);
ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
-   S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
+   S_028008_SLICE_MAX(iview->base_layer + iview->layer_count - 1);
 
ds->db_htile_data_base = 0;
ds->db_htile_surface = 0;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] ac/surface: handle S8 on gfx9

2017-09-17 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

If we don't have a depth piece, we don't get a correct
swizzle mode and we hit an assert in addrlib.

In case of no depth get the preferrred swizzle mode for
stencil alone.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_surface.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 88cc8a1..850d707 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1138,9 +1138,14 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
/* Calculate texture layout information for stencil. */
if (surf->flags & RADEON_SURF_SBUFFER) {
-   AddrSurfInfoIn.bpp = 8;
-   AddrSurfInfoIn.flags.depth = 0;
AddrSurfInfoIn.flags.stencil = 1;
+   AddrSurfInfoIn.bpp = 8;
+
+   if (!AddrSurfInfoIn.flags.depth)
+   r = gfx9_get_preferred_swizzle_mode(addrlib, 
, false,
+   
);
+   else
+   AddrSurfInfoIn.flags.depth = 0;
 
r = gfx9_compute_miptree(addrlib, surf, compressed, 
);
if (r)
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] radv: Add VK_KHR_bind_memory2 support.

2017-09-17 Thread Dave Airlie
On 18 September 2017 at 01:00, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> Reviewed: Jason Ekstrand <ja...@jlekstrand.net>

Reviewed-by: Dave Airlie <airl...@redhat.com>

>
>
>
> On September 17, 2017 5:00:01 AM Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
> wrote:
>
>> Nothing too exciting, just adding the possibility for a pNext pointer,
>> and batch binding. Our binding is pretty much trivial.
>>
>> It also adds VK_IMAGE_CREATE_ALIAS_BIT_KHR, but since we store no
>> state in radv_image, I don't think we have to do anything there.
>> ---
>>  src/amd/vulkan/radv_device.c   | 82
>> --
>>  src/amd/vulkan/radv_entrypoints_gen.py |  1 +
>>  2 files changed, 59 insertions(+), 24 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index e6d595dfbe5..7bfdddf0eea 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -174,6 +174,10 @@ static const VkExtensionProperties
>> common_device_extensions[] = {
>> .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
>> .specVersion = 1,
>> },
>> +   {
>> +   .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
>> +   .specVersion = 1,
>> +   },
>>  };
>>  static const VkExtensionProperties ext_sema_device_extensions[] = {
>> {
>> @@ -2481,44 +2485,74 @@ void radv_GetDeviceMemoryCommitment(
>> *pCommittedMemoryInBytes = 0;
>>  }
>>
>> +VkResult radv_BindBufferMemory2KHR(VkDevice device,
>> +   uint32_t bindInfoCount,
>> +   const VkBindBufferMemoryInfoKHR
>> *pBindInfos)
>> +{
>> +   for (uint32_t i = 0; i < bindInfoCount; ++i) {
>> +   RADV_FROM_HANDLE(radv_device_memory, mem,
>> pBindInfos[i].memory);
>> +   RADV_FROM_HANDLE(radv_buffer, buffer,
>> pBindInfos[i].buffer);
>> +
>> +   if (mem) {
>> +   buffer->bo = mem->bo;
>> +   buffer->offset = pBindInfos[i].memoryOffset;
>> +   } else {
>> +   buffer->bo = NULL;
>> +   }
>> +   }
>> +   return VK_SUCCESS;
>> +}
>> +
>>  VkResult radv_BindBufferMemory(
>> VkDevicedevice,
>> -   VkBuffer_buffer,
>> -   VkDeviceMemory  _memory,
>> +   VkBufferbuffer,
>> +   VkDeviceMemory  memory,
>> VkDeviceSizememoryOffset)
>>  {
>> -   RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
>> -   RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
>> +   const VkBindBufferMemoryInfoKHR info = {
>> +   .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
>> +   .buffer = buffer,
>> +   .memory = memory,
>> +   .memoryOffset = memoryOffset
>> +   };
>>
>> -   if (mem) {
>> -   buffer->bo = mem->bo;
>> -   buffer->offset = memoryOffset;
>> -   } else {
>> -   buffer->bo = NULL;
>> -   buffer->offset = 0;
>> -   }
>> +   return radv_BindBufferMemory2KHR(device, 1, );
>> +}
>>
>> +VkResult radv_BindImageMemory2KHR(VkDevice device,
>> +  uint32_t bindInfoCount,
>> +  const VkBindImageMemoryInfoKHR
>> *pBindInfos)
>> +{
>> +   for (uint32_t i = 0; i < bindInfoCount; ++i) {
>> +   RADV_FROM_HANDLE(radv_device_memory, mem,
>> pBindInfos[i].memory);
>> +   RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
>> +
>> +   if (mem) {
>> +   image->bo = mem->bo;
>> +   image->offset = pBindInfos[i].memoryOffset;
>> +   } else {
>> +   image->bo = NULL;
>> +   image->offset = 0;
>> +   }
>> +   }
>> return VK_SUCCESS;
>>  }
>>
>> +
>>  VkResult radv_BindImageMemory(
>> VkDevicedevice,
>> -   VkImage   

Re: [Mesa-dev] [PATCH 3/3] radv: Don't use a virtual function for getting the buffer virtual address.

2017-09-17 Thread Dave Airlie
On 17 September 2017 at 20:59, Bas Nieuwenhuizen
<b...@basnieuwenhuizen.nl> wrote:
> We are really not going to use a winsys which does not need to store
> the va, so might as well store it in a standard field.
>
> Not sure this helps perf much though, as most of the cost is in the
> cache miss accessing the bo anyway, which we stil need to do.

I think I considered doing this in the past to no major effect but
with the inline renamed to radv_buffer_get_va,

All 3 are:

Reviewed-by: Dave Airlie <airl...@redhat.com>

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/5] mesa: align atomic buffer handling code with ubo/ssbo

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

this adds automatic size support to the atomic buffer code,
but also realigns the code to act like the ubo/ssbo code.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/bufferobj.c | 132 ++
 src/mesa/main/mtypes.h|   1 +
 2 files changed, 88 insertions(+), 45 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 2da2128..93b66dc 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1268,18 +1268,19 @@ set_atomic_buffer_binding(struct gl_context *ctx,
   struct gl_atomic_buffer_binding *binding,
   struct gl_buffer_object *bufObj,
   GLintptr offset,
-  GLsizeiptr size)
+  GLsizeiptr size,
+  bool autoSize)
 {
_mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
 
-   if (bufObj == ctx->Shared->NullBufferObj) {
-  binding->Offset = 0;
-  binding->Size = 0;
-   } else {
-  binding->Offset = offset;
-  binding->Size = size;
-  bufObj->UsageHistory |= USAGE_ATOMIC_COUNTER_BUFFER;
-   }
+   binding->Offset = offset;
+   binding->Size = size;
+   binding->AutomaticSize = autoSize;
+   /* If this is a real buffer object, mark it has having been used
+* at some point as an atomic counter buffer.
+*/
+   if (size >= 0)
+ bufObj->UsageHistory |= USAGE_ATOMIC_COUNTER_BUFFER;
 }
 
 /**
@@ -1399,6 +1400,33 @@ bind_shader_storage_buffer(struct gl_context *ctx,
 }
 
 /**
+ * Binds a buffer object to an atomic buffer binding point.
+ *
+ * Unlike set_atomic_binding(), this function also flushes vertices
+ * and updates NewDriverState.  It also checks if the binding
+ * has actually changed before updating it.
+ */
+static void
+bind_atomic_buffer(struct gl_context *ctx, unsigned index,
+   struct gl_buffer_object *bufObj, GLintptr offset,
+   GLsizeiptr size, GLboolean autoSize)
+{
+   struct gl_atomic_buffer_binding *binding =
+  >AtomicBufferBindings[index];
+   if (binding->BufferObject == bufObj &&
+   binding->Offset == offset &&
+   binding->Size == size &&
+   binding->AutomaticSize == autoSize) {
+  return;
+   }
+
+   FLUSH_VERTICES(ctx, 0);
+   ctx->NewDriverState |= ctx->DriverFlags.NewAtomicBuffer;
+
+   set_atomic_buffer_binding(ctx, binding, bufObj, offset, size, autoSize);
+}
+
+/**
  * Bind a buffer object to a uniform block binding point.
  * As above, but offset = 0.
  */
@@ -1442,25 +1470,26 @@ bind_buffer_base_shader_storage_buffer(struct 
gl_context *ctx,
   bind_shader_storage_buffer(ctx, index, bufObj, 0, 0, GL_TRUE);
 }
 
+/**
+ * Bind a buffer object to a shader storage block binding point.
+ * As above, but offset = 0.
+ */
 static void
-bind_atomic_buffer(struct gl_context *ctx, unsigned index,
-   struct gl_buffer_object *bufObj, GLintptr offset,
-   GLsizeiptr size)
+bind_buffer_base_atomic_buffer(struct gl_context *ctx,
+   GLuint index,
+   struct gl_buffer_object *bufObj)
 {
-   _mesa_reference_buffer_object(ctx, >AtomicBuffer, bufObj);
-
-   struct gl_atomic_buffer_binding *binding =
-  >AtomicBufferBindings[index];
-   if (binding->BufferObject == bufObj &&
-   binding->Offset == offset &&
-   binding->Size == size) {
+   if (index >= ctx->Const.MaxAtomicBufferBindings) {
+  _mesa_error(ctx, GL_INVALID_VALUE, "glBindBufferBase(index=%d)", index);
   return;
}
 
-   FLUSH_VERTICES(ctx, 0);
-   ctx->NewDriverState |= ctx->DriverFlags.NewAtomicBuffer;
+   _mesa_reference_buffer_object(ctx, >AtomicBuffer, bufObj);
 
-   set_atomic_buffer_binding(ctx, binding, bufObj, offset, size);
+   if (bufObj == ctx->Shared->NullBufferObj)
+  bind_atomic_buffer(ctx, index, bufObj, -1, -1, GL_TRUE);
+   else
+  bind_atomic_buffer(ctx, index, bufObj, 0, 0, GL_TRUE);
 }
 
 /**
@@ -1562,8 +1591,8 @@ delete_buffers(struct gl_context *ctx, GLsizei n, const 
GLuint *ids)
  /* unbind Atomci Buffer binding points */
  for (j = 0; j < ctx->Const.MaxAtomicBufferBindings; j++) {
 if (ctx->AtomicBufferBindings[j].BufferObject == bufObj) {
-   _mesa_BindBufferBase( GL_ATOMIC_COUNTER_BUFFER, j, 0 );
-   bind_atomic_buffer(ctx, j, ctx->Shared->NullBufferObj, 0, 0);
+   bind_buffer_base_atomic_buffer(ctx, j,
+  ctx->Shared->NullBufferObj);
 }
  }
 
@@ -3564,32 +3593,46 @@ bind_buffer_range_shader_storage_buffer_err(struct 
gl_context *ctx,
bind_buffer_range_shader_storage_buffer(ctx, index

[Mesa-dev] [PATCH 3/5] mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

These are 90% the same code, consoldiate them into a couple of
common codepaths.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/bufferobj.c | 146 +++---
 1 file changed, 47 insertions(+), 99 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 7eb7ccf..052a671 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1258,18 +1258,18 @@ _mesa_BindBuffer(GLenum target, GLuint buffer)
 }
 
 /**
- * Binds a buffer object to an atomic buffer binding point.
+ * Binds a buffer object to a binding point.
  *
  * The caller is responsible for validating the offset,
  * flushing the vertices and updating NewDriverState.
  */
 static void
-set_atomic_buffer_binding(struct gl_context *ctx,
-  struct gl_buffer_binding *binding,
-  struct gl_buffer_object *bufObj,
-  GLintptr offset,
-  GLsizeiptr size,
-  bool autoSize)
+set_buffer_binding(struct gl_context *ctx,
+   struct gl_buffer_binding *binding,
+   struct gl_buffer_object *bufObj,
+   GLintptr offset,
+   GLsizeiptr size,
+   bool autoSize, gl_buffer_usage usage)
 {
_mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
 
@@ -1280,67 +1280,38 @@ set_atomic_buffer_binding(struct gl_context *ctx,
 * at some point as an atomic counter buffer.
 */
if (size >= 0)
- bufObj->UsageHistory |= USAGE_ATOMIC_COUNTER_BUFFER;
+  bufObj->UsageHistory |= usage;
 }
 
-/**
- * Binds a buffer object to a uniform buffer binding point.
- *
- * The caller is responsible for flushing vertices and updating
- * NewDriverState.
- */
 static void
-set_ubo_binding(struct gl_context *ctx,
-struct gl_buffer_binding *binding,
-struct gl_buffer_object *bufObj,
-GLintptr offset,
-GLsizeiptr size,
-GLboolean autoSize)
+set_buffer_multi_binding(struct gl_context *ctx,
+ const GLuint *buffers,
+ int idx,
+ const char *caller,
+ struct gl_buffer_binding *binding,
+ GLintptr offset,
+ GLsizeiptr size,
+ bool range,
+ gl_buffer_usage usage)
 {
-   _mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
-
-   binding->Offset = offset;
-   binding->Size = size;
-   binding->AutomaticSize = autoSize;
-
-   /* If this is a real buffer object, mark it has having been used
-* at some point as a UBO.
-*/
-   if (size >= 0)
-  bufObj->UsageHistory |= USAGE_UNIFORM_BUFFER;
-}
-
-/**
- * Binds a buffer object to a shader storage buffer binding point.
- *
- * The caller is responsible for flushing vertices and updating
- * NewDriverState.
- */
-static void
-set_ssbo_binding(struct gl_context *ctx,
- struct gl_buffer_binding *binding,
- struct gl_buffer_object *bufObj,
- GLintptr offset,
- GLsizeiptr size,
- GLboolean autoSize)
-{
-   _mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
-
-   binding->Offset = offset;
-   binding->Size = size;
-   binding->AutomaticSize = autoSize;
+   struct gl_buffer_object *bufObj;
+   if (binding->BufferObject && binding->BufferObject->Name == buffers[idx])
+  bufObj = binding->BufferObject;
+   else
+  bufObj = _mesa_multi_bind_lookup_bufferobj(ctx, buffers, idx, caller);
 
-   /* If this is a real buffer object, mark it has having been used
-* at some point as a SSBO.
-*/
-   if (size >= 0)
-  bufObj->UsageHistory |= USAGE_SHADER_STORAGE_BUFFER;
+   if (bufObj) {
+  if (bufObj == ctx->Shared->NullBufferObj)
+ set_buffer_binding(ctx, binding, bufObj, -1, -1, !range, usage);
+  else
+ set_buffer_binding(ctx, binding, bufObj, offset, size, !range, usage);
+   }
 }
 
 /**
  * Binds a buffer object to a uniform buffer binding point.
  *
- * Unlike set_ubo_binding(), this function also flushes vertices
+ * Unlike set_buffer_binding(), this function also flushes vertices
  * and updates NewDriverState.  It also checks if the binding
  * has actually changed before updating it.
  */
@@ -1365,7 +1336,7 @@ bind_uniform_buffer(struct gl_context *ctx,
FLUSH_VERTICES(ctx, 0);
ctx->NewDriverState |= ctx->DriverFlags.NewUniformBuffer;
 
-   set_ubo_binding(ctx, binding, bufObj, offset, size, autoSize);
+   set_buffer_binding(ctx, binding, bufObj, offset, size, autoSize, 
USAGE_UNIFORM_BUFFER);
 }
 
 /**
@@ -1396,7 +1367,7 @@ bind_shader_storage_buffer(struct gl_context *ctx,
FLUSH_VERTICES(ctx, 0);
  

[Mesa-dev] realign some atomic/ssbo/ubo code

2017-09-14 Thread Dave Airlie
I was digging around the atomic code looking at r600 again,
and noticed this code had some inconsistencies for the 3 codepaths
that should really be the same. There is probably further room
for consolidation here.

This saves 300 bytes in the text segment :-P

Dave.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/5] mesa: rename various buffer bindings to one struct.

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

One binding to bind them all, these are all the same thing.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  6 ++---
 src/mesa/drivers/dri/i965/genX_state_upload.c|  2 +-
 src/mesa/main/bufferobj.c| 18 ++---
 src/mesa/main/mtypes.h   | 33 +++-
 src/mesa/state_tracker/st_atom_atomicbuf.c   |  2 +-
 src/mesa/state_tracker/st_atom_constbuf.c|  2 +-
 src/mesa/state_tracker/st_atom_storagebuf.c  |  2 +-
 7 files changed, 20 insertions(+), 45 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d110482..dae0439 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1279,7 +1279,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct 
gl_program *prog,
   _state->surf_offset[prog_data->binding_table.ubo_start];
 
for (int i = 0; i < prog->info.num_ubos; i++) {
-  struct gl_uniform_buffer_binding *binding =
+  struct gl_buffer_binding *binding =
  >UniformBufferBindings[prog->sh.UniformBlocks[i]->Binding];
 
   if (binding->BufferObject == ctx->Shared->NullBufferObj) {
@@ -1304,7 +1304,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct 
gl_program *prog,
   _state->surf_offset[prog_data->binding_table.ssbo_start];
 
for (int i = 0; i < prog->info.num_ssbos; i++) {
-  struct gl_shader_storage_buffer_binding *binding =
+  struct gl_buffer_binding *binding =
  
>ShaderStorageBufferBindings[prog->sh.ShaderStorageBlocks[i]->Binding];
 
   if (binding->BufferObject == ctx->Shared->NullBufferObj) {
@@ -1386,7 +1386,7 @@ brw_upload_abo_surfaces(struct brw_context *brw,
 
if (prog->info.num_abos) {
   for (unsigned i = 0; i < prog->info.num_abos; i++) {
- struct gl_atomic_buffer_binding *binding =
+ struct gl_buffer_binding *binding =
 >AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding];
  struct intel_buffer_object *intel_bo =
 intel_buffer_object(binding->BufferObject);
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 6127616..54fada7 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3076,7 +3076,7 @@ genX(upload_push_constant_packets)(struct brw_context 
*brw)
 
const struct gl_uniform_block *block =
   prog->sh.UniformBlocks[range->block];
-   const struct gl_uniform_buffer_binding *binding =
+   const struct gl_buffer_binding *binding =
   >UniformBufferBindings[block->Binding];
 
if (binding->BufferObject == ctx->Shared->NullBufferObj) {
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 93b66dc..7eb7ccf 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1265,7 +1265,7 @@ _mesa_BindBuffer(GLenum target, GLuint buffer)
  */
 static void
 set_atomic_buffer_binding(struct gl_context *ctx,
-  struct gl_atomic_buffer_binding *binding,
+  struct gl_buffer_binding *binding,
   struct gl_buffer_object *bufObj,
   GLintptr offset,
   GLsizeiptr size,
@@ -1291,7 +1291,7 @@ set_atomic_buffer_binding(struct gl_context *ctx,
  */
 static void
 set_ubo_binding(struct gl_context *ctx,
-struct gl_uniform_buffer_binding *binding,
+struct gl_buffer_binding *binding,
 struct gl_buffer_object *bufObj,
 GLintptr offset,
 GLsizeiptr size,
@@ -1318,7 +1318,7 @@ set_ubo_binding(struct gl_context *ctx,
  */
 static void
 set_ssbo_binding(struct gl_context *ctx,
- struct gl_shader_storage_buffer_binding *binding,
+ struct gl_buffer_binding *binding,
  struct gl_buffer_object *bufObj,
  GLintptr offset,
  GLsizeiptr size,
@@ -1352,7 +1352,7 @@ bind_uniform_buffer(struct gl_context *ctx,
 GLsizeiptr size,
 GLboolean autoSize)
 {
-   struct gl_uniform_buffer_binding *binding =
+   struct gl_buffer_binding *binding =
   >UniformBufferBindings[index];
 
if (binding->BufferObject == bufObj &&
@@ -1383,7 +1383,7 @@ bind_shader_storage_buffer(struct gl_context *ctx,
GLsizeiptr size,
GLboolean autoSize)
 {
-   struct gl_shader_storage_buffer_binding *binding =
+   struct gl_buffer_binding *binding =
   >ShaderStorage

[Mesa-dev] [PATCH 4/5] mesa/bufferobj: consolidate some buffer binding code.

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

These paths are again 90% the same, consolidate them into
one.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/bufferobj.c | 76 ++-
 1 file changed, 35 insertions(+), 41 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 052a671..fba1f44 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1308,6 +1308,29 @@ set_buffer_multi_binding(struct gl_context *ctx,
}
 }
 
+static void
+bind_buffer(struct gl_context *ctx,
+struct gl_buffer_binding *binding,
+struct gl_buffer_object *bufObj,
+GLintptr offset,
+GLsizeiptr size,
+GLboolean autoSize,
+uint64_t driver_state,
+gl_buffer_usage usage)
+{
+   if (binding->BufferObject == bufObj &&
+   binding->Offset == offset &&
+   binding->Size == size &&
+   binding->AutomaticSize == autoSize) {
+  return;
+   }
+
+   FLUSH_VERTICES(ctx, 0);
+   ctx->NewDriverState |= driver_state;
+
+   set_buffer_binding(ctx, binding, bufObj, offset, size, autoSize, usage);
+}
+
 /**
  * Binds a buffer object to a uniform buffer binding point.
  *
@@ -1323,20 +1346,10 @@ bind_uniform_buffer(struct gl_context *ctx,
 GLsizeiptr size,
 GLboolean autoSize)
 {
-   struct gl_buffer_binding *binding =
-  >UniformBufferBindings[index];
-
-   if (binding->BufferObject == bufObj &&
-   binding->Offset == offset &&
-   binding->Size == size &&
-   binding->AutomaticSize == autoSize) {
-  return;
-   }
-
-   FLUSH_VERTICES(ctx, 0);
-   ctx->NewDriverState |= ctx->DriverFlags.NewUniformBuffer;
-
-   set_buffer_binding(ctx, binding, bufObj, offset, size, autoSize, 
USAGE_UNIFORM_BUFFER);
+   bind_buffer(ctx, >UniformBufferBindings[index],
+   bufObj, offset, size, autoSize,
+   ctx->DriverFlags.NewUniformBuffer,
+   USAGE_UNIFORM_BUFFER);
 }
 
 /**
@@ -1354,20 +1367,10 @@ bind_shader_storage_buffer(struct gl_context *ctx,
GLsizeiptr size,
GLboolean autoSize)
 {
-   struct gl_buffer_binding *binding =
-  >ShaderStorageBufferBindings[index];
-
-   if (binding->BufferObject == bufObj &&
-   binding->Offset == offset &&
-   binding->Size == size &&
-   binding->AutomaticSize == autoSize) {
-  return;
-   }
-
-   FLUSH_VERTICES(ctx, 0);
-   ctx->NewDriverState |= ctx->DriverFlags.NewShaderStorageBuffer;
-
-   set_buffer_binding(ctx, binding, bufObj, offset, size, autoSize, 
USAGE_SHADER_STORAGE_BUFFER);
+   bind_buffer(ctx, >ShaderStorageBufferBindings[index],
+   bufObj, offset, size, autoSize,
+   ctx->DriverFlags.NewShaderStorageBuffer,
+   USAGE_SHADER_STORAGE_BUFFER);
 }
 
 /**
@@ -1382,19 +1385,10 @@ bind_atomic_buffer(struct gl_context *ctx, unsigned 
index,
struct gl_buffer_object *bufObj, GLintptr offset,
GLsizeiptr size, GLboolean autoSize)
 {
-   struct gl_buffer_binding *binding =
-  >AtomicBufferBindings[index];
-   if (binding->BufferObject == bufObj &&
-   binding->Offset == offset &&
-   binding->Size == size &&
-   binding->AutomaticSize == autoSize) {
-  return;
-   }
-
-   FLUSH_VERTICES(ctx, 0);
-   ctx->NewDriverState |= ctx->DriverFlags.NewAtomicBuffer;
-
-   set_buffer_binding(ctx, binding, bufObj, offset, size, autoSize, 
USAGE_ATOMIC_COUNTER_BUFFER);
+   bind_buffer(ctx, >AtomicBufferBindings[index],
+   bufObj, offset, size, autoSize,
+   ctx->DriverFlags.NewAtomicBuffer,
+   USAGE_ATOMIC_COUNTER_BUFFER);
 }
 
 /**
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 5/5] mesa/st: fix atomic buffer sizing to align with ssbo.

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This respects the size from the range setting like ssbo.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/state_tracker/st_atom_atomicbuf.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/state_tracker/st_atom_atomicbuf.c 
b/src/mesa/state_tracker/st_atom_atomicbuf.c
index 7ebcd08..ee5944f 100644
--- a/src/mesa/state_tracker/st_atom_atomicbuf.c
+++ b/src/mesa/state_tracker/st_atom_atomicbuf.c
@@ -62,6 +62,12 @@ st_bind_atomics(struct st_context *st, struct gl_program 
*prog,
  sb.buffer = st_obj->buffer;
  sb.buffer_offset = binding->Offset;
  sb.buffer_size = st_obj->buffer->width0 - binding->Offset;
+
+/* AutomaticSize is FALSE if the buffer was set with BindBufferRange.
+  * Take the minimum just to be sure.
+  */
+ if (!binding->AutomaticSize)
+sb.buffer_size = MIN2(sb.buffer_size, (unsigned) binding->Size);
   }
 
   st->pipe->set_shader_buffers(st->pipe, shader_type,
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] r600: fork and import gallium/radeon

2017-09-14 Thread Dave Airlie
On 15 September 2017 at 02:10, Marek Olšák <mar...@gmail.com> wrote:
> On Thu, Sep 14, 2017 at 4:19 PM, Emil Velikov <emil.l.veli...@gmail.com> 
> wrote:
>> Hi Marek,
>>
>> On 14 September 2017 at 14:06, Marek Olšák <mar...@gmail.com> wrote:
>>> From: Marek Olšák <marek.ol...@amd.com>
>>>
>>> This marks the end of code sharing between r600 and radeonsi.
>>>
>> It has the "what" but it's missing the "why". Can you please add some
>> information.
>>
>> From a quick look which will make each binary ~140KiB larger (dri,
>> omx, vdpau ...). As a reference point drivers/r600 and
>> drivers/radeonsi themselves are around 620KiB and 280KiB respectively.
>>
>> With the bits duplicated/forked, should one `mv radeon{,si}` or you're
>> planning that at a later stage?
>>
>>> A lot of functions had to be renamed to prevent linker conflicts.
>>>
>>> There are also minor cleanups.
>>> ---
>>>
>>> This one is huge. Please review here:
>>> https://cgit.freedesktop.org/~mareko/mesa/commit/?h=master=858b2d1c8cec727fdf750192c8c210f72d38f853
>>>
>> I'll look at those in an hour or so.
>
> The plan is to merge gallium/radeon into radeonsi gradually over a
> longer period of time.
>
> Existing uncommitted work in gallium/radeon should apply more or less
> cleanly, but will only affect radeonsi, not r600,
>

I don't love it, but we've got to drop the ties at some point, and
it's getting less likely we can usefully share.

if only we had addrlib support for r600->ni :-P

Anyways,

Acked-by: Dave Airlie <airl...@redhat.com>

The disk space doesn't concern me.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] Vulkan extensions

2017-09-14 Thread Dave Airlie
On 15 September 2017 at 09:12, Jordan Justen  wrote:
> On 2017-09-14 15:36:10, Romain Failliot wrote:
>> Le 14 sept. 2017 6:11 PM, "Bas Nieuwenhuizen"  a
>> écrit :
>>
>> > For vulkan, because 1.0 is the initial version, there are no
>> > extensions to implement to get to that version, so having an
>> > extensions list would be nonsensical.
>>
>> I don't think it is nonsensical, say the nouveau devs starts to work on a
>> Vulkan 1.0 driver and they'd like to show their progress in features.txt. I
>> think it would be interesting for them to have the list of extensions to
>> implement to be Vulkan 1.0 compliant, so they could flag which extensions
>> are done, in progress or not started.
>
> That would be fine, except I don't think the 1.0 features are bucketed
> into a set of 'extensions'. Right? I thought 1.0 was the baseline, and
> extensions were built upon that.
>

I think Romain missed Bas's point. There is no extension list to get to 1.0.
1.0 is step one. The closest thing is probably the device features list,
and even that you don't expect any device to fill all of it, so what 100% is
differs for every device.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] st/glsl->tgsi: fix u64 to bool comparisons.

2017-09-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Otherwise we end up using a 32-bit comparison which didn't end well.

Timothy caught this while playing around with some opt passes.

Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index cf6e8f8..9b15b61 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -205,6 +205,7 @@ public:
st_src_reg st_src_reg_for_double(double val);
st_src_reg st_src_reg_for_float(float val);
st_src_reg st_src_reg_for_int(int val);
+   st_src_reg st_src_reg_for_int64(int64_t val);
st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
 
/**
@@ -909,6 +910,19 @@ glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
 }
 
 st_src_reg
+glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
+{
+   st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
+   union gl_constant_value uval[2];
+
+   memcpy(uval, , sizeof(uval));
+   src.index = add_constant(src.file, uval, 1, GL_DOUBLE, );
+   src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
+
+   return src;
+}
+
+st_src_reg
 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
 {
if (native_integers)
@@ -2141,7 +2155,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, 
st_src_reg *op)
   break;
}
case ir_unop_i642b:
-  emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], 
st_src_reg_for_int(0));
+  emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], 
st_src_reg_for_int64(0));
   break;
case ir_unop_i642f:
   emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 2/5] amd/common: round cube array slice in ac_prepare_cube_coords

2017-09-13 Thread Dave Airlie
On 14 September 2017 at 03:04, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> The NIR-to-LLVM pass already does this; now the same fix covers
> radeonsi as well.
>
> Fixes various tests of
> dEQP-GLES31.functional.texture.filtering.cube_array.combinations.*

Nice to see you guys catch up, I think I asked about a lot of these workarounds
when I wrote them and didn't get much response :-), other than radeonsi doesn't
need them, looks like it did after all.

Reviewed-by: Dave Airlie <airl...@redhat.com>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] radv/ac: bump params array for image atomic comp swap

2017-09-13 Thread Dave Airlie
On 13 September 2017 at 23:36, Andres Gomez  wrote:
> Hi Dave,
>
> This patch landed tagged for 17.2 only. Was it, then, not nominated for
> 17.1 intentionally ?

Actually good point, this one should be in 17.1 as well.

Thanks,
Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/ac: bump params array for image atomic comp swap

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

For the comp_swap case this was overflowing and crashing
sometimes.

Fixes:
dEQP-VK.image.atomic_operations.compare_exchange.*

Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 22e915d..1388ebd 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3466,7 +3466,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
 {
-   LLVMValueRef params[6];
+   LLVMValueRef params[7];
int param_count = 0;
const nir_variable *var = instr->variables[0]->var;
 
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/gfx9: fix image resource handling.

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

GFX9 changes how images are layed out, so this needs updating.

Fixes: dEQP-VK.query_pool.statistics_query.*

CC: "17.2" <mesa-sta...@lists.freedesktop.org
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 27 +++
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index df28866..46b6205 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1059,23 +1059,34 @@ radv_DestroyImage(VkDevice _device, VkImage _image,
 }
 
 void radv_GetImageSubresourceLayout(
-   VkDevicedevice,
+   VkDevice_device,
VkImage _image,
const VkImageSubresource*   pSubresource,
VkSubresourceLayout*pLayout)
 {
RADV_FROM_HANDLE(radv_image, image, _image);
+   RADV_FROM_HANDLE(radv_device, device, _device);
int level = pSubresource->mipLevel;
int layer = pSubresource->arrayLayer;
struct radeon_surf *surface = >surface;
 
-   pLayout->offset = surface->u.legacy.level[level].offset + 
surface->u.legacy.level[level].slice_size * layer;
-   pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * 
surface->bpe;
-   pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
-   pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
-   pLayout->size = surface->u.legacy.level[level].slice_size;
-   if (image->type == VK_IMAGE_TYPE_3D)
-   pLayout->size *= u_minify(image->info.depth, level);
+   if (device->physical_device->rad_info.chip_class >= GFX9) {
+   pLayout->offset = surface->u.gfx9.offset[level] + 
surface->u.gfx9.surf_slice_size * layer;
+   pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+   pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
+   pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
+   pLayout->size = surface->u.gfx9.surf_slice_size;
+   if (image->type == VK_IMAGE_TYPE_3D)
+   pLayout->size *= u_minify(image->info.depth, level);
+   } else {
+   pLayout->offset = surface->u.legacy.level[level].offset + 
surface->u.legacy.level[level].slice_size * layer;
+   pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * 
surface->bpe;
+   pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
+   pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
+   pLayout->size = surface->u.legacy.level[level].slice_size;
+   if (image->type == VK_IMAGE_TYPE_3D)
+   pLayout->size *= u_minify(image->info.depth, level);
+   }
 }
 
 
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/gfx9: set mip0-depth correctly for 2d arrays/3d images

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This field covers the whole resource.

Fixes:
dEQP-VK.pipeline.image.suballocation.sampling_type.combined.view_type.3d.format.*
dEQP-VK.texture.filtering.3d.combinations.*

Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 6b96a3d..3c512bd 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3094,8 +3094,8 @@ radv_initialise_color_surface(struct radv_device *device,
}
 
if (device->physical_device->rad_info.chip_class >= GFX9) {
-   uint32_t max_slice = radv_surface_layer_count(iview);
-   unsigned mip0_depth = iview->base_layer + max_slice - 1;
+   unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
+ (iview->extent.depth - 1) : (iview->image->info.array_size - 
1);
 
cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

2017-09-12 Thread Dave Airlie
On 13 September 2017 at 13:42, Timothy Arceri <tarc...@itsqueeze.com> wrote:
>
> On 13/09/17 12:57, Dave Airlie wrote:
>>
>> From: Dave Airlie <airl...@redhat.com>
>>
>> With the shaders in the ssao demo, the nir_opt_if wasn't
>> working properly without this, after this the if gets optimised
>> so that loop unrolling gets called.
>>
>> (loop unrolling fails due to instruction count, but at least
>> it gets to do that.)
>>
>> Signed-off-by: Dave Airlie <airl...@redhat.com>
>> ---
>>   src/amd/vulkan/radv_shader.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
>> index 1e25ea3..87deb7c 100644
>> --- a/src/amd/vulkan/radv_shader.c
>> +++ b/src/amd/vulkan/radv_shader.c
>> @@ -129,6 +129,7 @@ radv_optimize_nir(struct nir_shader *shader)
>>   if (nir_opt_trivial_continues(shader)) {
>>   progress = true;
>>   NIR_PASS(progress, shader, nir_copy_prop);
>> +   NIR_PASS(progress, shader, nir_opt_remove_phis);
>
>
> Any reason for not just putting this in the main nir opt loop rather than
> inside this if?

It's already in there.

This is adding it after the second copy_prop.

Dave.
>
>
>>   NIR_PASS(progress, shader, nir_opt_dce);
>>   }
>>   NIR_PASS(progress, shader, nir_opt_if);
>>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/2] [rfc] nir: bump unroll instruction count to 96.

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This gets the ssao demo from 400->440 fps on radv with the
previous patch.

Now the demo does a 0->32 loop across a ubo with 32 members,
I don't know if we still have that sort of information available
about the UBO in question at this stage. Maybe someone more
familiar with spir-v/nir can tell if we can access that info
then we can force a loop unroll like we do for var arrays.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/compiler/nir/nir_opt_loop_unroll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_opt_loop_unroll.c 
b/src/compiler/nir/nir_opt_loop_unroll.c
index 79d04f9..6158d58 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -34,7 +34,7 @@
  * loops that would unroll with GLSL IR fail to unroll if we set this to 25 so
  * we set it to 26.
  */
-#define LOOP_UNROLL_LIMIT 26
+#define LOOP_UNROLL_LIMIT 96
 
 /* Prepare this loop for unrolling by first converting to lcssa and then
  * converting the phis from the loops first block and the block that follows
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

With the shaders in the ssao demo, the nir_opt_if wasn't
working properly without this, after this the if gets optimised
so that loop unrolling gets called.

(loop unrolling fails due to instruction count, but at least
it gets to do that.)

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_shader.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 1e25ea3..87deb7c 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -129,6 +129,7 @@ radv_optimize_nir(struct nir_shader *shader)
 if (nir_opt_trivial_continues(shader)) {
 progress = true;
 NIR_PASS(progress, shader, nir_copy_prop);
+   NIR_PASS(progress, shader, nir_opt_remove_phis);
 NIR_PASS(progress, shader, nir_opt_dce);
 }
 NIR_PASS(progress, shader, nir_opt_if);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] (UNTESTED) virgl: filter out 2D constant file accesses and declarations

2017-09-12 Thread Dave Airlie
On 13 September 2017 at 06:34, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Sorry for the mess.
>
> I suspect something like this patch is needed. Is this sufficient to
> fix the problem?


Oops I missed this, I just posted almost identical patch, and tested mine.

btw this is normal for virgl, I just have to keep an eye out for tgsi
differences.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] virgl: drop const dimensions on first block.

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

The virgl protocol version of tgsi doesn't handle this yet,
transform it back to the old ways.

Fixes: 41e342d5 tgsi/ureg: always emit constants (and their decls) as 2D
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/gallium/drivers/virgl/virgl_tgsi.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_tgsi.c 
b/src/gallium/drivers/virgl/virgl_tgsi.c
index 7ad1cbd..bf5c84c 100644
--- a/src/gallium/drivers/virgl/virgl_tgsi.c
+++ b/src/gallium/drivers/virgl/virgl_tgsi.c
@@ -31,6 +31,24 @@ struct virgl_transform_context {
struct tgsi_transform_context base;
 };
 
+static void
+virgl_tgsi_transform_declaration(struct tgsi_transform_context *ctx,
+ struct tgsi_full_declaration *decl)
+{
+   switch (decl->Declaration.File) {
+   case TGSI_FILE_CONSTANT:
+  if (decl->Declaration.Dimension) {
+ if (decl->Dim.Index2D == 0)
+decl->Declaration.Dimension = 0;
+  }
+  break;
+   default:
+  break;
+   }
+   ctx->emit_declaration(ctx, decl);
+
+}
+
 /* for now just strip out the new properties the remote doesn't understand
yet */
 static void
@@ -54,6 +72,13 @@ virgl_tgsi_transform_instruction(struct 
tgsi_transform_context *ctx,
 {
if (inst->Instruction.Precise)
   inst->Instruction.Precise = 0;
+
+   for (unsigned i = 0; i < TGSI_FULL_MAX_SRC_REGISTERS; i++) {
+  if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT &&
+  inst->Src[i].Register.Dimension &&
+  inst->Src[i].Dimension.Index == 0)
+ inst->Src[i].Register.Dimension = 0;
+   }
ctx->emit_instruction(ctx, inst);
 }
 
@@ -69,6 +94,7 @@ struct tgsi_token *virgl_tgsi_transform(const struct 
tgsi_token *tokens_in)
   return NULL;
 
memset(, 0, sizeof(transform));
+   transform.base.transform_declaration = virgl_tgsi_transform_declaration;
transform.base.transform_property = virgl_tgsi_transform_property;
transform.base.transform_instruction = virgl_tgsi_transform_instruction;
tgsi_transform_shader(tokens_in, new_tokens, newLen, );
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/2] radv: handle GFX9 1D textures

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

As GFX9 can't handle 1D depth textures, radeonsi and
apparantly pro just update all 1D textures to 2D,
and work around it.

This ports the workarounds from radeonsi.

Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 80 +++--
 src/amd/vulkan/radv_image.c | 10 --
 2 files changed, 76 insertions(+), 14 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8f9f771..22e915d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3264,13 +3264,13 @@ static LLVMValueRef get_image_coords(struct 
ac_nir_context *ctx,
 
int count;
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
+   bool is_array = glsl_sampler_type_is_array(type);
bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
  dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
-
-   count = image_type_to_components_count(dim,
-  
glsl_sampler_type_is_array(type));
+   bool gfx9_1d = ctx->abi->chip_class >= GFX9 && dim == 
GLSL_SAMPLER_DIM_1D;
+   count = image_type_to_components_count(dim, is_array);
 
if (is_ms) {
LLVMValueRef fmask_load_address[3];
@@ -3278,7 +3278,7 @@ static LLVMValueRef get_image_coords(struct 
ac_nir_context *ctx,
 
fmask_load_address[0] = 
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
fmask_load_address[1] = 
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
-   if (glsl_sampler_type_is_array(type))
+   if (is_array)
fmask_load_address[2] = 
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
else
fmask_load_address[2] = NULL;
@@ -3297,7 +3297,7 @@ static LLVMValueRef get_image_coords(struct 
ac_nir_context *ctx,
   sample_index,
   
get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
}
-   if (count == 1) {
+   if (count == 1 && !gfx9_1d) {
if (instr->src[0].ssa->num_components)
res = LLVMBuildExtractElement(ctx->ac.builder, src0, 
masks[0], "");
else
@@ -3307,9 +3307,8 @@ static LLVMValueRef get_image_coords(struct 
ac_nir_context *ctx,
if (is_ms)
count--;
for (chan = 0; chan < count; ++chan) {
-   coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, 
src0, masks[chan], "");
+   coords[chan] = llvm_extract_elem(>ac, src0, chan);
}
-
if (add_frag_pos) {
for (chan = 0; chan < 2; ++chan)
coords[chan] = LLVMBuildAdd(ctx->ac.builder, 
coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
@@ -3317,6 +3316,16 @@ static LLVMValueRef get_image_coords(struct 
ac_nir_context *ctx,
coords[2] = ac_to_integer(>ac, 
ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
count++;
}
+
+   if (gfx9_1d) {
+   if (is_array) {
+   coords[2] = coords[1];
+   coords[1] = ctx->ac.i32_0;
+   } else
+   coords[1] = ctx->ac.i32_0;
+   count++;
+   }
+
if (is_ms) {
coords[count] = sample_index;
count++;
@@ -3561,14 +3570,22 @@ static LLVMValueRef visit_image_size(struct 
ac_nir_context *ctx,
 
res = ac_build_image_opcode(>ac, );
 
+   LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
+
if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
glsl_sampler_type_is_array(type)) {
-   LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, 
two, "");
z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
}
+   if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_

[Mesa-dev] [PATCH 1/2] radv: don't use iview for meta image width/height.

2017-09-12 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Work out the width/height from the level manually, as on GFX9
we won't minify the iview width/height.

This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image* on gfx9

Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_meta_blit.c  | 19 ---
 src/amd/vulkan/radv_meta_clear.c | 15 +--
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 3510e87..2c1a132 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -275,15 +275,20 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
VkFilter blit_filter)
 {
struct radv_device *device = cmd_buffer->device;
+   uint32_t src_width = radv_minify(src_iview->image->info.width, 
src_iview->base_mip);
+   uint32_t src_height = radv_minify(src_iview->image->info.height, 
src_iview->base_mip);
+   uint32_t src_depth = radv_minify(src_iview->image->info.depth, 
src_iview->base_mip);
+   uint32_t dst_width = radv_minify(dest_iview->image->info.width, 
dest_iview->base_mip);
+   uint32_t dst_height = radv_minify(dest_iview->image->info.height, 
dest_iview->base_mip);
 
assert(src_image->info.samples == dest_image->info.samples);
 
float vertex_push_constants[5] = {
-   (float)src_offset_0.x / (float)src_iview->extent.width,
-   (float)src_offset_0.y / (float)src_iview->extent.height,
-   (float)src_offset_1.x / (float)src_iview->extent.width,
-   (float)src_offset_1.y / (float)src_iview->extent.height,
-   (float)src_offset_0.z / (float)src_iview->extent.depth,
+   (float)src_offset_0.x / (float)src_width,
+   (float)src_offset_0.y / (float)src_height,
+   (float)src_offset_1.x / (float)src_width,
+   (float)src_offset_1.y / (float)src_height,
+   (float)src_offset_0.z / (float)src_depth,
};
 
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -310,8 +315,8 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
   .pAttachments = (VkImageView[]) {
   
radv_image_view_to_handle(dest_iview),
   },
-  .width = dest_iview->extent.width,
-  .height = dest_iview->extent.height,
+  .width = dst_width,
+  .height = dst_height,
   .layers = 1,
}, _buffer->pool->alloc, );
VkPipeline pipeline;
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index b3eb389..08a6278 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1202,6 +1202,9 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
 {
VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
struct radv_image_view iview;
+   uint32_t width = radv_minify(image->info.width, range->baseMipLevel + 
level);
+   uint32_t height = radv_minify(image->info.height, range->baseMipLevel + 
level);
+
radv_image_view_init(, cmd_buffer->device,
 &(VkImageViewCreateInfo) {
 .sType = 
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
@@ -1225,9 +1228,9 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
   .pAttachments = (VkImageView[]) {
   
radv_image_view_to_handle(),
   },
-  .width = iview.extent.width,
-   .height = 
iview.extent.height,
-   .layers = 1
+  .width = width,
+  .height = height,
+  .layers = 1
   },
   _buffer->pool->alloc,
   );
@@ -1283,8 +1286,8 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
.renderArea = {
.offset = { 0, 0, },
.extent = {
-   .width = 
iview.extent.width,
-

[Mesa-dev] [PATCH 2/6] radv: use upload_data to upload push descriptors.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This is just a reusing code.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 532781b..1a4d88b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1385,18 +1385,15 @@ static void
 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
 {
struct radv_descriptor_set *set = _buffer->push_descriptors.set;
-   uint32_t *ptr = NULL;
unsigned bo_offset;
 
-   if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
- _offset,
- (void**) ))
+   if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
+set->mapped_ptr,
+_offset))
return;
 
set->va = 
cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
set->va += bo_offset;
-
-   memcpy(ptr, set->mapped_ptr, set->size);
 }
 
 static void
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] radv: some ia_multi_vgt_param optimisations. (v2)

2017-09-11 Thread Dave Airlie
Just noticed a bug in the current code, so pushed a patch to fix
that first, then redid the others on top of it.

Dave.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 3/6] radv: only calculate num_prims when required.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index eb8ce3e..d808df2 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -691,7 +691,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
bool ia_switch_on_eoi = false;
bool partial_vs_wave = false;
bool partial_es_wave = false;
-   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
bool multi_instances_smaller_than_primgroup;
 
if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
@@ -699,8 +698,13 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
primgroup_size = 64;  /* recommended with a GS */
 
-   multi_instances_smaller_than_primgroup = indirect_draw || 
(instanced_draw &&
-  num_prims < 
primgroup_size);
+   multi_instances_smaller_than_primgroup = indirect_draw;
+   if (!multi_instances_smaller_than_primgroup && instanced_draw) {
+   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
+   if (num_prims < primgroup_size)
+   multi_instances_smaller_than_primgroup = true;
+   }
+
if 
(cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
ia_switch_on_eoi = true;
 
@@ -808,9 +812,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
 */
if (family == CHIP_HAWAII && ia_switch_on_eoi) {
bool set_vgt_flush = indirect_draw;
-   if (!set_vgt_flush && instanced_draw)
+   if (!set_vgt_flush && instanced_draw) {
+   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
if (num_prims <= 1)
set_vgt_flush = true;
+   }
if (set_vgt_flush)
cmd_buffer->state.flush_bits |= 
RADV_CMD_FLAG_VGT_FLUSH;
}
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 5/6] radv: calculate non-draw related ia_multi_vgt_param bits in pipeline

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This moves a bunch of non-draw dependent calcs into the pipeline code,
to reduce CPU overheads in the draw path.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c | 66 ++
 src/amd/vulkan/radv_private.h  |  6 
 src/amd/vulkan/si_cmd_buffer.c | 64 +++-
 3 files changed, 76 insertions(+), 60 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 590dd67..b95b4f8 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2014,6 +2014,72 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
else
pipeline->graphics.primgroup_size = 128; /* recommended without 
a GS */
 
+   pipeline->graphics.partial_es_wave = false;
+   if (pipeline->device->has_distributed_tess) {
+   if (radv_pipeline_has_gs(pipeline)) {
+   if (device->physical_device->rad_info.chip_class <= VI)
+   pipeline->graphics.partial_es_wave = true;
+   }
+   }
+   /* GS requirement. */
+   if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= 
pipeline->device->gs_table_depth - 3)
+   pipeline->graphics.partial_es_wave = true;
+
+   pipeline->graphics.wd_switch_on_eop = false;
+   if (device->physical_device->rad_info.chip_class >= CIK) {
+   unsigned prim = pipeline->graphics.prim;
+   /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
+* 4 shader engines. Set 1 to pass the assertion below.
+* The other cases are hardware requirements. */
+   if (device->physical_device->rad_info.max_se < 4 ||
+   prim == V_008958_DI_PT_POLYGON ||
+   prim == V_008958_DI_PT_LINELOOP ||
+   prim == V_008958_DI_PT_TRIFAN ||
+   prim == V_008958_DI_PT_TRISTRIP_ADJ ||
+   (pipeline->graphics.prim_restart_enable &&
+(device->physical_device->rad_info.family < CHIP_POLARIS10 
||
+ (prim != V_008958_DI_PT_POINTLIST &&
+  prim != V_008958_DI_PT_LINESTRIP &&
+  prim != V_008958_DI_PT_TRISTRIP
+   pipeline->graphics.wd_switch_on_eop = true;
+   }
+
+   pipeline->graphics.ia_switch_on_eoi = false;
+   if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   if (radv_pipeline_has_gs(pipeline) &&
+   pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   if (radv_pipeline_has_tess(pipeline)) {
+   /* SWITCH_ON_EOI must be set if PrimID is used. */
+   if 
(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
+   
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   }
+
+   pipeline->graphics.partial_vs_wave = false;
+   if (radv_pipeline_has_tess(pipeline)) {
+   /* Bug with tessellation and GS on Bonaire and older 2 SE 
chips. */
+   if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
+device->physical_device->rad_info.family == CHIP_PITCAIRN 
||
+device->physical_device->rad_info.family == CHIP_BONAIRE) 
&&
+   radv_pipeline_has_gs(pipeline))
+   pipeline->graphics.partial_vs_wave = true;
+   /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+   if (device->has_distributed_tess) {
+   if (radv_pipeline_has_gs(pipeline)) {
+   if (device->physical_device->rad_info.family == 
CHIP_TONGA ||
+   device->physical_device->rad_info.family == 
CHIP_FIJI ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS10 ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS11 ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS12)
+   pipeline->graphics.partial_vs_wave = 
true;
+   } else {
+   pipeline->graphics.partial_vs_wave = true;
+   }
+   }
+   }
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struc

[Mesa-dev] [PATCH 1/6] radv: realign vgt flush on hawaii workaround with radeonsi.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This realigns this code with the radeonsi version and fixes
the indirect case to work properly.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 937f231..eb8ce3e 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -802,12 +802,18 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
if (SI_GS_PER_ES / primgroup_size >= 
cmd_buffer->device->gs_table_depth - 3)
partial_es_wave = true;
 
-   /* Hw bug with single-primitive instances and SWITCH_ON_EOI
-* on multi-SE chips. */
-   if (info->max_se >= 2 && ia_switch_on_eoi &&
-   ((instanced_draw || indirect_draw) &&
-num_prims <= 1))
-   cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
+   /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
+* The hw doc says all multi-SE chips are affected, but Vulkan
+* only applies it to Hawaii. Do what Vulkan does.
+*/
+   if (family == CHIP_HAWAII && ia_switch_on_eoi) {
+   bool set_vgt_flush = indirect_draw;
+   if (!set_vgt_flush && instanced_draw)
+   if (num_prims <= 1)
+   set_vgt_flush = true;
+   if (set_vgt_flush)
+   cmd_buffer->state.flush_bits |= 
RADV_CMD_FLAG_VGT_FLUSH;
+   }
}
 
return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 6/6] radv: work out a base ia_multi_vgt_param.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This just reduces the calculations a bit further.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c |  7 +++
 src/amd/vulkan/radv_private.h  |  1 +
 src/amd/vulkan/si_cmd_buffer.c | 15 +--
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b95b4f8..7d07153 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2080,6 +2080,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
}
}
 
+   pipeline->graphics.base_ia_multi_vgt_param =
+   S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
+   /* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
+   
S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI 
? 2 : 0) |
+   
S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= 
GFX9) |
+   
S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = >vertex_elements;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index af3024f..31991a3 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1086,6 +1086,7 @@ struct radv_pipeline {
uint32_t pa_cl_vs_out_cntl;
uint32_t vgt_shader_stages_en;
uint32_t vtx_base_sgpr;
+   uint32_t base_ia_multi_vgt_param;
bool wd_switch_on_eop;
bool ia_switch_on_eoi;
bool partial_vs_wave;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index d7827a0..7b7e26d 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -680,8 +680,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
enum chip_class chip_class = 
cmd_buffer->device->physical_device->rad_info.chip_class;
enum radeon_family family = 
cmd_buffer->device->physical_device->rad_info.family;
struct radeon_info *info = 
_buffer->device->physical_device->rad_info;
-   unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
-   unsigned max_primgroup_in_wave = 2;
+   const unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false;
bool ia_switch_on_eop = false;
@@ -728,6 +727,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
if (ia_switch_on_eoi &&
(family == CHIP_HAWAII ||
 (chip_class == VI &&
+ /* max primgroup in wave is always 2 - leave this for 
documentation */
  (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || 
max_primgroup_in_wave != 2
partial_vs_wave = true;
 
@@ -760,17 +760,12 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
}
}
 
-   return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+   return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
+   S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-   
S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 
1) |
-   S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0) |
-   /* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
-   S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?
-max_primgroup_in_wave : 0) |
-   S_030960_EN_INST_OPT_BASIC(chip_class >= GFX9) |
-   S_030960_EN_INST_OPT_ADV(chip_class >= GFX9);
+   S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0);
 
 }
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 4/6] radv: move calculating primgroup_size to pipeline.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This moves this out of the draw paths.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c |  7 +++
 src/amd/vulkan/radv_private.h  |  1 +
 src/amd/vulkan/si_cmd_buffer.c | 12 +++-
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index acc955f..590dd67 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2007,6 +2007,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
calculate_tess_state(pipeline, pCreateInfo);
}
 
+   if (radv_pipeline_has_tess(pipeline))
+   pipeline->graphics.primgroup_size = 
pipeline->graphics.tess.num_patches;
+   else if (radv_pipeline_has_gs(pipeline))
+   pipeline->graphics.primgroup_size = 64;
+   else
+   pipeline->graphics.primgroup_size = 128; /* recommended without 
a GS */
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = >vertex_elements;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index dd99d7f..c647efd 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1075,6 +1075,7 @@ struct radv_pipeline {
uint32_t vgt_gs_mode;
bool vgt_primitiveid_en;
bool prim_restart_enable;
+   uint8_t primgroup_size;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32];
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index d808df2..794b2fc 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -683,7 +683,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
enum radeon_family family = 
cmd_buffer->device->physical_device->rad_info.family;
struct radeon_info *info = 
_buffer->device->physical_device->rad_info;
unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
-   unsigned primgroup_size = 128; /* recommended without a GS */
unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false;
@@ -693,15 +692,10 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
bool partial_es_wave = false;
bool multi_instances_smaller_than_primgroup;
 
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   primgroup_size = 
cmd_buffer->state.pipeline->graphics.tess.num_patches;
-   else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-   primgroup_size = 64;  /* recommended with a GS */
-
multi_instances_smaller_than_primgroup = indirect_draw;
if (!multi_instances_smaller_than_primgroup && instanced_draw) {
uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
-   if (num_prims < primgroup_size)
+   if (num_prims < 
cmd_buffer->state.pipeline->graphics.primgroup_size)
multi_instances_smaller_than_primgroup = true;
}
 
@@ -803,7 +797,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
ia_switch_on_eoi = true;
 
/* GS requirement. */
-   if (SI_GS_PER_ES / primgroup_size >= 
cmd_buffer->device->gs_table_depth - 3)
+   if (SI_GS_PER_ES / 
cmd_buffer->state.pipeline->graphics.primgroup_size >= 
cmd_buffer->device->gs_table_depth - 3)
partial_es_wave = true;
 
/* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
@@ -826,7 +820,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-   S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+   
S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 
1) |
S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0) |
/* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 4/5] radv: calculate non-draw related ia_multi_vgt_param bits in pipeline

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This moves a bunch of non-draw dependent calcs into the pipeline code,
to reduce CPU overheads in the draw path.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c | 66 ++
 src/amd/vulkan/radv_private.h  |  6 
 src/amd/vulkan/si_cmd_buffer.c | 64 +++-
 3 files changed, 76 insertions(+), 60 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 590dd67..b95b4f8 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2014,6 +2014,72 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
else
pipeline->graphics.primgroup_size = 128; /* recommended without 
a GS */
 
+   pipeline->graphics.partial_es_wave = false;
+   if (pipeline->device->has_distributed_tess) {
+   if (radv_pipeline_has_gs(pipeline)) {
+   if (device->physical_device->rad_info.chip_class <= VI)
+   pipeline->graphics.partial_es_wave = true;
+   }
+   }
+   /* GS requirement. */
+   if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= 
pipeline->device->gs_table_depth - 3)
+   pipeline->graphics.partial_es_wave = true;
+
+   pipeline->graphics.wd_switch_on_eop = false;
+   if (device->physical_device->rad_info.chip_class >= CIK) {
+   unsigned prim = pipeline->graphics.prim;
+   /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
+* 4 shader engines. Set 1 to pass the assertion below.
+* The other cases are hardware requirements. */
+   if (device->physical_device->rad_info.max_se < 4 ||
+   prim == V_008958_DI_PT_POLYGON ||
+   prim == V_008958_DI_PT_LINELOOP ||
+   prim == V_008958_DI_PT_TRIFAN ||
+   prim == V_008958_DI_PT_TRISTRIP_ADJ ||
+   (pipeline->graphics.prim_restart_enable &&
+(device->physical_device->rad_info.family < CHIP_POLARIS10 
||
+ (prim != V_008958_DI_PT_POINTLIST &&
+  prim != V_008958_DI_PT_LINESTRIP &&
+  prim != V_008958_DI_PT_TRISTRIP
+   pipeline->graphics.wd_switch_on_eop = true;
+   }
+
+   pipeline->graphics.ia_switch_on_eoi = false;
+   if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   if (radv_pipeline_has_gs(pipeline) &&
+   pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   if (radv_pipeline_has_tess(pipeline)) {
+   /* SWITCH_ON_EOI must be set if PrimID is used. */
+   if 
(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
+   
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
+   pipeline->graphics.ia_switch_on_eoi = true;
+   }
+
+   pipeline->graphics.partial_vs_wave = false;
+   if (radv_pipeline_has_tess(pipeline)) {
+   /* Bug with tessellation and GS on Bonaire and older 2 SE 
chips. */
+   if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
+device->physical_device->rad_info.family == CHIP_PITCAIRN 
||
+device->physical_device->rad_info.family == CHIP_BONAIRE) 
&&
+   radv_pipeline_has_gs(pipeline))
+   pipeline->graphics.partial_vs_wave = true;
+   /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+   if (device->has_distributed_tess) {
+   if (radv_pipeline_has_gs(pipeline)) {
+   if (device->physical_device->rad_info.family == 
CHIP_TONGA ||
+   device->physical_device->rad_info.family == 
CHIP_FIJI ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS10 ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS11 ||
+   device->physical_device->rad_info.family == 
CHIP_POLARIS12)
+   pipeline->graphics.partial_vs_wave = 
true;
+   } else {
+   pipeline->graphics.partial_vs_wave = true;
+   }
+   }
+   }
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struc

[Mesa-dev] [PATCH 5/5] radv: work out a base ia_multi_vgt_param.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This just reduces the calculations a bit further.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c |  7 +++
 src/amd/vulkan/radv_private.h  |  1 +
 src/amd/vulkan/si_cmd_buffer.c | 15 +--
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b95b4f8..7d07153 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2080,6 +2080,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
}
}
 
+   pipeline->graphics.base_ia_multi_vgt_param =
+   S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
+   /* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
+   
S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI 
? 2 : 0) |
+   
S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= 
GFX9) |
+   
S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = >vertex_elements;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index af3024f..31991a3 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1086,6 +1086,7 @@ struct radv_pipeline {
uint32_t pa_cl_vs_out_cntl;
uint32_t vgt_shader_stages_en;
uint32_t vtx_base_sgpr;
+   uint32_t base_ia_multi_vgt_param;
bool wd_switch_on_eop;
bool ia_switch_on_eoi;
bool partial_vs_wave;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 0e1e89d..031adf6 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -680,8 +680,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
enum chip_class chip_class = 
cmd_buffer->device->physical_device->rad_info.chip_class;
enum radeon_family family = 
cmd_buffer->device->physical_device->rad_info.family;
struct radeon_info *info = 
_buffer->device->physical_device->rad_info;
-   unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
-   unsigned max_primgroup_in_wave = 2;
+   const unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false;
bool ia_switch_on_eop = false;
@@ -728,6 +727,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
if (ia_switch_on_eoi &&
(family == CHIP_HAWAII ||
 (chip_class == VI &&
+ /* max primgroup in wave is always 2 - leave this for 
documentation */
  (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || 
max_primgroup_in_wave != 2
partial_vs_wave = true;
 
@@ -754,17 +754,12 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
}
}
 
-   return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+   return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
+   S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-   
S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 
1) |
-   S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0) |
-   /* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
-   S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?
-max_primgroup_in_wave : 0) |
-   S_030960_EN_INST_OPT_BASIC(chip_class >= GFX9) |
-   S_030960_EN_INST_OPT_ADV(chip_class >= GFX9);
+   S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0);
 
 }
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/5] radv: only calculate num_prims when required.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 937f231..021ab88 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -691,7 +691,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
bool ia_switch_on_eoi = false;
bool partial_vs_wave = false;
bool partial_es_wave = false;
-   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
bool multi_instances_smaller_than_primgroup;
 
if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
@@ -699,8 +698,13 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
primgroup_size = 64;  /* recommended with a GS */
 
-   multi_instances_smaller_than_primgroup = indirect_draw || 
(instanced_draw &&
-  num_prims < 
primgroup_size);
+   multi_instances_smaller_than_primgroup = indirect_draw;
+   if (!multi_instances_smaller_than_primgroup && instanced_draw) {
+   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
+   if (num_prims < primgroup_size)
+   multi_instances_smaller_than_primgroup = true;
+   }
+
if 
(cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
ia_switch_on_eoi = true;
 
@@ -805,9 +809,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
/* Hw bug with single-primitive instances and SWITCH_ON_EOI
 * on multi-SE chips. */
if (info->max_se >= 2 && ia_switch_on_eoi &&
-   ((instanced_draw || indirect_draw) &&
-num_prims <= 1))
-   cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
+   ((instanced_draw || indirect_draw))) {
+   uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
+   if (num_prims <= 1)
+   cmd_buffer->state.flush_bits |= 
RADV_CMD_FLAG_VGT_FLUSH;
+   }
}
 
return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 3/5] radv: move calculating primgroup_size to pipeline.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This moves this out of the draw paths.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_pipeline.c |  7 +++
 src/amd/vulkan/radv_private.h  |  1 +
 src/amd/vulkan/si_cmd_buffer.c | 12 +++-
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index acc955f..590dd67 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2007,6 +2007,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
calculate_tess_state(pipeline, pCreateInfo);
}
 
+   if (radv_pipeline_has_tess(pipeline))
+   pipeline->graphics.primgroup_size = 
pipeline->graphics.tess.num_patches;
+   else if (radv_pipeline_has_gs(pipeline))
+   pipeline->graphics.primgroup_size = 64;
+   else
+   pipeline->graphics.primgroup_size = 128; /* recommended without 
a GS */
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = >vertex_elements;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index dd99d7f..c647efd 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1075,6 +1075,7 @@ struct radv_pipeline {
uint32_t vgt_gs_mode;
bool vgt_primitiveid_en;
bool prim_restart_enable;
+   uint8_t primgroup_size;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32];
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 021ab88..fa1db33 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -683,7 +683,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
enum radeon_family family = 
cmd_buffer->device->physical_device->rad_info.family;
struct radeon_info *info = 
_buffer->device->physical_device->rad_info;
unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
-   unsigned primgroup_size = 128; /* recommended without a GS */
unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false;
@@ -693,15 +692,10 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
bool partial_es_wave = false;
bool multi_instances_smaller_than_primgroup;
 
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   primgroup_size = 
cmd_buffer->state.pipeline->graphics.tess.num_patches;
-   else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-   primgroup_size = 64;  /* recommended with a GS */
-
multi_instances_smaller_than_primgroup = indirect_draw;
if (!multi_instances_smaller_than_primgroup && instanced_draw) {
uint32_t num_prims = 
radv_prims_for_vertices(_buffer->state.pipeline->graphics.prim_vertex_count,
 draw_vertex_count);
-   if (num_prims < primgroup_size)
+   if (num_prims < 
cmd_buffer->state.pipeline->graphics.primgroup_size)
multi_instances_smaller_than_primgroup = true;
}
 
@@ -803,7 +797,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
ia_switch_on_eoi = true;
 
/* GS requirement. */
-   if (SI_GS_PER_ES / primgroup_size >= 
cmd_buffer->device->gs_table_depth - 3)
+   if (SI_GS_PER_ES / 
cmd_buffer->state.pipeline->graphics.primgroup_size >= 
cmd_buffer->device->gs_table_depth - 3)
partial_es_wave = true;
 
/* Hw bug with single-primitive instances and SWITCH_ON_EOI
@@ -820,7 +814,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-   S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+   
S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 
1) |
S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop 
: 0) |
/* The following field was moved to VGT_SHADER_STAGES_EN in 
GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/5] radv: use upload_data to upload push descriptors.

2017-09-11 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This is just a reusing code.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 532781b..1a4d88b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1385,18 +1385,15 @@ static void
 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
 {
struct radv_descriptor_set *set = _buffer->push_descriptors.set;
-   uint32_t *ptr = NULL;
unsigned bo_offset;
 
-   if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
- _offset,
- (void**) ))
+   if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
+set->mapped_ptr,
+_offset))
return;
 
set->va = 
cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
set->va += bo_offset;
-
-   memcpy(ptr, set->mapped_ptr, set->size);
 }
 
 static void
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] radv: some ia_multi_vgt_param optimisations.

2017-09-11 Thread Dave Airlie
These are just some trivial cpu optimisations for the draw path,
I'm sure we could do better than this, but this moves a lot of 
the calculations into the pipeline.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: add debug flags to zero vram allocations.

2017-09-10 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

We are seeing apps that sometimes rely on Windows behaviour, add
a flag to rule out vram zeroing.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_debug.h   | 1 +
 src/amd/vulkan/radv_device.c  | 1 +
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 4 ++--
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 1 +
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h | 1 +
 5 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 18ef7e7..e45c987 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -39,6 +39,7 @@ enum {
RADV_DEBUG_NO_IBS= 0x200,
RADV_DEBUG_DUMP_SPIRV= 0x400,
RADV_DEBUG_VM_FAULTS = 0x800,
+   RADV_DEBUG_ZERO_VRAM = 0x1000,
 };
 
 enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a68278f..6b96a3d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -412,6 +412,7 @@ static const struct debug_control radv_debug_options[] = {
{"noibs", RADV_DEBUG_NO_IBS},
{"spirv", RADV_DEBUG_DUMP_SPIRV},
{"vmfaults", RADV_DEBUG_VM_FAULTS},
+   {"zerovram", RADV_DEBUG_ZERO_VRAM},
{NULL, 0}
 };
 
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index a6941a7..c8b67a0 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -332,8 +332,8 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 
/* this won't do anything on pre 4.9 kernels */
-   if (initial_domain & RADEON_DOMAIN_VRAM)
-   request.flags |= (AMDGPU_GEM_CREATE_VRAM_CLEARED);
+   if (ws->zero_all_vram_allocs && (initial_domain & RADEON_DOMAIN_VRAM))
+   request.flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
r = amdgpu_bo_alloc(ws->dev, , _handle);
if (r) {
fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index a6dedfa..f721964 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -106,6 +106,7 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, 
uint64_t perftest_flags)
if (debug_flags & RADV_DEBUG_NO_IBS)
ws->use_ib_bos = false;
 
+   ws->zero_all_vram_allocs = !!(debug_flags & RADV_DEBUG_ZERO_VRAM);
ws->batchchain = !(perftest_flags & RADV_PERFTEST_NO_BATCHCHAIN);
LIST_INITHEAD(>global_bo_list);
pthread_mutex_init(>global_bo_list_lock, NULL);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
index f84f62c..66c9347 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
@@ -45,6 +45,7 @@ struct radv_amdgpu_winsys {
bool debug_all_bos;
bool batchchain;
bool use_ib_bos;
+   bool zero_all_vram_allocs;
unsigned num_buffers;
 
pthread_mutex_t global_bo_list_lock;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/2] radv/gfx9: allocate events from uncached VA space

2017-09-07 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This copies what amdgpu-pro does, and allocates the memory
for an event with an uncached mtype.

This fixes hangs with:
dEQP-VK.api.command_buffers.record_simul_use_primary

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c  | 2 +-
 src/amd/vulkan/radv_radeon_winsys.h   | 3 ++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 6 +-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7c218b1..bf7552e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2789,7 +2789,7 @@ VkResult radv_CreateEvent(
 
event->bo = device->ws->buffer_create(device->ws, 8, 8,
  RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_VA_UNCACHED | 
RADEON_FLAG_CPU_ACCESS);
if (!event->bo) {
vk_free2(>alloc, pAllocator, event);
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index 8e2ba74..a9c1f54 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -51,7 +51,8 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_GTT_WC =(1 << 0),
RADEON_FLAG_CPU_ACCESS =(1 << 1),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
-   RADEON_FLAG_VIRTUAL =   (1 << 3)
+   RADEON_FLAG_VIRTUAL =   (1 << 3),
+   RADEON_FLAG_VA_UNCACHED =   (1 << 4),
 };
 
 enum radeon_bo_usage { /* bitfield */
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 95290a4..325f875 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -340,7 +340,11 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
goto error_bo_alloc;
}
 
-   r = radv_amdgpu_bo_va_op(ws->dev, buf_handle, 0, size, va, 0, 
AMDGPU_VA_OP_MAP);
+
+   uint32_t va_flags = 0;
+   if (flags & RADEON_FLAG_VA_UNCACHED)
+   va_flags |= AMDGPU_VM_MTYPE_UC;
+   r = radv_amdgpu_bo_va_op(ws->dev, buf_handle, 0, size, va, flags, 
AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/2] radv/winsys: use amdgpu_bo_va_op_raw.

2017-09-07 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This is a precursor to the gfx9 fix to use uncached for the event
memory. Move to the interface which allows setting the flags,
but wrap it to avoid having to copy it around the place.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 31 +--
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 75444d5..95290a4 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -39,6 +39,23 @@
 
 static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo);
 
+static int
+radv_amdgpu_bo_va_op(amdgpu_device_handle dev,
+amdgpu_bo_handle bo,
+uint64_t offset,
+uint64_t size,
+uint64_t addr,
+uint64_t flags,
+uint32_t ops)
+{
+   size = ALIGN(size, getpagesize());
+   flags |= (AMDGPU_VM_PAGE_READABLE |
+ AMDGPU_VM_PAGE_WRITEABLE |
+ AMDGPU_VM_PAGE_EXECUTABLE);
+   return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+  flags, ops);
+}
+
 static void
 radv_amdgpu_winsys_virtual_map(struct radv_amdgpu_winsys_bo *bo,
const struct radv_amdgpu_map_range *range)
@@ -49,8 +66,8 @@ radv_amdgpu_winsys_virtual_map(struct radv_amdgpu_winsys_bo 
*bo,
return; /* TODO: PRT mapping */
 
p_atomic_inc(>bo->ref_count);
-   int r = amdgpu_bo_va_op(range->bo->bo, range->bo_offset, range->size,
-   range->offset + bo->va, 0, AMDGPU_VA_OP_MAP);
+   int r = radv_amdgpu_bo_va_op(bo->ws->dev, range->bo->bo, 
range->bo_offset, range->size,
+range->offset + bo->va, 0, 
AMDGPU_VA_OP_MAP);
if (r)
abort();
 }
@@ -64,8 +81,8 @@ radv_amdgpu_winsys_virtual_unmap(struct radv_amdgpu_winsys_bo 
*bo,
if (!range->bo)
return; /* TODO: PRT mapping */
 
-   int r = amdgpu_bo_va_op(range->bo->bo, range->bo_offset, range->size,
-   range->offset + bo->va, 0, AMDGPU_VA_OP_UNMAP);
+   int r = radv_amdgpu_bo_va_op(bo->ws->dev, range->bo->bo, 
range->bo_offset, range->size,
+range->offset + bo->va, 0, 
AMDGPU_VA_OP_UNMAP);
if (r)
abort();
radv_amdgpu_winsys_bo_destroy((struct radeon_winsys_bo *)range->bo);
@@ -235,7 +252,7 @@ static void radv_amdgpu_winsys_bo_destroy(struct 
radeon_winsys_bo *_bo)
bo->ws->num_buffers--;
pthread_mutex_unlock(>ws->global_bo_list_lock);
}
-   amdgpu_bo_va_op(bo->bo, 0, bo->size, bo->va, 0, 
AMDGPU_VA_OP_UNMAP);
+   radv_amdgpu_bo_va_op(bo->ws->dev, bo->bo, 0, bo->size, bo->va, 
0, AMDGPU_VA_OP_UNMAP);
amdgpu_bo_free(bo->bo);
}
amdgpu_va_range_free(bo->va_handle);
@@ -323,7 +340,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
goto error_bo_alloc;
}
 
-   r = amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP);
+   r = radv_amdgpu_bo_va_op(ws->dev, buf_handle, 0, size, va, 0, 
AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
 
@@ -399,7 +416,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
if (r)
goto error_query;
 
-   r = amdgpu_bo_va_op(result.buf_handle, 0, result.alloc_size, va, 0, 
AMDGPU_VA_OP_MAP);
+   r = radv_amdgpu_bo_va_op(ws->dev, result.buf_handle, 0, 
result.alloc_size, va, 0, AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] radv: use simpler indirect packet 3 if possible.

2017-09-07 Thread Dave Airlie
On 7 Sep. 2017 6:34 pm, "Nicolai Hähnle" <nhaeh...@gmail.com> wrote:

On 07.09.2017 09:58, Bas Nieuwenhuizen wrote:

> I'm not really happy with this,  what happens if a game actually uses
> e.g. indirect count in a secondary cmd buf?
>

Note that some packets that require fetching data in the CP cannot be run
in secondary command buffers, because the data fetching path overlaps with
that used for fetching IB2. I thought this only affects SET_PREDICATION and
OCCLUSION_QUERY though.



Can you check it, it may be multi indirect is busted on some firmwares,
this seems cik specific.

Also is set predication a problem for all Pred setting types?

Dave.


> That said this patch seems correct, so
>
> Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
>
> You may want to nominate this for stable (and provide a backport
> probably..)
>
> On Thu, Sep 7, 2017, at 05:03, Dave Airlie wrote:
>
>> From: Dave Airlie <airl...@redhat.com>
>>
>> This fixes some observed hangs on CIK GPUs.
>>
>> Signed-off-by: Dave Airlie <airl...@redhat.com>
>> ---
>>   src/amd/vulkan/radv_cmd_buffer.c | 37
>>   +++--
>>   1 file changed, 23 insertions(+), 14 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
>> b/src/amd/vulkan/radv_cmd_buffer.c
>> index b372123..bc4aeb3 100644
>> --- a/src/amd/vulkan/radv_cmd_buffer.c
>> +++ b/src/amd/vulkan/radv_cmd_buffer.c
>> @@ -2834,20 +2834,29 @@ radv_cs_emit_indirect_draw_packet(struct
>> radv_cmd_buffer *cmd_buffer,
>> uint32_t base_reg = cmd_buffer->state.pipeline->gr
>> aphics.vtx_base_sgpr;
>> assert(base_reg);
>>   -   radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
>> -  PKT3_DRAW_INDIRECT_MULTI,
>> -8, false));
>> -   radeon_emit(cs, 0);
>> -   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
>> -   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
>> -   radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
>> -   S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
>> -   S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
>> -   radeon_emit(cs, draw_count); /* count */
>> -   radeon_emit(cs, count_va); /* count_addr */
>> -   radeon_emit(cs, count_va >> 32);
>> -   radeon_emit(cs, stride); /* stride */
>> -   radeon_emit(cs, di_src_sel);
>> +   if (draw_count == 1 && !count_va && !draw_id_enable) {
>> +   radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
>> +PKT3_DRAW_INDIRECT, 3, false));
>> +   radeon_emit(cs, 0);
>> +   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
>> +   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >>
>> 2);
>> +   radeon_emit(cs, di_src_sel);
>> +   } else {
>> +   radeon_emit(cs, PKT3(indexed ?
>> PKT3_DRAW_INDEX_INDIRECT_MULTI :
>> +PKT3_DRAW_INDIRECT_MULTI,
>> +8, false));
>> +   radeon_emit(cs, 0);
>> +   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
>> +   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >>
>> 2);
>> +   radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >>
>> 2) |
>> +   S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
>> +   S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
>> +   radeon_emit(cs, draw_count); /* count */
>> +   radeon_emit(cs, count_va); /* count_addr */
>> +   radeon_emit(cs, count_va >> 32);
>> +   radeon_emit(cs, stride); /* stride */
>> +   radeon_emit(cs, di_src_sel);
>> +   }
>>   }
>> static void
>> --
>> 2.9.4
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>

-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/gfx9: allocate events from uncached VA space

2017-09-06 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This copies what amdgpu-pro does, and allocates the memory
for an event with an uncached mtype.

This fixes hangs with:
dEQP-VK.api.command_buffers.record_simul_use_primary

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c  | 2 +-
 src/amd/vulkan/radv_radeon_winsys.h   | 3 ++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 9 -
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 0b25469..12f6fe6 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2793,7 +2793,7 @@ VkResult radv_CreateEvent(
 
event->bo = device->ws->buffer_create(device->ws, 8, 8,
  RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_VA_UNCACHED | 
RADEON_FLAG_CPU_ACCESS);
if (!event->bo) {
vk_free2(>alloc, pAllocator, event);
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index 8e2ba74..a9c1f54 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -51,7 +51,8 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_GTT_WC =(1 << 0),
RADEON_FLAG_CPU_ACCESS =(1 << 1),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
-   RADEON_FLAG_VIRTUAL =   (1 << 3)
+   RADEON_FLAG_VIRTUAL =   (1 << 3),
+   RADEON_FLAG_VA_UNCACHED =   (1 << 4),
 };
 
 enum radeon_bo_usage { /* bitfield */
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 75444d5..0af5a39 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -323,7 +323,14 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
goto error_bo_alloc;
}
 
-   r = amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP);
+   uint32_t raw_flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE 
|
+   AMDGPU_VM_PAGE_EXECUTABLE;
+   if (flags & RADEON_FLAG_VA_UNCACHED)
+   raw_flags |= AMDGPU_VM_MTYPE_UC;
+
+   size = ALIGN(size, getpagesize());
+
+   r = amdgpu_bo_va_op_raw(ws->dev, buf_handle, 0, size, va, raw_flags, 
AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
 
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: use simpler indirect packet 3 if possible.

2017-09-06 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This fixes some observed hangs on CIK GPUs.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 37 +++--
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b372123..bc4aeb3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2834,20 +2834,29 @@ radv_cs_emit_indirect_draw_packet(struct 
radv_cmd_buffer *cmd_buffer,
uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
assert(base_reg);
 
-   radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
-  PKT3_DRAW_INDIRECT_MULTI,
-8, false));
-   radeon_emit(cs, 0);
-   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
-   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
-   radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
-   S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
-   S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
-   radeon_emit(cs, draw_count); /* count */
-   radeon_emit(cs, count_va); /* count_addr */
-   radeon_emit(cs, count_va >> 32);
-   radeon_emit(cs, stride); /* stride */
-   radeon_emit(cs, di_src_sel);
+   if (draw_count == 1 && !count_va && !draw_id_enable) {
+   radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
+PKT3_DRAW_INDIRECT, 3, false));
+   radeon_emit(cs, 0);
+   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
+   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
+   radeon_emit(cs, di_src_sel);
+   } else {
+   radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
+PKT3_DRAW_INDIRECT_MULTI,
+8, false));
+   radeon_emit(cs, 0);
+   radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
+   radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
+   radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
+   S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
+   S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
+   radeon_emit(cs, draw_count); /* count */
+   radeon_emit(cs, count_va); /* count_addr */
+   radeon_emit(cs, count_va >> 32);
+   radeon_emit(cs, stride); /* stride */
+   radeon_emit(cs, di_src_sel);
+   }
 }
 
 static void
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] nir: put compact into bitfields in nir_variable_data

2017-09-05 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This being declared bool means it won't get merged with the previous
bitfields, this seems like an oversight rather than deliberate.

Noticed when running pahole.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/compiler/nir/nir.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9313b7ac90..8330e6d7ce 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -220,7 +220,7 @@ typedef struct nir_variable {
* be tightly packed.  In other words, consecutive array elements
* should be stored one component apart, rather than one slot apart.
*/
-  bool compact:1;
+  unsigned compact:1;
 
   /**
* Whether this is a fragment shader output implicitly initialized with
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] mesa/mtypes: repack gl_texture_object.

2017-09-05 Thread Dave Airlie
On 6 September 2017 at 03:11, Marek Olšák <mar...@gmail.com> wrote:
> On Tue, Sep 5, 2017 at 5:50 PM, Brian Paul <bri...@vmware.com> wrote:
>> On 09/04/2017 05:29 AM, Marek Olšák wrote:
>>>
>>> On Sun, Sep 3, 2017 at 1:18 PM, Dave Airlie <airl...@gmail.com> wrote:
>>>>
>>>> From: Dave Airlie <airl...@redhat.com>
>>>>
>>>> reduces size from 1144 to 1128.
>>>>
>>>> Signed-off-by: Dave Airlie <airl...@redhat.com>
>>>> ---
>>>>   src/mesa/main/mtypes.h | 10 +-
>>>>   1 file changed, 5 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
>>>> index d44897b..3d68a6d 100644
>>>> --- a/src/mesa/main/mtypes.h
>>>> +++ b/src/mesa/main/mtypes.h
>>>> @@ -1012,7 +1012,6 @@ struct gl_texture_object
>>>>  struct gl_sampler_object Sampler;
>>>>
>>>>  GLenum DepthMode;   /**< GL_ARB_depth_texture */
>>>
>>>
>>> The patch looks good, but here are some ideas for future improvements:
>>>
>>> GLenum can be uint16_t everywhere, because GL doesn't set higher bits:
>>>
>>> typedef uint16_t GLenum16.
>>> s/GLenum/GLenum16/
>>>
>>>> -   bool StencilSampling;   /**< Should we sample stencil instead of
>>>> depth? */
>>>>
>>>>  GLfloat Priority;   /**< in [0,1] */
>>>>  GLint BaseLevel;/**< min mipmap level, OpenGL 1.2 */
>>>> @@ -1033,12 +1032,17 @@ struct gl_texture_object
>>>>  GLboolean Immutable;/**< GL_ARB_texture_storage */
>>>>  GLboolean _IsFloat; /**< GL_OES_float_texture */
>>>>  GLboolean _IsHalfFloat; /**< GL_OES_half_float_texture */
>>>> +   bool StencilSampling;   /**< Should we sample stencil instead of
>>>> depth? */
>>>> +   bool HandleAllocated;   /**< GL_ARB_bindless_texture */
>>>
>>>
>>> All bools can be 1 bit:
>>>
>>> bool x:1;
>>> GLboolean y:1;
>>>
>>> etc.
>>>
>>>>
>>>>  GLuint MinLevel;/**< GL_ARB_texture_view */
>>>>  GLuint MinLayer;/**< GL_ARB_texture_view */
>>>>  GLuint NumLevels;   /**< GL_ARB_texture_view */
>>>>  GLuint NumLayers;   /**< GL_ARB_texture_view */
>>>
>>>
>>> MinLevel, NumLevels can be ubyte (uint8_t). MinLayer, NumLayers can be
>>> ushort (uint16_t)... simply by considering the range of possible
>>> values.
>>
>>
>> There's lots of opportunities along these lines in gl_texture_image. And
>> since we often have many gl_texture_images per gl_texture_object, and we
>> often have many textures, it'll probably have considerable impact.  I've
>> suggested this in the past but never got around to working on it.
>>
>> I recall Eric Anholt mentioning a memory profiling tool that was helpful for
>> finding wasted space in structures, etc.  I don't recall the name right now.
>> Eric?
>
> Dave used pahole for this patch series too. It can't obviously suggest
> what I suggested above (like changing the types and bits).

Yup this was pahole, doing what Marek describes is definitely something
that can be done, but needs a lot more care and attention.

Replacing bool with unsigned :1 fields isn't always a win, as you then
have a mask/shift on the accesses so overall may end up slowing things
down, and increasing instruction count etc.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] mesa/mtypes: repack gl_texture_object.

2017-09-03 Thread Dave Airlie
On 3 September 2017 at 21:22, Thomas Helland <thomashellan...@gmail.com> wrote:
> 2017-09-03 13:18 GMT+02:00 Dave Airlie <airl...@gmail.com>:
>> From: Dave Airlie <airl...@redhat.com>
>>
>> reduces size from 1144 to 1128.
>>
>> Signed-off-by: Dave Airlie <airl...@redhat.com>
>> ---
>>  src/mesa/main/mtypes.h | 10 +-
>>  1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
>> index d44897b..3d68a6d 100644
>> --- a/src/mesa/main/mtypes.h
>> +++ b/src/mesa/main/mtypes.h
>> @@ -1012,7 +1012,6 @@ struct gl_texture_object
>> struct gl_sampler_object Sampler;
>>
>> GLenum DepthMode;   /**< GL_ARB_depth_texture */
>> -   bool StencilSampling;   /**< Should we sample stencil instead of 
>> depth? */
>>
>> GLfloat Priority;   /**< in [0,1] */
>> GLint BaseLevel;/**< min mipmap level, OpenGL 1.2 */
>> @@ -1033,12 +1032,17 @@ struct gl_texture_object
>> GLboolean Immutable;/**< GL_ARB_texture_storage */
>> GLboolean _IsFloat; /**< GL_OES_float_texture */
>> GLboolean _IsHalfFloat; /**< GL_OES_half_float_texture */
>> +   bool StencilSampling;   /**< Should we sample stencil instead of 
>> depth? */
>> +   bool HandleAllocated;   /**< GL_ARB_bindless_texture */
>>
>
> Maybe we could use "pragma pack" here instead?
> I'm debating with myself whether or not moving this
> bool away from the rest of the bindless_texture related
> variables is worth saving the few bytes.

You don't ever want pragma pack for this. As that will force a
uint32_t after a bool to be misaligned,
which would suck for everyone.

Saving 7 bytes of pointless padding at the end of a struct that gets
allocated quite a lot by GL applications,
seems worth it for me. gl_texture_object is probably one of the most
allocated application object structs.

Dave.

>
>> GLuint MinLevel;/**< GL_ARB_texture_view */
>> GLuint MinLayer;/**< GL_ARB_texture_view */
>> GLuint NumLevels;   /**< GL_ARB_texture_view */
>> GLuint NumLayers;   /**< GL_ARB_texture_view */
>>
>> +   /** GL_EXT_memory_object */
>> +   GLenum TextureTiling;
>> +
>> /** Actual texture images, indexed by [cube face] and [mipmap level] */
>> struct gl_texture_image *Image[MAX_FACES][MAX_TEXTURE_LEVELS];
>>
>> @@ -1057,13 +1061,9 @@ struct gl_texture_object
>> /** GL_ARB_shader_image_load_store */
>> GLenum ImageFormatCompatibilityType;
>>
>> -   /** GL_EXT_memory_object */
>> -   GLenum TextureTiling;
>> -
>> /** GL_ARB_bindless_texture */
>> struct util_dynarray SamplerHandles;
>> struct util_dynarray ImageHandles;
>> -   bool HandleAllocated;
>>  };
>>
>>
>> --
>> 2.9.5
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] mesa/mtypes: repack gl_sampler_object.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

160->152.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 3d68a6d..db9ea76 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -990,8 +990,8 @@ struct gl_sampler_object
GLboolean CubeMapSeamless;   /**< GL_AMD_seamless_cubemap_per_texture */
 
/** GL_ARB_bindless_texture */
-   struct util_dynarray Handles;
bool HandleAllocated;
+   struct util_dynarray Handles;
 };
 
 
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] mesa/mtypes: repack gl_texture_object.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

reduces size from 1144 to 1128.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index d44897b..3d68a6d 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1012,7 +1012,6 @@ struct gl_texture_object
struct gl_sampler_object Sampler;
 
GLenum DepthMode;   /**< GL_ARB_depth_texture */
-   bool StencilSampling;   /**< Should we sample stencil instead of depth? 
*/
 
GLfloat Priority;   /**< in [0,1] */
GLint BaseLevel;/**< min mipmap level, OpenGL 1.2 */
@@ -1033,12 +1032,17 @@ struct gl_texture_object
GLboolean Immutable;/**< GL_ARB_texture_storage */
GLboolean _IsFloat; /**< GL_OES_float_texture */
GLboolean _IsHalfFloat; /**< GL_OES_half_float_texture */
+   bool StencilSampling;   /**< Should we sample stencil instead of depth? 
*/
+   bool HandleAllocated;   /**< GL_ARB_bindless_texture */
 
GLuint MinLevel;/**< GL_ARB_texture_view */
GLuint MinLayer;/**< GL_ARB_texture_view */
GLuint NumLevels;   /**< GL_ARB_texture_view */
GLuint NumLayers;   /**< GL_ARB_texture_view */
 
+   /** GL_EXT_memory_object */
+   GLenum TextureTiling;
+
/** Actual texture images, indexed by [cube face] and [mipmap level] */
struct gl_texture_image *Image[MAX_FACES][MAX_TEXTURE_LEVELS];
 
@@ -1057,13 +1061,9 @@ struct gl_texture_object
/** GL_ARB_shader_image_load_store */
GLenum ImageFormatCompatibilityType;
 
-   /** GL_EXT_memory_object */
-   GLenum TextureTiling;
-
/** GL_ARB_bindless_texture */
struct util_dynarray SamplerHandles;
struct util_dynarray ImageHandles;
-   bool HandleAllocated;
 };
 
 
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] mesa/mtypes: reback gl_shader_program_data.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This reduces the size from 144 bytes to 128 bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2dab594..d44897b 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2853,9 +2853,9 @@ struct gl_shader_program_data
struct gl_uniform_storage *UniformStorage;
 
unsigned NumUniformBlocks;
-   struct gl_uniform_block *UniformBlocks;
-
unsigned NumShaderStorageBlocks;
+
+   struct gl_uniform_block *UniformBlocks;
struct gl_uniform_block *ShaderStorageBlocks;
 
struct gl_active_atomic_buffer *AtomicBuffers;
@@ -2873,13 +2873,13 @@ struct gl_shader_program_data
 * lands we should switch to using the cache_fallback support.
 */
bool skip_cache;
+   GLboolean Validated;
 
/** List of all active resources after linking. */
struct gl_program_resource *ProgramResourceList;
unsigned NumProgramResourceList;
 
enum gl_link_status LinkStatus;   /**< GL_LINK_STATUS */
-   GLboolean Validated;
GLchar *InfoLog;
 
unsigned Version;   /**< GLSL version used for linking */
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] mesa/mtypes: reorganise gl_shader

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This reduces this from 200->182 bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 34da6b9..2dab594 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2567,9 +2567,10 @@ struct gl_shader
GLchar *Label;   /**< GL_KHR_debug */
unsigned char sha1[20]; /**< SHA1 hash of pre-processed source */
GLboolean DeletePending;
-   enum gl_compile_status CompileStatus;
bool IsES;  /**< True if this shader uses GLSL ES */
 
+   enum gl_compile_status CompileStatus;
+
 #ifdef DEBUG
unsigned SourceChecksum;   /**< for debug/logging purposes */
 #endif
@@ -2581,14 +2582,14 @@ struct gl_shader
 
unsigned Version;   /**< GLSL version used for linking */
 
-   struct exec_list *ir;
-   struct glsl_symbol_table *symbols;
-
/**
 * A bitmask of gl_advanced_blend_mode values
 */
GLbitfield BlendSupport;
 
+   struct exec_list *ir;
+   struct glsl_symbol_table *symbols;
+
/**
 * Whether early fragment tests are enabled as defined by
 * ARB_shader_image_load_store.
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 3/3] mesa/mtypes: repack display list structs.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This reduces each of these by 8 bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index a72a3b2..34da6b9 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4342,8 +4342,8 @@ union gl_dlist_node;
 struct gl_display_list
 {
GLuint Name;
-   GLchar *Label; /**< GL_KHR_debug */
GLbitfield Flags;  /**< DLIST_x flags */
+   GLchar *Label; /**< GL_KHR_debug */
/** The dlist commands are in a linked list of nodes */
union gl_dlist_node *Head;
 };
@@ -4354,11 +4354,10 @@ struct gl_display_list
  */
 struct gl_dlist_state
 {
-   GLuint CallDepth;   /**< Current recursion calling depth */
-
struct gl_display_list *CurrentList; /**< List currently being compiled */
union gl_dlist_node *CurrentBlock; /**< Pointer to current block of nodes */
GLuint CurrentPos;  /**< Index into current block of nodes */
+   GLuint CallDepth;   /**< Current recursion calling depth */
 
GLvertexformat ListVtxfmt;
 
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/3] mesa/mtypes: reduce size of gl_sync_object.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Drops from 40->32 bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 7f9c30f..a72a3b2 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3192,8 +3192,8 @@ struct gl_query_state
 struct gl_sync_object
 {
GLuint Name;   /**< Fence name */
-   GLchar *Label; /**< GL_KHR_debug */
GLint RefCount;/**< Reference count */
+   GLchar *Label; /**< GL_KHR_debug */
GLboolean DeletePending;   /**< Object was deleted while there were still
   * live references (e.g., sync not yet finished)
   */
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/3] mesa/mtypes: reorg vertex/fragment program state.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

reduces both of these by 8 bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index ac75ee5..7f9c30f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2256,6 +2256,9 @@ struct gl_vertex_program_state
GLboolean Enabled;/**< User-set GL_VERTEX_PROGRAM_ARB/NV flag */
GLboolean PointSizeEnabled;   /**< GL_VERTEX_PROGRAM_POINT_SIZE_ARB/NV */
GLboolean TwoSideEnabled; /**< GL_VERTEX_PROGRAM_TWO_SIDE_ARB/NV */
+   /** Should fixed-function T be implemented with a vertex prog? */
+   GLboolean _MaintainTnlProgram;
+
struct gl_program *Current;  /**< User-bound vertex program */
 
/** Currently enabled and valid vertex program (including internal
@@ -2266,9 +2269,6 @@ struct gl_vertex_program_state
 
GLfloat Parameters[MAX_PROGRAM_ENV_PARAMS][4]; /**< Env params */
 
-   /** Should fixed-function T be implemented with a vertex prog? */
-   GLboolean _MaintainTnlProgram;
-
/** Program to emulate fixed-function T (see above) */
struct gl_program *_TnlProgram;
 
@@ -2317,6 +2317,9 @@ struct gl_geometry_program_state
 struct gl_fragment_program_state
 {
GLboolean Enabled; /**< User-set fragment program enable flag */
+   /** Should fixed-function texturing be implemented with a fragment prog? */
+   GLboolean _MaintainTexEnvProgram;
+
struct gl_program *Current;  /**< User-bound fragment program */
 
/** Currently enabled and valid fragment program (including internal
@@ -2327,9 +2330,6 @@ struct gl_fragment_program_state
 
GLfloat Parameters[MAX_PROGRAM_ENV_PARAMS][4]; /**< Env params */
 
-   /** Should fixed-function texturing be implemented with a fragment prog? */
-   GLboolean _MaintainTexEnvProgram;
-
/** Program to emulate fixed-function texture env/combine (see above) */
struct gl_program *_TexEnvProgram;
 
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 2/3] ac: reorg ac_shader_binary struct to take less space.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This reduces the size from 96 to 80 bytes but putting all the
32-bit sizes at the start.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_binary.h | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index 45f554e..f81b821 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -36,31 +36,32 @@ struct ac_shader_reloc {
 };
 
 struct ac_shader_binary {
+   unsigned code_size;
+   unsigned config_size;
+   /** The number of bytes of config information for each global symbol.
+*/
+   unsigned config_size_per_symbol;
+   unsigned rodata_size;
+   unsigned global_symbol_count;
+   unsigned reloc_count;
+
/** Shader code */
unsigned char *code;
-   unsigned code_size;
 
/** Config/Context register state that accompanies this shader.
 * This is a stream of dword pairs.  First dword contains the
 * register address, the second dword contains the value.*/
unsigned char *config;
-   unsigned config_size;
 
-   /** The number of bytes of config information for each global symbol.
-*/
-   unsigned config_size_per_symbol;
 
/** Constant data accessed by the shader.  This will be uploaded
 * into a constant buffer. */
unsigned char *rodata;
-   unsigned rodata_size;
 
/** List of symbol offsets for the shader */
uint64_t *global_symbol_offsets;
-   unsigned global_symbol_count;
 
struct ac_shader_reloc *relocs;
-   unsigned reloc_count;
 
/** Disassembled shader in a string. */
char *disasm_string;
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 3/3] mesa/bindless: reorder gl_bindless_image gl_bindless_sampler.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This makes these use 16-bytes instead of 24-bytes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/mesa/main/mtypes.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 1913567..ac75ee5 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2000,12 +2000,12 @@ struct gl_bindless_sampler
/** Texture unit (set by glUniform1()). */
GLubyte unit;
 
-   /** Texture Target (TEXTURE_1D/2D/3D/etc_INDEX). */
-   gl_texture_index target;
-
/** Whether this bindless sampler is bound to a unit. */
GLboolean bound;
 
+   /** Texture Target (TEXTURE_1D/2D/3D/etc_INDEX). */
+   gl_texture_index target;
+
/** Pointer to the base of the data. */
GLvoid *data;
 };
@@ -2018,12 +2018,12 @@ struct gl_bindless_image
/** Image unit (set by glUniform1()). */
GLubyte unit;
 
-   /** Access qualifier (GL_READ_WRITE, GL_READ_ONLY, GL_WRITE_ONLY) */
-   GLenum access;
-
/** Whether this bindless image is bound to a unit. */
GLboolean bound;
 
+   /** Access qualifier (GL_READ_WRITE, GL_READ_ONLY, GL_WRITE_ONLY) */
+   GLenum access;
+
/** Pointer to the base of the data. */
GLvoid *data;
 };
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/3] radv: drop emit2d_dst_type.

2017-09-03 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This is completely unused now.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_meta_blit2d.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index 79e76be..6763384 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -28,22 +28,6 @@
 #include "nir/nir_builder.h"
 #include "vk_format.h"
 
-enum blit2d_dst_type {
-   /* We can bind this destination as a "normal" render target and render
-* to it just like you would anywhere else.
-*/
-   BLIT2D_DST_TYPE_NORMAL,
-
-   /* The destination has a 3-channel RGB format.  Since we can't render to
-* non-power-of-two textures, we have to bind it as a red texture and
-* select the correct component for the given red pixel in the shader.
-*/
-   BLIT2D_DST_TYPE_RGB,
-
-   BLIT2D_NUM_DST_TYPES,
-};
-
-
 enum blit2d_src_type {
BLIT2D_SRC_TYPE_IMAGE,
BLIT2D_SRC_TYPE_BUFFER,
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 3/3] radv: Add trace ids for secondary buffers.

2017-08-28 Thread Dave Airlie
Nice, I started reinventing the same wheel yesterday so this is 90% of
what I had done, but right.

The only other thing I did was tie secondary execution into the
primary for lookups instead of debug all bos.

Once this lands I might clean that up if we want it.

Otherwise, for all 3
Reviewed-by: Dave Airlie <airl...@redhat.com>

On 29 August 2017 at 07:30, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote:
> Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c  | 2 ++
>  src/amd/vulkan/radv_device.c  | 2 +-
>  src/amd/vulkan/radv_radeon_winsys.h   | 2 +-
>  src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 4 ++--
>  4 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index e1249641917..12209d1dbdb 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -341,6 +341,8 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer 
> *cmd_buffer)
> return;
>
> va = device->ws->buffer_get_va(device->trace_bo);
> +   if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
> +   va += 4;
>
> MAYBE_UNUSED unsigned cdw_max = 
> radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index fec965c6225..1e3148a0432 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -1389,7 +1389,7 @@ static void radv_dump_trace(struct radv_device *device,
> }
>
> fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
> -   device->ws->cs_dump(cs, f, *device->trace_id_ptr);
> +   device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
> fclose(f);
>  }
>
> diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
> b/src/amd/vulkan/radv_radeon_winsys.h
> index 215ef0bfc15..8e2ba7431a7 100644
> --- a/src/amd/vulkan/radv_radeon_winsys.h
> +++ b/src/amd/vulkan/radv_radeon_winsys.h
> @@ -216,7 +216,7 @@ struct radeon_winsys {
> void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
> struct radeon_winsys_cs *child);
>
> -   void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t 
> trace_id);
> +   void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int 
> *trace_ids, int trace_id_count);
>
> int (*surface_init)(struct radeon_winsys *ws,
> const struct ac_surf_info *surf_info,
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
> b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> index 49c9c909466..4a9ecab657f 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> @@ -987,7 +987,7 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, 
> uint64_t addr)
>
>  static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
> FILE* file,
> -   uint32_t trace_id)
> +   const int *trace_ids, int 
> trace_id_count)
>  {
> struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
> void *ib = cs->base.buf;
> @@ -998,7 +998,7 @@ static void radv_amdgpu_winsys_cs_dump(struct 
> radeon_winsys_cs *_cs,
> num_dw = cs->ib.size;
> }
> assert(ib);
> -   ac_parse_ib(file, ib, num_dw, (const int*)_id, 1,  "main IB",
> +   ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count,  "main IB",
> cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, 
> cs);
>  }
>
> --
> 2.14.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/gfx9: fix buffer size on gfx9.

2017-08-24 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

The VI sizing only applies to VI.

This fixes:
dEQP-VK.image.image_size.buffer.*

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cdfbff2..dd5ed1d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2012,7 +2012,7 @@ get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef 
descriptor, bool in_ele
LLVMConstInt(ctx->ac.i32, 2, false), 
"");
 
/* VI only */
-   if (ctx->abi->chip_class >= VI && in_elements) {
+   if (ctx->abi->chip_class == VI && in_elements) {
/* On VI, the descriptor contains the size in bytes,
 * but TXQ must return the size in elements.
 * The stride is always non-zero for resources using TXQ.
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv/gfx9: gfx9 has buffer sizing rules like pre-VI.

2017-08-24 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This fixes:
dEQP-VK.robustness.buffer_access.* on GFX9.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f561919..560d90e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -186,7 +186,7 @@ radv_make_buffer_descriptor(struct radv_device *device,
state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(stride);
 
-   if (device->physical_device->rad_info.chip_class < VI && stride) {
+   if (device->physical_device->rad_info.chip_class != VI && stride) {
range /= stride;
}
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: fix predication on gfx9

2017-08-24 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

When I added gfx9 I did it wrong, this fixes it.

Fixes: 5247b311e9 "radv/gfx9: fix set predication packet."
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 913ec0e..ef4f926 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1133,8 +1133,10 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 void
 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
 {
-   uint32_t op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
+   uint32_t op = 0;
 
+   if (va)
+   op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
radeon_emit(cmd_buffer->cs, op);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 2/2] radv: Don't set a new subpass on compute resolve.

2017-08-24 Thread Dave Airlie
On 25 August 2017 at 09:17, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote:
> We don't use the render path so totally unneeded.
>
> Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"

I think there is a more recent commit to fix this one :-)

either way,

Reviewed-by: Dave Airlie <airl...@redhat.com>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 11/11] radv: Expose VK_KHX_multiview.

2017-08-23 Thread Dave Airlie
On 24 August 2017 at 06:51, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote:
> ---
>  src/amd/vulkan/radv_device.c   | 17 +
>  src/amd/vulkan/radv_pipeline.c |  1 +
>  2 files changed, 18 insertions(+)

I've posted some comments on a couple of the patches, with those investigated,

Reviewed-by: Dave Airlie <airl...@redhat.com>

for the series.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 10/11] radv: Implement multiview draws.

2017-08-23 Thread Dave Airlie
On 24 August 2017 at 06:51, Bas Nieuwenhuizen  wrote:
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 132 
> ++-
>  src/amd/vulkan/radv_private.h|   1 +
>  2 files changed, 105 insertions(+), 28 deletions(-)
>

This looks like it has a few more candidate for for_each_bit.

I really don't like the duplication of the draw PKT3s, I'm assuming
all other options are
ugly.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 07/11] radv: Add multiview clears.

2017-08-23 Thread Dave Airlie
On 24 August 2017 at 06:51, Bas Nieuwenhuizen  wrote:
> ---
>  src/amd/vulkan/radv_cmd_buffer.c |  1 +
>  src/amd/vulkan/radv_meta_clear.c | 65 
> 
>  src/amd/vulkan/radv_private.h|  1 +
>  3 files changed, 48 insertions(+), 19 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 94453094eb6..ed11a4aa35e 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1867,6 +1867,7 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer 
> *cmd_buffer,
> }
>
> state->attachments[i].pending_clear_aspects = clear_aspects;
> +   state->attachments[i].cleared_views = 0;
> if (clear_aspects && info) {
> assert(info->clearValueCount > i);
> state->attachments[i].clear_value = 
> info->pClearValues[i];
> diff --git a/src/amd/vulkan/radv_meta_clear.c 
> b/src/amd/vulkan/radv_meta_clear.c
> index af76a517aaf..ea777d9979c 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -337,7 +337,8 @@ radv_device_finish_meta_clear_state(struct radv_device 
> *device)
>  static void
>  emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
>   const VkClearAttachment *clear_att,
> - const VkClearRect *clear_rect)
> + const VkClearRect *clear_rect,
> + uint32_t view_mask)
>  {
> struct radv_device *device = cmd_buffer->device;
> const struct radv_subpass *subpass = cmd_buffer->state.subpass;
> @@ -400,7 +401,14 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
>
> radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, 
> _rect->rect);
>
> -   radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 
> clear_rect->baseArrayLayer);
> +   if (view_mask) {
> +   for (unsigned i = 0; (1u << i) <= view_mask; ++i)
> +   if ((1u << i) & view_mask) {

for_each_bit?

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: fix resolve subpass restoring in compute resolve path.

2017-08-23 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

We need to restore the subpass before we do the fast clear flush.

found while hacking around on vega.

Fixes: 19be95f71 (radv: add subpass resolve compute path)
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_meta_resolve_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c 
b/src/amd/vulkan/radv_meta_resolve_cs.c
index d20d042..6ac8601 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -543,7 +543,7 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer 
*cmd_buffer)
 &(VkOffset2D) { 0, 0 },
 &(VkExtent2D) { fb->width, fb->height });
}
-
+   cmd_buffer->state.subpass = subpass;
radv_meta_restore_compute(_state, cmd_buffer, 16);
 
for (uint32_t i = 0; i < subpass->color_count; ++i) {
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] vulkan: import 1.0.59 headers and xml.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

---
 include/vulkan/vulkan.h| 19 +
 src/vulkan/registry/vk.xml | 53 +++---
 2 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/include/vulkan/vulkan.h b/include/vulkan/vulkan.h
index 3a74f5e..a297bae 100644
--- a/include/vulkan/vulkan.h
+++ b/include/vulkan/vulkan.h
@@ -43,7 +43,7 @@ extern "C" {
 #define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
 #define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
 // Version of this file
-#define VK_HEADER_VERSION 57
+#define VK_HEADER_VERSION 59
 
 
 #define VK_NULL_HANDLE 0
@@ -293,7 +293,7 @@ typedef enum VkStructureType {
 VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_LIMITS_NVX = 186004,
 VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_FEATURES_NVX = 186005,
 VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_W_SCALING_STATE_CREATE_INFO_NV = 
187000,
-VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT = 19,
+VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT = 19,
 VK_STRUCTURE_TYPE_DISPLAY_POWER_INFO_EXT = 191000,
 VK_STRUCTURE_TYPE_DEVICE_EVENT_INFO_EXT = 191001,
 VK_STRUCTURE_TYPE_DISPLAY_EVENT_INFO_EXT = 191002,
@@ -4827,7 +4827,7 @@ typedef struct VkPhysicalDeviceVariablePointerFeaturesKHR 
{
 
 
 #define VK_KHR_dedicated_allocation 1
-#define VK_KHR_DEDICATED_ALLOCATION_SPEC_VERSION 1
+#define VK_KHR_DEDICATED_ALLOCATION_SPEC_VERSION 3
 #define VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME 
"VK_KHR_dedicated_allocation"
 
 typedef struct VkMemoryDedicatedRequirementsKHR {
@@ -5648,7 +5648,7 @@ VKAPI_ATTR VkResult VKAPI_CALL 
vkEnumeratePhysicalDeviceGroupsKHX(
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkObjectTableNVX)
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkIndirectCommandsLayoutNVX)
 
-#define VK_NVX_DEVICE_GENERATED_COMMANDS_SPEC_VERSION 1
+#define VK_NVX_DEVICE_GENERATED_COMMANDS_SPEC_VERSION 3
 #define VK_NVX_DEVICE_GENERATED_COMMANDS_EXTENSION_NAME 
"VK_NVX_device_generated_commands"
 
 
@@ -5938,6 +5938,7 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetRandROutputDisplayEXT(
 #define VK_EXT_display_surface_counter 1
 #define VK_EXT_DISPLAY_SURFACE_COUNTER_SPEC_VERSION 1
 #define VK_EXT_DISPLAY_SURFACE_COUNTER_EXTENSION_NAME 
"VK_EXT_display_surface_counter"
+#define VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT 
VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT
 
 
 typedef enum VkSurfaceCounterFlagBitsEXT {
@@ -6342,6 +6343,11 @@ typedef struct 
VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT {
 #define VK_AMD_MIXED_ATTACHMENT_SAMPLES_EXTENSION_NAME 
"VK_AMD_mixed_attachment_samples"
 
 
+#define VK_EXT_shader_stencil_export 1
+#define VK_EXT_SHADER_STENCIL_EXPORT_SPEC_VERSION 1
+#define VK_EXT_SHADER_STENCIL_EXPORT_EXTENSION_NAME 
"VK_EXT_shader_stencil_export"
+
+
 #define VK_EXT_blend_operation_advanced 1
 #define VK_EXT_BLEND_OPERATION_ADVANCED_SPEC_VERSION 2
 #define VK_EXT_BLEND_OPERATION_ADVANCED_EXTENSION_NAME 
"VK_EXT_blend_operation_advanced"
@@ -6440,6 +6446,11 @@ typedef struct 
VkPipelineCoverageModulationStateCreateInfoNV {
 #define VK_EXT_POST_DEPTH_COVERAGE_EXTENSION_NAME "VK_EXT_post_depth_coverage"
 
 
+#define VK_EXT_shader_viewport_index_layer 1
+#define VK_EXT_SHADER_VIEWPORT_INDEX_LAYER_SPEC_VERSION 1
+#define VK_EXT_SHADER_VIEWPORT_INDEX_LAYER_EXTENSION_NAME 
"VK_EXT_shader_viewport_index_layer"
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/vulkan/registry/vk.xml b/src/vulkan/registry/vk.xml
index 85a49af..f0a1cd6 100644
--- a/src/vulkan/registry/vk.xml
+++ b/src/vulkan/registry/vk.xml
@@ -106,7 +106,7 @@ private version is maintained in the 1.0 branch of the 
member gitlab server.
 // Vulkan 1.0 version number
 #define VK_API_VERSION_1_0 VK_MAKE_VERSION(1, 0, 
0)// Patch version should always be set to 0
 // Version of this file
-#define VK_HEADER_VERSION 57
+#define VK_HEADER_VERSION 59
 
 
 #define VK_DEFINE_HANDLE(object) typedef struct object##_T* 
object;
@@ -2101,7 +2101,7 @@ private version is maintained in the 1.0 branch of the 
member gitlab server.
 const uint32_t* 
pCorrelationMasks
 
 
-VkStructureType
 sType
+VkStructureType
 sType
 void*
pNext
 uint32_t 
minImageCountSupported minimum number of images for the 
surface
 uint32_t 
maxImageCountSupported maximum number of images for the 
surface, 0 for unlimited
@@ -6218,7 +6218,7 @@ private version is maintained in the 1.0 branch of the 
member gitlab server.
 
 
 
-
+
 
 
  

Re: [Mesa-dev] [PATCH 00/18] Gallium blitter optimizations

2017-08-21 Thread Dave Airlie
On 21 August 2017 at 23:21, Marek Olšák  wrote:
> I'll push your patch when I push my series. I guess that's all, right?

If anything else falls out of r600 I'll take a look, but piglit seemed fine.
(as fine as piglit ever is on evergreen).

Nice to see some radv optimisation make their way into the GL driver :-P

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 07/10] radv/image: don't rescale width/height if the format isn't changing

2017-08-21 Thread Dave Airlie
On 21 August 2017 at 17:44, Bas Nieuwenhuizen  wrote:
> The old code would just do a * blocksize / blocksize , which is the
> identity (as long as we don't overflow).  Did this cause any issues?

Nope, just seemed like unnecessary cpu usage.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 8/8] gallium: remove TGSI opcode KILL

2017-08-21 Thread Dave Airlie
On 21 August 2017 at 23:44, Emil Velikov  wrote:
> On 21 August 2017 at 14:19, Marek Olšák  wrote:
>> On Mon, Aug 21, 2017 at 12:47 PM, Emil Velikov  
>> wrote:
>>> Hi Marek,
>>>
>>> On 20 August 2017 at 01:49, Marek Olšák  wrote:
 From: Marek Olšák 

 use KILL_IF -1 instead.
 ---
>>> I'm not 100% sure, but I believe virgl uses TGSI to talk with the host 
>>> driver.
>>> Thus Dave might want to check if the series does not break things on his 
>>> end.
>>>
>>> Alongside the drop of old opcodes new ones get added in their place.
>>> Thus virgl could use some cap checking, if there isn't one already.
>>>
>>> Then again, I'm not that familiar with the driver to know if/how much
>>> that matters.
>>
>> Gallium and TGSI are unstable interfaces. If some drivers expect them
>> to be stable, it's not our concern.
>>
> Agreed. all I'm saying is "lets give Dave the heads up" ;-)

Thanks,

I've forked TGSI on the backend, so I should be fine, I generally can
fix things up with
tgsi transform if someone breaks things a bit too much.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 09/10] radv: don't degrade tiling mode for small compressed or depth texture.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This is what radeonsi does, so we should do the same, also vega
doesn't support linear depth textures anyways.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 78f52a8..684e804 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -44,12 +44,16 @@ radv_choose_tiling(struct radv_device *Device,
return RADEON_SURF_MODE_LINEAR_ALIGNED;
}
 
-   /* Textures with a very small height are recommended to be linear. */
-   if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
-   /* Only very thin and long 2D textures should benefit from
-* linear_aligned. */
-   (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
-   return RADEON_SURF_MODE_LINEAR_ALIGNED;
+   if (!vk_format_is_compressed(pCreateInfo->format) &&
+   !vk_format_is_depth_or_stencil(pCreateInfo->format)) {
+   /* Textures with a very small height are recommended to be 
linear. */
+   if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
+   /* Only very thin and long 2D textures should benefit from
+* linear_aligned. */
+   (pCreateInfo->extent.width > 8 && 
pCreateInfo->extent.height <= 2))
+   return RADEON_SURF_MODE_LINEAR_ALIGNED;
+
+   }
 
/* MSAA resources must be 2D tiled. */
if (pCreateInfo->samples > 1)
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 05/10] radv/gfx9: emit sx_mrt_blend registers

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

GFX9 needs the SX MRT blend registers programmed, port over
the code from radeonsi to workout the values from the blend
state, and program the registers on rbplus systems.

This fixes lots of:
dEQP-VK.pipeline.blend.*

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c |   4 ++
 src/amd/vulkan/radv_pipeline.c   | 131 ++-
 src/amd/vulkan/radv_private.h|   2 +-
 3 files changed, 134 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6e8eff1..239f662 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -368,6 +368,10 @@ radv_emit_graphics_blend_state(struct radv_cmd_buffer 
*cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, 
pipeline->graphics.blend.db_alpha_to_mask);
 
if (cmd_buffer->device->physical_device->has_rbplus) {
+
+   radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028760_SX_MRT0_BLEND_OPT, 8);
+   radeon_emit_array(cmd_buffer->cs, 
pipeline->graphics.blend.sx_mrt_blend_opt, 8);
+
radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028754_SX_PS_DOWNCONVERT, 3);
radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
radeon_emit(cmd_buffer->cs, 0); /* 
R_028758_SX_BLEND_OPT_EPSILON */
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index bd5eeb7..6837cfa 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -849,6 +849,79 @@ static uint32_t si_translate_blend_factor(VkBlendFactor 
factor)
}
 }
 
+static uint32_t si_translate_blend_opt_function(VkBlendOp op)
+{
+   switch (op) {
+   case VK_BLEND_OP_ADD:
+   return V_028760_OPT_COMB_ADD;
+   case VK_BLEND_OP_SUBTRACT:
+   return V_028760_OPT_COMB_SUBTRACT;
+   case VK_BLEND_OP_REVERSE_SUBTRACT:
+   return V_028760_OPT_COMB_REVSUBTRACT;
+   case VK_BLEND_OP_MIN:
+   return V_028760_OPT_COMB_MIN;
+   case VK_BLEND_OP_MAX:
+   return V_028760_OPT_COMB_MAX;
+   default:
+   return V_028760_OPT_COMB_BLEND_DISABLED;
+   }
+}
+
+static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool 
is_alpha)
+{
+   switch (factor) {
+   case VK_BLEND_FACTOR_ZERO:
+   return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
+   case VK_BLEND_FACTOR_ONE:
+   return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
+   case VK_BLEND_FACTOR_SRC_COLOR:
+   return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
+   : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
+   case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
+   return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
+   : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
+   case VK_BLEND_FACTOR_SRC_ALPHA:
+   return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
+   case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
+   return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
+   case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
+   return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
+   : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
+   default:
+   return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
+   }
+}
+
+/**
+ * Get rid of DST in the blend factors by commuting the operands:
+ *func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
+ */
+static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
+   unsigned *dst_factor, unsigned expected_dst,
+   unsigned replacement_src)
+{
+   if (*src_factor == expected_dst &&
+   *dst_factor == VK_BLEND_FACTOR_ZERO) {
+   *src_factor = VK_BLEND_FACTOR_ZERO;
+   *dst_factor = replacement_src;
+
+   /* Commuting the operands requires reversing subtractions. */
+   if (*func == VK_BLEND_OP_SUBTRACT)
+   *func = VK_BLEND_OP_REVERSE_SUBTRACT;
+   else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
+   *func = VK_BLEND_OP_SUBTRACT;
+   }
+}
+
+static bool si_blend_factor_uses_dst(unsigned factor)
+{
+   return factor == VK_BLEND_FACTOR_DST_COLOR ||
+   factor == VK_BLEND_FACTOR_DST_ALPHA ||
+   factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
+   factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
+   factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
+}
+
 static bool is_dual_src(VkBlendFactor factor)
 {
switch (factor) {
@@ -1146,6 +1219,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline 
*pipel

[Mesa-dev] [PATCH 07/10] radv/image: don't rescale width/height if the format isn't changing

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

If the image view has the same format, we don't need to rescale
the w/h.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 5e38041..ddf15bc 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -947,10 +947,12 @@ radv_image_view_init(struct radv_image_view *iview,
.depth  = radv_minify(image->info.depth , range->baseMipLevel),
};
 
-   iview->extent.width = round_up_u32(iview->extent.width * 
vk_format_get_blockwidth(iview->vk_format),
-  
vk_format_get_blockwidth(image->vk_format));
-   iview->extent.height = round_up_u32(iview->extent.height * 
vk_format_get_blockheight(iview->vk_format),
-   
vk_format_get_blockheight(image->vk_format));
+   if (iview->vk_format != image->vk_format) {
+   iview->extent.width = round_up_u32(iview->extent.width * 
vk_format_get_blockwidth(iview->vk_format),
+  
vk_format_get_blockwidth(image->vk_format));
+   iview->extent.height = round_up_u32(iview->extent.height * 
vk_format_get_blockheight(iview->vk_format),
+   
vk_format_get_blockheight(image->vk_format));
+   }
 
iview->base_layer = range->baseArrayLayer;
iview->layer_count = radv_get_layerCount(image, range);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 03/10] radv/gfx9: fixup db/stencil disable.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This fixes disabled Z/stencil.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 0b959f9..0fa074d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1251,9 +1251,13 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer 
*cmd_buffer)
}
radv_load_depth_clear_regs(cmd_buffer, image);
} else {
-   radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 
2);
-   radeon_emit(cmd_buffer->cs, 
S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
-   radeon_emit(cmd_buffer->cs, 
S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
+   if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
GFX9)
+   radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028038_DB_Z_INFO, 2);
+   else
+   radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028040_DB_Z_INFO, 2);
+
+   radeon_emit(cmd_buffer->cs, 
S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
+   radeon_emit(cmd_buffer->cs, 
S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
}
radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
   S_028208_BR_X(framebuffer->width) |
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 02/10] radv/gfx9: fix level count in color register setup.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

There was an off by one here.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9bdad6a..a32f76d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3132,7 +3132,7 @@ radv_initialise_color_surface(struct radv_device *device,

S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
cb->cb_color_attrib2 = 
S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
-   S_028C68_MAX_MIP(iview->image->info.levels);
+   S_028C68_MAX_MIP(iview->image->info.levels - 1);
 
cb->gfx9_epitch = 
S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
 
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 06/10] radv: cleanup some image view descriptor setup.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Avoid passing the vulkan image creation into the image view descriptor
setup. This cleans up the usage of range inside the init, instead
using the properly inited values in the image view.

This is just a cleanup but some future vega changes will depend on it.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c   | 33 -
 src/amd/vulkan/radv_private.h |  1 +
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c0c120e..5e38041 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -862,11 +862,10 @@ radv_image_create(VkDevice _device,
 static void
 radv_image_view_make_descriptor(struct radv_image_view *iview,
struct radv_device *device,
-   const VkImageViewCreateInfo* pCreateInfo,
+   const VkComponentMapping *components,
bool is_storage_image)
 {
-   RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
-   const VkImageSubresourceRange *range = >subresourceRange;
+   struct radv_image *image = iview->image;
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
uint32_t blk_w;
uint32_t *descriptor;
@@ -886,20 +885,27 @@ radv_image_view_make_descriptor(struct radv_image_view 
*iview,
si_make_texture_descriptor(device, image, is_storage_image,
   iview->type,
   iview->vk_format,
-  >components,
-  0, radv_get_levelCount(image, range) - 1,
-  range->baseArrayLayer,
-  range->baseArrayLayer + 
radv_get_layerCount(image, range) - 1,
+  components,
+  0, iview->level_count - 1,
+  iview->base_layer,
+  iview->base_layer + iview->layer_count - 1,
   iview->extent.width,
   iview->extent.height,
   iview->extent.depth,
   descriptor,
   fmask_descriptor);
+
+   const struct legacy_surf_level *base_level_info = NULL;
+   if (device->physical_device->rad_info.chip_class <= GFX9) {
+   if (is_stencil)
+   base_level_info = 
>surface.u.legacy.stencil_level[iview->base_mip];
+   else
+   base_level_info = 
>surface.u.legacy.level[iview->base_mip];
+   }
si_set_mutable_tex_desc_fields(device, image,
-  is_stencil ? 
>surface.u.legacy.stencil_level[range->baseMipLevel]
- : 
>surface.u.legacy.level[range->baseMipLevel],
-  range->baseMipLevel,
-  range->baseMipLevel,
+  base_level_info,
+  iview->base_mip,
+  iview->base_mip,
   blk_w, is_stencil, descriptor);
 }
 
@@ -949,9 +955,10 @@ radv_image_view_init(struct radv_image_view *iview,
iview->base_layer = range->baseArrayLayer;
iview->layer_count = radv_get_layerCount(image, range);
iview->base_mip = range->baseMipLevel;
+   iview->level_count = radv_get_levelCount(image, range);
 
-   radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
-   radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
+   radv_image_view_make_descriptor(iview, device, 
>components, false);
+   radv_image_view_make_descriptor(iview, device, 
>components, true);
 }
 
 bool radv_layout_has_htile(const struct radv_image *image,
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 0d46cf6..c2a4cfb 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1305,6 +1305,7 @@ struct radv_image_view {
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
+   uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. 
*/
 
uint32_t descriptor[8];
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 10/10] radv/gfx9: don't expose linear depth on vega.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

This just zeros out the linear flags for gfx9 + depth formats.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_formats.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 57bde9e..c19a9a3 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -578,6 +578,10 @@ radv_physical_device_get_format_properties(struct 
radv_physical_device *physical
 VK_FORMAT_FEATURE_BLIT_DST_BIT;
tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
 VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
+
+   /* GFX9 doesn't support linear depth surfaces */
+   if (physical_device->rad_info.chip_class >= GFX9)
+   linear = 0;
}
} else {
bool linear_sampling;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] radv/gfx9: more vega fixes.

2017-08-21 Thread Dave Airlie
This is a good chunk of vega related fixes (with some cleanups).

I still have a few more fixes to go, but things are working a lot
better now, I've cleaned up the first round of fixes in this set.

It mostly addresses issues with the color/texture registers around
how miptrees are tiled mipmaps are layed out on gfx9.

It adds support for new rbplus blending registers which fixes
blending in the demos and games.

It also fixes some issues related to exposing linear depth texture
support.

Dave.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 08/10] radv/gfx9: only minify image view width/height/depth before gfx9.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

For gfx9 the addressing for images has changed, so we need to
provide the hw with the level0, however we still need to scale
for format block differences (so our compressed upload paths still
work).

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c |  4 ++--
 src/amd/vulkan/radv_image.c  | 18 +-
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a32f76d..1a7831e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3130,8 +3130,8 @@ radv_initialise_color_surface(struct radv_device *device,
cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |

S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
-   cb->cb_color_attrib2 = 
S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
-   S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
+   cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width 
- 1) |
+   S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
S_028C68_MAX_MIP(iview->image->info.levels - 1);
 
cb->gfx9_epitch = 
S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ddf15bc..78f52a8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -941,11 +941,19 @@ radv_image_view_init(struct radv_image_view *iview,
iview->vk_format = vk_format_depth_only(iview->vk_format);
}
 
-   iview->extent = (VkExtent3D) {
-   .width  = radv_minify(image->info.width , range->baseMipLevel),
-   .height = radv_minify(image->info.height, range->baseMipLevel),
-   .depth  = radv_minify(image->info.depth , range->baseMipLevel),
-   };
+   if (device->physical_device->rad_info.chip_class >= GFX9) {
+   iview->extent = (VkExtent3D) {
+   .width = image->info.width,
+   .height = image->info.height,
+   .depth = image->info.depth,
+   };
+   } else {
+   iview->extent = (VkExtent3D) {
+   .width  = radv_minify(image->info.width , 
range->baseMipLevel),
+   .height = radv_minify(image->info.height, 
range->baseMipLevel),
+   .depth  = radv_minify(image->info.depth , 
range->baseMipLevel),
+   };
+   }
 
if (iview->vk_format != image->vk_format) {
iview->extent.width = round_up_u32(iview->extent.width * 
vk_format_get_blockwidth(iview->vk_format),
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 01/10] radv/gfx9: use total levels in texture descriptor

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

We need to use all the levels when filling out the gfx9
descriptor.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 314964d..c0c120e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -414,7 +414,7 @@ si_make_texture_descriptor(struct radv_device *device,
state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
 util_logbase2(image->info.samples) 
:
-last_level);
+image->info.levels - 1);
} else {
state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
state[4] |= S_008F20_DEPTH(depth - 1);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 04/10] radv: bump space check for indexed draw.

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

For the GFX9 packet we need one more dword.

Fixes an assert in:
dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 0fa074d..6e8eff1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2712,7 +2712,7 @@ void radv_CmdDrawIndexed(
 
radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), 
false, indexCount);
 
-   MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
+   MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 16);
 
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cmd_buffer->cs, 
R_03090C_VGT_INDEX_TYPE,
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: don't crash if we have no framebuffer

2017-08-21 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Recording secondaries with no framebuffer attachment may
make this happen, though this might not be the complete solution.

(esp if someone does meta stuff in there, would we have to
save things, not sure).
---
 src/amd/vulkan/radv_cmd_buffer.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ea17e33..239f662 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1212,6 +1212,10 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer 
*cmd_buffer)
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 
+   /* this may happen for inherited secondary recording */
+   if (!framebuffer)
+   return;
+
for (i = 0; i < 8; ++i) {
if (i >= subpass->color_count || 
subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
radeon_set_context_reg(cmd_buffer->cs, 
R_028C70_CB_COLOR0_INFO + i * 0x3C,
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 00/18] Gallium blitter optimizations

2017-08-20 Thread Dave Airlie
On 21 August 2017 at 10:58, Marek Olšák <mar...@gmail.com> wrote:
> On Mon, Aug 21, 2017 at 2:41 AM, Dave Airlie <airl...@gmail.com> wrote:
>> On 21 August 2017 at 10:22, Dave Airlie <airl...@gmail.com> wrote:
>>> Hi Gert,
>>>
>>> Can you test this along with the fetch shader patch Marek sent?
>>>
>>> I'm giving it a piglit run now.
>>
>> Actually that patch is probably not necessary,
>>
>> I think you need to fill in 0 for the 4th 2D coordinate for LD to be used.
>>
>> TGSI spec for LD says it takes level in the last channel of the coord, and 
>> you
>> never set it, whereas the old blitter path set it correctly.
>
> radeonsi always uses TXF_LZ with u_blitter. That way level=0 is
> implied by the instruction. The CAP demands that both TXF_LZ and
> TEX_LZ are supported.

Do we add support for the cap in r600 and make the TXF_LZ CAP
mandatory for u_blitter,
or since before this series TXF_LZ is optional we continue to support
it, and set the
values to 0?

This does the latter, I think it should be fine everywhere.

Dave.
From fa9055be8721c93c971c261fc1e095dbb97f26df Mon Sep 17 00:00:00 2001
From: Dave Airlie <airl...@redhat.com>
Date: Mon, 21 Aug 2017 11:05:31 +1000
Subject: [PATCH] r600: handle the non-TXF_LZ support path.

it appears that texcoord.z/w will be 0 in all cases already,
so just put them into the vbo always.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 4d1b31d..80ef291 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -257,10 +257,10 @@ void r600_draw_rectangle(struct blitter_context *blitter,
 			memcpy(vb+8, attrib->color, sizeof(float)*4);
 			break;
 		case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
+		case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
 			vb[2] = vb[6] = vb[10] = attrib->texcoord.z;
 			vb[3] = vb[7] = vb[11] = attrib->texcoord.w;
 			/* fall through */
-		case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
 			vb[0] = attrib->texcoord.x1;
 			vb[1] = attrib->texcoord.y1;
 			vb[4] = attrib->texcoord.x2;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 00/18] Gallium blitter optimizations

2017-08-20 Thread Dave Airlie
On 21 August 2017 at 10:22, Dave Airlie <airl...@gmail.com> wrote:
> Hi Gert,
>
> Can you test this along with the fetch shader patch Marek sent?
>
> I'm giving it a piglit run now.

Actually that patch is probably not necessary,

I think you need to fill in 0 for the 4th 2D coordinate for LD to be used.

TGSI spec for LD says it takes level in the last channel of the coord, and you
never set it, whereas the old blitter path set it correctly.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 00/18] Gallium blitter optimizations

2017-08-20 Thread Dave Airlie
Hi Gert,

Can you test this along with the fetch shader patch Marek sent?

I'm giving it a piglit run now.

Dave.

On 21 August 2017 at 09:22, Dave Airlie <airl...@gmail.com> wrote:
> On 20 August 2017 at 05:25, Marek Olšák <mar...@gmail.com> wrote:
>> On Sat, Aug 19, 2017 at 7:24 PM, Gert Wollny <gw.foss...@gmail.com> wrote:
>>> Am Samstag, den 19.08.2017, 18:35 +0200 schrieb Marek Olšák:
>>>> Can you try the attached patch?
>>>
>>> While if fixes the crash and lets me run glxgears and some other rathe
>>> simple OpenGL programs it completely messes up blender (menu unreadable
>>> etc) and UE4Editor Window is also flickering.
>>
>> OK, well, I might have to fork u_blitter for radeonsi. I don't think I
>> have any other choice.
>
> Seems extreme, I'm sure you own at least one evergreen card.
>
> The first patch breaks things, but when I fix that a later patch
> breaks things again,
> but I'll reply to the individual patches in a minute.
>
> Dave.
From 4686bc355e54c9081c3c06a864b016b4da5f9bab Mon Sep 17 00:00:00 2001
From: Dave Airlie <airl...@redhat.com>
Date: Mon, 21 Aug 2017 10:03:10 +1000
Subject: [PATCH] r600g: limit coords passes to hw for txf on 2d surface.

This should be improved to cover a lot more cases,
but this is enough to fix up the new blitter series.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 8c5e6ff..df3165a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -7634,6 +7634,26 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		/* the array index is read from Z */
 		tex.coord_type_z = 0;
 
+	if (opcode == FETCH_OP_LD) {
+		/* masking doesn't appear to work for LD,
+		   set the unused srcs to 0. */
+		switch (inst->Texture.Texture) {
+		case TGSI_TEXTURE_2D_ARRAY:
+			tex.src_sel_w = 4;
+			break;
+		case TGSI_TEXTURE_2D:
+		case TGSI_TEXTURE_RECT:
+			tex.src_sel_z = 4;
+			tex.src_sel_w = 4;
+			break;
+		case TGSI_TEXTURE_1D:
+			tex.src_sel_y = 4;
+			tex.src_sel_z = 4;
+			tex.src_sel_w = 4;
+			break;
+		}
+	}
+
 	/* mask unused source components */
 	if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
 		switch (inst->Texture.Texture) {
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 02/18] gallium/radeon: use rectangles for 1D and 2D texture blits

2017-08-20 Thread Dave Airlie
>
> Actually I can still get into a wierd place where simple tests that
> readback fail.
>
> I'll try and dig some more.

Ignore previous, the problem is you don't zero the other coords in the
vertex buffer, so r600 sees a TXF 2D but passes all 4 texture coord
to the hw.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 02/18] gallium/radeon: use rectangles for 1D and 2D texture blits

2017-08-20 Thread Dave Airlie
On 21 August 2017 at 09:28, Dave Airlie <airl...@gmail.com> wrote:
> On 18 August 2017 at 04:31, Marek Olšák <mar...@gmail.com> wrote:
>> From: Marek Olšák <marek.ol...@amd.com>
>>
>
> This break r600 first.
>
>> -   if (attrib) {
>> +   switch (type) {
>> +   case UTIL_BLITTER_ATTRIB_COLOR:
>> memcpy(vb+4, attrib->f, sizeof(float)*4);
>> memcpy(vb+12, attrib->f, sizeof(float)*4);
>> memcpy(vb+20, attrib->f, sizeof(float)*4);
>> +   break;
>> +   case UTIL_BLITTER_ATTRIB_TEXCOORD:
>> +   vb[4] = attrib->f[0]; /* x1 */
>> +   vb[5] = attrib->f[1]; /* y1 */
>> +   vb[12] = attrib->f[0]; /* x1 */
>> +   vb[13] = attrib->f[3]; /* y2 */
>> +   vb[20] = attrib->f[2]; /* x2 */
>> +   vb[21] = attrib->f[1]; /* y1 */
>
> Something in here is backwards compared to the normal path.
>
> Making this (0,1) (2, 1), (2, 3) fixes evergreen for me, until the later
> patch breaks it again.
>
> This is the same order that set_texcoords_in_vertices uses
> before this patch.

Actually I can still get into a wierd place where simple tests that
readback fail.

I'll try and dig some more.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 02/18] gallium/radeon: use rectangles for 1D and 2D texture blits

2017-08-20 Thread Dave Airlie
On 18 August 2017 at 04:31, Marek Olšák  wrote:
> From: Marek Olšák 
>

This break r600 first.

> -   if (attrib) {
> +   switch (type) {
> +   case UTIL_BLITTER_ATTRIB_COLOR:
> memcpy(vb+4, attrib->f, sizeof(float)*4);
> memcpy(vb+12, attrib->f, sizeof(float)*4);
> memcpy(vb+20, attrib->f, sizeof(float)*4);
> +   break;
> +   case UTIL_BLITTER_ATTRIB_TEXCOORD:
> +   vb[4] = attrib->f[0]; /* x1 */
> +   vb[5] = attrib->f[1]; /* y1 */
> +   vb[12] = attrib->f[0]; /* x1 */
> +   vb[13] = attrib->f[3]; /* y2 */
> +   vb[20] = attrib->f[2]; /* x2 */
> +   vb[21] = attrib->f[1]; /* y1 */

Something in here is backwards compared to the normal path.

Making this (0,1) (2, 1), (2, 3) fixes evergreen for me, until the later
patch breaks it again.

This is the same order that set_texcoords_in_vertices uses
before this patch.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH 00/18] Gallium blitter optimizations

2017-08-20 Thread Dave Airlie
On 20 August 2017 at 05:25, Marek Olšák  wrote:
> On Sat, Aug 19, 2017 at 7:24 PM, Gert Wollny  wrote:
>> Am Samstag, den 19.08.2017, 18:35 +0200 schrieb Marek Olšák:
>>> Can you try the attached patch?
>>
>> While if fixes the crash and lets me run glxgears and some other rathe
>> simple OpenGL programs it completely messes up blender (menu unreadable
>> etc) and UE4Editor Window is also flickering.
>
> OK, well, I might have to fork u_blitter for radeonsi. I don't think I
> have any other choice.

Seems extreme, I'm sure you own at least one evergreen card.

The first patch breaks things, but when I fix that a later patch
breaks things again,
but I'll reply to the individual patches in a minute.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: disable support for VEGA for now.

2017-08-17 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

I'm working on this, but I'm not sure I'll make 17.2 at this stage,
maybe 17.2.1.

Cc: "17.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index 2503489..607ef62 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -46,6 +46,11 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
if (!ac_query_gpu_info(fd, ws->dev, >info, >amdinfo))
return false;
 
+   if (ws->info.chip_class >= GFX9) {
+   fprintf(stderr, "radv: VEGA support not completed.\n");
+   return false;
+   }
+
/* LLVM 5.0 is required for GFX9. */
if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM 
%i.%i\n",
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] ac/nir: fixup layer/viewport export for GFX9.

2017-08-16 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

GFX9 moved where the viewport index export goes.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 32 +---
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7aa7567..a17a232 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5518,11 +5518,11 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
 
ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
}
 
-   uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
-(outinfo->writes_layer == true ? 4 : 0) |
-(outinfo->writes_viewport_index == true ? 8 : 0));
-   if (mask) {
-   pos_args[1].enabled_channels = mask;
+   if (outinfo->writes_pointsize ||
+   outinfo->writes_layer ||
+   outinfo->writes_viewport_index) {
+   pos_args[1].enabled_channels = ((outinfo->writes_pointsize == 
true ? 1 : 0) |
+   (outinfo->writes_layer == true 
? 4 : 0));
pos_args[1].valid_mask = 0;
pos_args[1].done = 0;
pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
@@ -5536,8 +5536,26 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
pos_args[1].out[0] = psize_value;
if (outinfo->writes_layer == true)
pos_args[1].out[2] = layer_value;
-   if (outinfo->writes_viewport_index == true)
-   pos_args[1].out[3] = viewport_index_value;
+   if (outinfo->writes_viewport_index == true) {
+   if (ctx->options->chip_class >= GFX9) {
+   /* GFX9 has the layer in out.z[10:0] and the 
viewport
+* index in out.z[19:16].
+*/
+   LLVMValueRef v = viewport_index_value;
+   v = to_integer(>ac, v);
+   v = LLVMBuildShl(ctx->builder, v,
+LLVMConstInt(ctx->i32, 16, 
false),
+"");
+   v = LLVMBuildOr(ctx->builder, v,
+   to_integer(>ac, 
pos_args[1].out[2]), "");
+
+   pos_args[1].out[2] = to_float(>ac, v);
+   pos_args[1].enabled_channels |= 1 << 2;
+   } else {
+   pos_args[1].out[3] = viewport_index_value;
+   pos_args[1].enabled_channels |= 1 << 3;
+   }
+   }
}
for (i = 0; i < 4; i++) {
if (pos_args[i].out[0])
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH] radv: disable texture gather workaround on gfx9.

2017-08-16 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

Not required anymore.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bc325e6..cc42877 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2185,7 +2185,7 @@ static LLVMValueRef build_tex_intrinsic(struct 
ac_nir_context *ctx,
break;
}
 
-   if (instr->op == nir_texop_tg4) {
+   if (instr->op == nir_texop_tg4 && ctx->abi->chip_class <= VI) {
enum glsl_base_type stype = 
glsl_get_sampler_result_type(instr->texture->var->type);
if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
return radv_lower_gather4_integer(>ac, args, 
instr);
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 4/5] radv/gfx9: handle GFX9 opaque metadata

2017-08-14 Thread Dave Airlie
From: David Airlie <airl...@dhcp-40-204.bne.redhat.com>

port the opaque metadata changes from radeonsi for gfx9.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_image.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8d3ff1a515..7a4b2d57a5 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -555,10 +555,11 @@ radv_query_opaque_metadata(struct radv_device *device,
memcpy(>metadata[2], desc, sizeof(desc));
 
/* Dwords [10:..] contain the mipmap level offsets. */
-   for (i = 0; i <= image->info.levels - 1; i++)
-   md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 
8;
-
-   md->size_metadata = (11 + image->info.levels - 1) * 4;
+   if (device->physical_device->rad_info.chip_class <= VI) {
+   for (i = 0; i <= image->info.levels - 1; i++)
+   md->metadata[10+i] = 
image->surface.u.legacy.level[i].offset >> 8;
+   md->size_metadata = (11 + image->info.levels - 1) * 4;
+   }
 }
 
 void
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] radv: some initial gfx9 fixes

2017-08-14 Thread Dave Airlie
This is just a first batch of vega changes from today, some 
of the vulkan samples render (triangle, texture, gears), but nothing
too useful.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 5/5] radv/gfx9: fix tile swizzle handling for gfx9

2017-08-14 Thread Dave Airlie
From: David Airlie <airl...@dhcp-40-204.bne.redhat.com>

This sets the tile swizzle up properly for gfx9.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_device.c |  7 +++
 src/amd/vulkan/radv_image.c  | 12 +---
 2 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 85ba165b4c..9bdad6ad6f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2983,6 +2983,7 @@ radv_initialise_color_surface(struct radv_device *device,
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
 
cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset 
>> 8;
+   cb->cb_color_base |= iview->image->surface.tile_swizzle;
} else {
const struct legacy_surf_level *level_info = 
>u.legacy.level[iview->base_mip];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
@@ -3024,8 +3025,7 @@ radv_initialise_color_surface(struct radv_device *device,
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->dcc_offset;
cb->cb_dcc_base = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
+   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
 
uint32_t max_slice = radv_surface_layer_count(iview);
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
@@ -3041,8 +3041,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (iview->image->fmask.size) {
va = device->ws->buffer_get_va(iview->bo) + 
iview->image->offset + iview->image->fmask.offset;
cb->cb_color_fmask = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
+   cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 7a4b2d57a5..314964d64e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -215,9 +215,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
va += base_level_info->offset;
 
state[0] = va >> 8;
-   if (chip_class < GFX9)
-   if (base_level_info->mode == RADEON_SURF_MODE_2D)
-   state[0] |= image->surface.tile_swizzle;
+   if (chip_class >= GFX9 ||
+   base_level_info->mode == RADEON_SURF_MODE_2D)
+   state[0] |= image->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
@@ -230,8 +230,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va += base_level_info->dcc_offset;
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
-   if (chip_class < GFX9)
-   state[7] |= image->surface.tile_swizzle;
+   state[7] |= image->surface.tile_swizzle;
}
}
 
@@ -479,8 +478,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
 
fmask_state[0] = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   fmask_state[0] |= image->fmask.tile_swizzle;
+   fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


[Mesa-dev] [PATCH 1/5] radv/gfx9: fix set predication packet.

2017-08-14 Thread Dave Airlie
From: Dave Airlie <airl...@redhat.com>

The predication packet changed format on GFX9, update the driver.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 88616edfa2..913ec0e7d2 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1133,15 +1133,18 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 void
 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
 {
-   uint32_t val = 0;
-
-   if (va)
-   val = (((va >> 32) & 0xff) |
-  PRED_OP(PREDICATION_OP_BOOL64)|
-  PREDICATION_DRAW_VISIBLE);
-   radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, val);
+   uint32_t op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
+
+   if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+   radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
+   radeon_emit(cmd_buffer->cs, op);
+   radeon_emit(cmd_buffer->cs, va);
+   radeon_emit(cmd_buffer->cs, va >> 32);
+   } else {
+   radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
+   radeon_emit(cmd_buffer->cs, va);
+   radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
+   }
 }
 
 /* Set this if you want the 3D engine to wait until CP DMA is done.
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev


  1   2   3   4   5   6   7   8   9   10   >