Paul Berry stereotype...@gmail.com writes:
This patch series adds varying packing to Mesa, so that we can handle
varyings composed of things other than vec4's without using up extra
varying components.
Results for glbenchmark 2.7 at 320x240 (units of fps):
N Min Max
Gen7 stores the JIP/UIP bits in different places.
---
src/mesa/drivers/dri/i965/brw_disasm.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
Otherwise you get awful junk like endif 8207. Clearly rubbish.
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
On Tue, 14 Aug 2012 12:59:42 -0700
Matt Turner matts...@gmail.com wrote:
Cc: Jeremy Huddleston jerem...@apple.com
---
Jeremy, does OS X ship the pkg-config files?
Haiku doesn't... Mesa should have a path to properly handle a system
not having X11 installed. ( Mesa *is* the only open source GL
https://bugs.freedesktop.org/show_bug.cgi?id=57899
--- Comment #1 from pejakm pej...@gmail.com ---
Sorry for bumping up, I still get this error. Anyone care to take a look?
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On 12/11/2012 09:25 PM, Paul Berry wrote:
Previously, if the client program didn't specify a stride when setting
up a vertex attribute, we used _mesa_sizeof_type() to compute the size
of the type, and multiplied it by the number of components.
This didn't work for the 2_10_10_10 formats, since
On 12 December 2012 00:02, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch series adds varying packing to Mesa, so that we can handle
varyings composed of things other than vec4's without using up extra
varying components.
Results for glbenchmark
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
configure.ac | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/configure.ac b/configure.ac
index a133902..1294740 100644
--- a/configure.ac
+++ b/configure.ac
@@ -341,18 +341,18 @@ AC_ARG_ENABLE([debug],
if test
Sounds good to me.
Jose
- Original Message -
This is redundant since we're calling draw_bind_fragment_shader()
which already does a flush.
v2: the redundant flush in llvmpipe_set_constant_buffer() has
already been removed by commit
3427466e6dbbb8db7c1ecda6b3859ca1cc5827a3
---
On Dec 12, 2012 8:30 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Looks good.
Reviewed-by: Dan Nicholson dbn.li...@gmail.com
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On 11 December 2012 23:49, Aras Pranckevicius a...@unity3d.com wrote:
For the initial implementation I've chosen a strategy that operates
exclusively at the GLSL IR level, so that it doesn't require the
cooperation of the driver back-ends.
Wouldn't this negatively affect performance of
On 12 December 2012 00:02, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch series adds varying packing to Mesa, so that we can handle
varyings composed of things other than vec4's without using up extra
varying components.
Results for glbenchmark
On Wed, Dec 12, 2012 at 5:06 PM, Paul Berry stereotype...@gmail.com wrote:
On 11 December 2012 23:49, Aras Pranckevicius a...@unity3d.com wrote:
For the initial implementation I've chosen a strategy that operates
exclusively at the GLSL IR level, so that it doesn't require the
cooperation of
Paul Berry stereotype...@gmail.com writes:
On 12 December 2012 00:02, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch series adds varying packing to Mesa, so that we can handle
varyings composed of things other than vec4's without using up extra
On 12 December 2012 09:51, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
On 12 December 2012 00:02, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch series adds varying packing to Mesa, so that we can handle
On 12 December 2012 09:09, Marek Olšák mar...@gmail.com wrote:
R300 and R400 support 4 texture indirections (as defined by
ARB_fragment_program). Adding ALU instructions before the first TEX
instruction increases the number of texture indirections by 1, which
might make some shaders not be
On 12 December 2012 10:21, Paul Berry stereotype...@gmail.com wrote:
On 12 December 2012 09:09, Marek Olšák mar...@gmail.com wrote:
R300 and R400 support 4 texture indirections (as defined by
ARB_fragment_program). Adding ALU instructions before the first TEX
instruction increases the number
Kenneth Graunke kenn...@whitecape.org writes:
Gen7 stores the JIP/UIP bits in different places.
Reviewed-by: Eric Anholt e...@anholt.net
pgpnqrtiFdjEP.pgp
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NOTE: This is a candidate for the stable branches.
---
src/gallium/drivers/llvmpipe/lp_texture.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/llvmpipe/lp_texture.c
b/src/gallium/drivers/llvmpipe/lp_texture.c
index 2e9c6bf..f17a04a 100644
---
On Wed, Dec 12, 2012 at 7:51 PM, Paul Berry stereotype...@gmail.com wrote:
On 12 December 2012 10:21, Paul Berry stereotype...@gmail.com wrote:
On 12 December 2012 09:09, Marek Olšák mar...@gmail.com wrote:
R300 and R400 support 4 texture indirections (as defined by
ARB_fragment_program).
Marek Olšák mar...@gmail.com writes:
On Wed, Dec 12, 2012 at 5:06 PM, Paul Berry stereotype...@gmail.com wrote:
On 11 December 2012 23:49, Aras Pranckevicius a...@unity3d.com wrote:
Not sure if relevant for Mesa, but e.g. on PowerVR SGX it's really bad to
pack two vec2 texture coordinates
https://bugs.freedesktop.org/show_bug.cgi?id=58210
Priority: medium
Bug ID: 58210
Assignee: mesa-dev@lists.freedesktop.org
Summary: vmwgfx freezes system when starting Xorg
Severity: major
Classification: Unclassified
OS:
Not sure if relevant for Mesa, but e.g. on PowerVR SGX it's really bad to
pack two vec2 texture coordinates into a single vec4. That's because var.xy
texture read can be prefetched, whereas var.zw texture read is not
prefetched (essentially treated as a dependent texture read), and often
Looks good AFAICT.
Maybe we should add a test for this in piglit?
Jose
- Original Message -
From: Roland Scheidegger srol...@vmware.com
Since we don't call lp_build_sample_common() in the texel fetch path
we missed
the layer fixup code. If someone would have tried to do texelFetch
On 12/12/2012 09:52 AM, Dan Nicholson wrote:
On Dec 12, 2012 8:30 AM, Emil Velikov emil.l.veli...@gmail.com
mailto:emil.l.veli...@gmail.com wrote:
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
mailto:emil.l.veli...@gmail.com
Looks good.
Reviewed-by: Dan Nicholson
On Wed, Dec 12, 2012 at 9:21 PM, Eric Anholt e...@anholt.net wrote:
Marek Olšák mar...@gmail.com writes:
On Wed, Dec 12, 2012 at 5:06 PM, Paul Berry stereotype...@gmail.com wrote:
On 11 December 2012 23:49, Aras Pranckevicius a...@unity3d.com wrote:
Not sure if relevant for Mesa, but e.g. on
https://bugs.freedesktop.org/show_bug.cgi?id=57899
pejakm pej...@gmail.com changed:
What|Removed |Added
Status|NEW |RESOLVED
On 12 December 2012 12:44, Aras Pranckevicius a...@unity3d.com wrote:
Not sure if relevant for Mesa, but e.g. on PowerVR SGX it's really bad to
pack two vec2 texture coordinates into a single vec4. That's because var.xy
texture read can be prefetched, whereas var.zw texture read is not
On 12 December 2012 12:53, Marek Olšák mar...@gmail.com wrote:
On Wed, Dec 12, 2012 at 9:21 PM, Eric Anholt e...@anholt.net wrote:
Marek Olšák mar...@gmail.com writes:
On Wed, Dec 12, 2012 at 5:06 PM, Paul Berry stereotype...@gmail.com
wrote:
On 11 December 2012 23:49, Aras
Paul Berry stereotype...@gmail.com writes:
This patch subdivides the loop that assigns varying locations into two
phases: one phase to match up varyings between shader stages (and
assign them varying locations), and a second phase to record the
varying assignments for use by transform
On 12 December 2012 13:32, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch subdivides the loop that assigns varying locations into two
phases: one phase to match up varyings between shader stages (and
assign them varying locations), and a second
I was wrong that there is no test for this in piglit.
spec/glsl-1.30/execution/fs-texelFetch-2D.c (and the offset version)
only test 2d samplers, but texturing/shaders/texelFetch.c can test all
samplers, in both fs and vs.
It currently crashes though with llvmpipe (using glsl and GL version
Paul Berry stereotype...@gmail.com writes:
This patch implements varying packing between varyings.
Previously, each varying occupied components 0 through N-1 of its
assigned varying slot, so there was no way to pack two varyings into
the same slot. For example, if the varyings were a float,
Paul Berry stereotype...@gmail.com writes:
This patch implements varying packing within varyings that are
composed of multiple vectors of size less than 4 (e.g. arrays of
vec2's, or matrices with height less than 4).
Previously, such varyings used up a full 4-wide varying slot for each
On 12 December 2012 14:08, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch implements varying packing within varyings that are
composed of multiple vectors of size less than 4 (e.g. arrays of
vec2's, or matrices with height less than 4).
On 12 December 2012 14:06, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
This patch implements varying packing between varyings.
Previously, each varying occupied components 0 through N-1 of its
assigned varying slot, so there was no way to pack two
Hi list,
I've been working on i965g, a new pipe driver for Intel GEN6 (and
later), for a while now. I would like to know if there is any
interest in it and if it can be merged upstream. The code is
currently available here
https://github.com/olvaffe/mesa/tree/i965g
The project was started
Paul Berry stereotype...@gmail.com writes:
diff --git a/src/glsl/lower_packed_varyings.cpp
b/src/glsl/lower_packed_varyings.cpp
new file mode 100644
index 000..4cb9066
--- /dev/null
+++ b/src/glsl/lower_packed_varyings.cpp
@@ -0,0 +1,371 @@
+/*
+ * Copyright © 2011 Intel Corporation
This series is based on gles3 branch of mesa. All patches collectively
fixes around 17 failing test cases in gles3 conformance framebuffer_blit
and framebuffer_srgb_default_encoding.test. Observed no regressions
in gles3 conformance.
Anuj Phogat (6):
mesa: Allow GL_BACK in glDrawBuffers() for
Makes framebuffer_blit_coverage_default_draw_buffer_binding.test in
gles3 conformance pass.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/main/buffers.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/buffers.c
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/main/fbobject.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 4b7d4ab..9e32836 100644
--- a/src/mesa/main/fbobject.c
+++
This is required by glBlitFrameBuffer() in gles3. This patch, along with
other patches in this series, make failing framebuffer_blit test cases in
gles3 conformancen pass.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/common/meta.c | 313
This patch fixes a case when blitting to a framebuffer with
renderbuffers/textures attached to GL_COLOR_ATTACHMENT{1, 2, ...}.
Earlier we were incorrectly blitting to GL_COLOR_ATTACHMENT0 by default.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
This patch fixes a case when blitting to a framebuffer with
renderbuffers/textures attached to GL_COLOR_ATTACHMENT{1, 2, ...}.
Earlier we were incorrectly blitting to GL_COLOR_ATTACHMENT0 by default.
It also fixes a blitting case when drawAttachment-Texture ==
readAttachment-Texture. This was
On 12 December 2012 14:49, Eric Anholt e...@anholt.net wrote:
Paul Berry stereotype...@gmail.com writes:
diff --git a/src/glsl/lower_packed_varyings.cpp
b/src/glsl/lower_packed_varyings.cpp
new file mode 100644
index 000..4cb9066
--- /dev/null
+++
If you want a piece of advice... it would be great to extend gallium
to allow the GLSL IR to be passed to drivers directly. Once that's
done, I think you can copy their shader codegen as-is with all
optimizations or even share it. Also, I don't think Intel will move to
Gallium if they can't use
On Wed, Dec 12, 2012 at 3:49 PM, Roland Scheidegger srol...@vmware.com wrote:
This is interesting, personally I'm fine with getting this merged.
That said, there was a i965g driver upstream before (though it never
worked right IIRC and was probably gen4 or maybe gen5 too only due to
its age),
This adds support to draw for the new features of transform feedback.
a) fix count_from_stream_output, using max_index+1 for now but it looks
like it should be valid as its derived from the vertex elements/vbo.
b) fix striding and dst offsets in output buffers - was just wrong before.
c) fix
GCC complains about mixed code and declarations and unhandled enum cases
when compiling r600. This patch correct it :
From 25b5d12eec732ed582a8a3e146c0285819806ba8 Mon Sep 17 00:00:00 2001
From: Maxence Le Dore maxence.led...@gmail.com
Date: Thu, 13 Dec 2012 05:17:35 +0100
Subject: [PATCH] r600:
Hi,
So I've been playing around a bit more with transform feedback with
llvmpipe, and it seems the position output from the vertex shader is
different from what softpipe produces.
using from piglit ./bin/ext_transform_feedback-builtin-varyings gl_Position
the position with softpipe for
On Thu, Dec 13, 2012 at 7:49 AM, Roland Scheidegger srol...@vmware.com wrote:
This is interesting, personally I'm fine with getting this merged.
That said, there was a i965g driver upstream before (though it never
worked right IIRC and was probably gen4 or maybe gen5 too only due to
its age),
On Thu, Dec 13, 2012 at 2:48 PM, Dave Airlie airl...@gmail.com wrote:
Hi,
So I've been playing around a bit more with transform feedback with
llvmpipe, and it seems the position output from the vertex shader is
different from what softpipe produces.
using from piglit
Hi Marek,
On Thu, Dec 13, 2012 at 8:58 AM, Marek Olšák mar...@gmail.com wrote:
If you want a piece of advice... it would be great to extend gallium
to allow the GLSL IR to be passed to drivers directly. Once that's
done, I think you can copy their shader codegen as-is with all
optimizations
On Thu, Dec 13, 2012 at 10:59 AM, Stéphane Marchesin
stephane.marche...@gmail.com wrote:
On Wed, Dec 12, 2012 at 3:49 PM, Roland Scheidegger srol...@vmware.com
wrote:
This is interesting, personally I'm fine with getting this merged.
That said, there was a i965g driver upstream before (though
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