We only want to enable ARB_transform_feedback2 if we can write to
registers from batchbuffers. In order to test that, we need to be able
to submit batches. And for batches to work, we need to program the
initial pipeline state (like PIPELINE_SELECT), which is done from
brw_state_init().
With Linux 3.12, register writes work on Ivybridge and Baytrail, but not
Haswell. That will be fixed in a future kernel revision, at which point
this extension will automatically be enabled.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_extensions.c |
Fixes Uninitialized pointer field defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
On 10/08/2013 12:31 PM, Ian Romanick wrote:
On 10/08/2013 02:34 AM, Chris Forbes wrote:
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
Fixes Dereference before null check defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/mesa/drivers/dri/radeon/radeon_texture.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c
Fixes Resource leak defects reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/mesa/drivers/dri/i915/intel_mipmap_tree.c | 4 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git
On 10/08/2013 02:35 AM, Chris Forbes wrote:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 45
++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
On 10/08/2013 02:34 AM, Chris Forbes wrote:
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use.
logic_op is of type GLenum (unsigned int).
Fixes Macro compares unsigned to 0 defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/mesa/drivers/dri/i915/intel_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, 2013-10-25 at 14:51 -0700, Paul Berry wrote:
+ _mesa_glsl_error(loc, state,
+ is_initializer ? initializer : value
+ of type %s cannot be assigned to
+ variable of type %s,
+
On 10/14/2013 01:30 AM, Chris Forbes wrote:
gather4_c's argument layout is straightforward -- refz just goes on the
end.
gather4_po_c's layout however -- the array index is replaced with refz.
That is really strange...especially since GLSL requires supporting
textureGatherOffset with
On 10/14/2013 01:33 AM, Chris Forbes wrote:
Rewrites textureGatherOffsets(s, p, offsets) into
gvec4(
textureGatherOffset(s, p, offsets[0]).w,
textureGatherOffset(s, p, offsets[1]).w,
textureGatherOffset(s, p, offsets[2]).w,
textureGatherOffset(s, p, offsets[3]).w
Remove dead code left behind by commit
8d7b913e4e089cc8b0b800cbcf80737d0be0a0f7.
Fixes Logically dead code defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/gallium/drivers/svga/svga_draw_elements.c | 6 --
1 file changed, 6 deletions(-)
diff --git
On 10/14/2013 01:36 AM, Chris Forbes wrote:
It turns out that nonzero offsets with gsampler2DRect don't work -- they
just return garbage. Work around this by folding the offset into the
coord.
Done as an IR pass rather than yet another hack in the visitors because
it's clear what's going on
On 10/14/2013 01:36 AM, Chris Forbes wrote:
ir_txf expects an ivec* coordinate, and may be larger than ivec2;
shuffle things around so that this will work.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
.../dri/i965/brw_lower_unnormalized_offset.cpp | 51
++
1
On 10/20/2013 08:12 PM, Armin K. wrote:
On 10/19/2013 02:24 AM, Anuj Phogat wrote:
Setting bilinear_filter flag in case of multisample blits with
GL_LINEAR filter causes incorrect behavior in translate_dst_to_src()
function. This broke Modern Warfare (1, 2 and 3) on SNB, IVB and HSW.
Tested
From: Dave Airlie airl...@redhat.com
+ nvc0 support for demo purposes, will split up later.
So I've done this by just adding pipe cap queries for this stuff,
we might want to add another high level query to say if we are
bothered exposing this stuff.
nouveau can't get the pci device id as it
On 10/26/2013 02:12 AM, Vinson Lee wrote:
Remove dead code left behind by commit
8d7b913e4e089cc8b0b800cbcf80737d0be0a0f7.
Fixes Logically dead code defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/gallium/drivers/svga/svga_draw_elements.c | 6 --
1
On 10/25/2013 05:44 PM, Anuj Phogat wrote:
New functions added by GL_ARB_sample_shading:
glMinSampleShadingARB()
New enums:
GL_SAMPLE_SHADING_ARB
GL_MIN_SAMPLE_SHADING_VALUE_ARB
V2: Update comments.
Create new GL4x.xml.
Remove redundant code in get.c.
Update the API_XML list in
On 10/25/2013 05:45 PM, Anuj Phogat wrote:
Number of samples will be required in fragment shader program by new
GLSL builtin uniform gl_NumSamples.
V2: Use state.numsamples in place of state.num.samples
Use _NEW_BUFFERS flag in place of _NEW_MULTISAMPLE
Signed-off-by: Anuj Phogat
On 10/26/2013 05:55 AM, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
+ nvc0 support for demo purposes, will split up later.
So I've done this by just adding pipe cap queries for this stuff,
we might want to add another high level query to say if we are
bothered exposing this stuff.
Merged the fixes and pushed the result this morning.
Thanks for the help,
Christian.
Am 26.10.2013 01:25, schrieb Marek Olšák:
On Sun, Oct 20, 2013 at 11:57 AM, Christian König
deathsim...@vodafone.de wrote:
Hi Marek,
I've just send out a v6 of the patch, please take a second look. Most
For patches 1 2:
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Sat, Oct 26, 2013 at 7:35 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Both Gallium and i965 subclass gl_transform_feedback_object, which
requires implementing a custom NewTransformFeedback hook. Creating a
helper
This looks good. I recommend porting all_varyings_in_vbos from
st_draw.c to vbo_all_varyings_in_vbos, because it also takes instanced
arrays into account.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Sat, Oct 26, 2013 at 7:35 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Sorry for the weekly delay to answer, I am currently very busy.
Hello,
You can find attached a patch to apply on the include/GL/gl.h file.
This patch aims to fix a build issue with GCC when using the
-DGL_GLEXT_LEGACY, -Werror and -Wundef flags. I have remarked the problem
with Qt 5.1.1
Hi,
I looked at the openmax decoder posted yesterday and have seen that
only two fields are missing to also decode hi10p with the current
vdpau uvd infrastructure in place.
I mailed two patches to the vdpau mailing list in order to get the API
bumped to ship those two fields via the h264
On Fri, Oct 25, 2013 at 10:02 AM, Baptist BENOIST retur...@live.com wrote:
Sorry for the weekly delay to answer, I am currently very busy.
Hello,
You can find attached a patch to apply on the include/GL/gl.h file.
This patch aims to fix a build issue with GCC when using the
FYI, the flags psp-max_gl_xxx_version are incorrect for most (all?)
Gallium drivers.
Marek
On Sat, Oct 26, 2013 at 1:55 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
+ nvc0 support for demo purposes, will split up later.
So I've done this by just adding pipe
On 26.10.2013 16:31, Peter Frühberger wrote:
Hi,
I looked at the openmax decoder posted yesterday and have seen that
only two fields are missing to also decode hi10p with the current
vdpau uvd infrastructure in place.
I mailed two patches to the vdpau mailing list in order to get the API
Signed-off-by: Kai Wasserbäch k...@dev.carbon-project.org
Cc: thomas.stell...@amd.com
---
Hi Tom,
the patches you sent seem to work, but only for in-tree builds. If you push
them out, please also fold the following patch into that series, that ensures
out-of-tree builds work as well.
If ran a
This will let us use strcasecmp() from anywhere inside Mesa without
having to worry about the fact that it doesn't exist in MSVC.
---
src/glsl/glsl_parser.yy | 8 +---
src/mesa/main/imports.h | 1 +
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/glsl/glsl_parser.yy
On 26 October 2013 07:26, Christian König deathsim...@vodafone.de wrote:
Merged the fixes and pushed the result this morning.
Did you by any chance run make check? I'm seeing the following failure:
===
Mesa 10.0.0-devel:
On 18 October 2013 15:44, Eric Anholt e...@anholt.net wrote:
This only operates on constant/uniform values for now, because otherwise
I'd
have to deal with killing my available CSE entries when assignments happen,
and getting even this working in the tree ir was painful enough.
As is, it
These patches add some missing flushing, which appears to help. I'm
still getting GPU hangs, but they're much less frequent, and now have
an IPEHR of MI_SEMAPHORE_MBOX. I suspect those may be due to bugs in
my performance monitoring code, rather than upstream problems.
Xinkai Chen reported that
From the comments above intel_emit_post_sync_nonzero_flush:
[DevSNB-C+{W/A}] Before any depth stall flush (including those
produced by non-pipelined state commands), software needs to first
send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0.
This suggests that every
From: Daniel Vetter daniel.vet...@ffwll.ch
Otherwise the gen6 w/a in the kernel won't kick in and the write will
land nowhere.
Inspired by a patch Ken pointed me at which had the same issue (but
isn't yet merged and also for a gen7+ feature). An audit of the entire
driver didn't reveal any other
Non-pipelined commands need this flush.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index
This is another non-pipelined command that needs a flush on Sandybridge.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
For some reason, we put the flush in the caller, rather than just before
emitting the packet. This is more than a cosmetic problem: BLORP calls
gen6_emit_3dstate_multisample() directly, and so it missed the flush.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
The normal drawing path does this, and it's necessary on Ivybridge,
so let's try it on Sandybridge too. It's not explicitly documented
as necessary, but might help with hangs.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 12
1
From the documentation:
[DevIVB] 3DSTATE_DEPTH_BUFFER must always be programmed along with the
other Depth/Stencil state commands(i.e. 3DSTATE_CLEAR_PARAMS,
3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
We normally do this, but BLORP was failing to do so in the case where it
disables
On 10/26/2013 10:32 AM, Paul Berry wrote:
This will let us use strcasecmp() from anywhere inside Mesa without
having to worry about the fact that it doesn't exist in MSVC.
---
src/glsl/glsl_parser.yy | 8 +---
src/mesa/main/imports.h | 1 +
2 files changed, 2 insertions(+), 7
This is a bit shorter.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index
Currently, we emit one SO_DECL structure per output, so we use the index
in the Outputs[] array as the index into the so_decl[] array as well.
In order to support the fake gl_SkipComponents[1234] varyings from
ARB_transform_feedback3, we'll need to emit SO_DECLs to fill in the
holes between
This depends on ARB_transform_feedback2, so I've predicated it on the
ability to do register writes.
It also depends on ARB_transform_feedback3, which is the only reason we
couldn't expose it previously.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
https://bugs.freedesktop.org/show_bug.cgi?id=70900
Priority: medium
Bug ID: 70900
Keywords: regression
CC: deathsim...@vodafone.de
Assignee: mesa-dev@lists.freedesktop.org
Summary: DispatchSanity_test.GL31_CORE regression
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