From: Kevin Rogovin kevin.rogo...@intel.com
Add extension flag and constant values for ARB_framebuffer_no_attachments.
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/fbobject.c| 1 +
src/mesa/main/framebuffer.c | 1 +
src/mesa/main/mtypes.h | 52
From: Kevin Rogovin kevin.rogo...@intel.com
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 7 +++
src/mesa/drivers/dri/i965/gen8_ps_state.c | 4
2 files changed, 11
From: Kevin Rogovin kevin.rogo...@intel.com
Define enumerations, functions and associated glGet's for
extension ARB_framebuffer_no_attachment.
---
.../glapi/gen/ARB_framebuffer_no_attachments.xml | 33 ++
src/mapi/glapi/gen/Makefile.am | 1 +
From: Noone no...@mailinator.com
For GL_TEXTURE_1D_ARRAY targets we store the depth of the array
in the Height field and leave Depth=1 in the underlying texture
object. When we call intel_miptree_copy_teximage in the process
of re-creating a miptree (possibily because the number of miplevels
has
From: Noone no...@mailinator.com
For GL_TEXTURE_1D_ARRAY targets we store the depth of the array
in the Height field and leave Depth=1 in the underlying texture
object. When we call intel_miptree_copy_teximage in the process
of re-creating a miptree (possibily because the number of miplevels
has
From: Kevin Rogovin kevin.rogo...@intel.com
To assist drivers to implement ARB_framebuffer_no_attachment, provide
a set of convenience functions that check for gl_framebuffer::_HasAttachments
that return the geometry of the gl_framebuffer.
---
src/mesa/main/framebuffer.c | 49
From: Kevin Rogovin kevin.rogo...@intel.com
To prepare for i965 to support ARB_framebuffer_no_attachment, use
the convenience functions mesa_geometry_width/height/layers/samples
to specify the geometry of the render target surfaces to the GPU.
---
src/mesa/drivers/dri/i965/brw_clip_state.c
From: Kevin Rogovin kevin.rogo...@intel.com
Complete the implementation of ARB_framebuffer_no_attachment in Mesa core:
1. Implement _mesa_GetFramebufferParameteriv() and
_mesa_FramebufferParameteri()
2. Additions to _mesa_test_framebuffer_completeness()
---
src/mesa/main/fbobject.c | 153
From: Kevin Rogovin kevin.rogo...@intel.com
Enable extension GL_ARB_framebuffer_no_attachment in i965 for Gen7
and higher. Lower gens are left disabled because those generations
do not support fragment shaders with side effects.
---
src/mesa/drivers/dri/i965/brw_context.c | 6 ++
Please ignore posting: [PATCH] i965:Fix intel_mipmap_copy_teximage for
GL_TEXTURE_1D_ARRAY.
Sighs. I had put the wrong directory when git send-email. My big apologies for
the idiot-noise.
However, please do NOT ignore the patch series for
ARB_framebuffer_no_attachment.
Best Regards,
-Kevin
Ping for the non-OpenCL stuff.
Thanks,
Marek
On Wed, Apr 15, 2015 at 12:19 AM, Marek Olšák mar...@gmail.com wrote:
Hi,
This patch series implements:
- EGL_KHR_fence_sync
- EGL_KHR_wait_sync
- EGL_KHR_cl_event2
These extensions are required by EGL 1.5.
EGL_KHR_fence_sync has piglit
https://bugs.freedesktop.org/show_bug.cgi?id=90162
Bug ID: 90162
Summary: glGetFramebufferAttachmentParameteriv failing if
certain FB attributes are zero
Product: Mesa
Version: 10.1
Hardware: Other
OS:
On Fri, Apr 24, 2015 at 9:43 AM, Zhou, Jammy jammy.z...@amd.com wrote:
Hi Alex,
For the core driver patch:
+config DRM_AMDGPU
+ tristate AMD GPU
+ depends on DRM PCI
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select
On 04/24/2015 09:59 AM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
Define enumerations, functions and associated glGet's for
extension ARB_framebuffer_no_attachment.
---
.../glapi/gen/ARB_framebuffer_no_attachments.xml | 33 ++
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
On 04/24/2015 09:59 AM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
---
There's trailing white space errors in quite a few lines. I noticed that
patch 4 corrects some of these but you should really fix them in this
commit, patch 4 should not touch them.
On 04/24/2015 09:59 AM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
Add
On 04/23/2015 07:28 PM, Ilia Mirkin wrote:
Add the 4.0/4.1/4.2 extensions lists to compute_version. A coule of
extensions aren't in mesa yet, so those are marked with 0 until they
become supported.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
coule - couple.
--
Petri Latvala
I'd enable this if at least GLSL 1.30 was supported. I think drivers
like r300, nv30, i915, and svga shouldn't get this.
Marek
On Fri, Apr 24, 2015 at 3:42 AM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
I'm not sure if we shouldn't enable this everywhere
and
Hi Alex,
For the core driver patch:
+config DRM_AMDGPU
+ tristate AMD GPU
+ depends on DRM PCI
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select FW_LOADER
+select DRM_KMS_HELPER
+ select DRM_KMS_FB_HELPER
+
Functionally everything looks correct to me, as a coding style fix,
don't exceed 80 characters per line, there are few lines that do this.
With that fixed;
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
On 04/24/2015 09:59 AM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
https://bugs.freedesktop.org/show_bug.cgi?id=90162
--- Comment #1 from Martina Kollarova martina.kollar...@intel.com ---
Created attachment 115303
-- https://bugs.freedesktop.org/attachment.cgi?id=115303action=edit
glxinfo.output
--
You are receiving this mail because:
You are the QA Contact
Functionally correct, style nitpicks below, with those fixed;
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
On 04/24/2015 09:59 AM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
To assist drivers to implement ARB_framebuffer_no_attachment, provide
a set of
---
src/gallium/state_trackers/clover/Makefile.sources | 1 -
src/gallium/state_trackers/clover/api/program.cpp | 2 +-
.../state_trackers/clover/core/compiler.hpp| 2 +-
src/gallium/state_trackers/clover/core/error.hpp | 6 ++--
src/gallium/state_trackers/clover/util/compat.cpp |
Since clover should compile use -std=c++11,
compat classes are no longer neccessary
EdB (4):
clover: remove compat class that matche std one
clover: remove compat::string
clover: make module::symbol::name a string
clover: remove util/compat
---
src/gallium/state_trackers/clover/api/program.cpp | 3 +--
src/gallium/state_trackers/clover/core/module.cpp | 21 +
src/gallium/state_trackers/clover/core/module.hpp | 4 ++--
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git
---
src/gallium/state_trackers/clover/api/program.cpp | 2 +-
.../state_trackers/clover/core/compiler.hpp| 14 +--
src/gallium/state_trackers/clover/core/error.hpp | 4 +-
src/gallium/state_trackers/clover/core/program.cpp | 2 +-
.../state_trackers/clover/llvm/invocation.cpp
The extension is currently marked as GLC, so that equates to dummy_true right?
On Fri, Apr 24, 2015 at 9:00 AM, Brian Paul bri...@vmware.com wrote:
Yes, I second that.
-Brian
On 04/24/2015 04:29 AM, Marek Olšák wrote:
I'd enable this if at least GLSL 1.30 was supported. I think drivers
Yes, as long as it's core-only, dummy_true is fine.
Marek
On Fri, Apr 24, 2015 at 3:14 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
The extension is currently marked as GLC, so that equates to dummy_true right?
On Fri, Apr 24, 2015 at 9:00 AM, Brian Paul bri...@vmware.com wrote:
Yes, I second
On Fri, Apr 24, 2015 at 09:59:08AM +0300, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
To prepare for i965 to support ARB_framebuffer_no_attachment, use
the convenience functions mesa_geometry_width/height/layers/samples
to specify the geometry of the render
This change will make the dispatch_sanity test fail.
On Fri, Apr 24, 2015 at 3:05 AM, Matt Turner matts...@gmail.com wrote:
The subject should be prefixed with mesa:
On Thu, Apr 23, 2015 at 11:59 PM, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
Define
Normally we have brief title on the subject line followed by more elaborate
description of the changes. You had:
Subject: [Mesa-dev] [PATCH 3/7] Complete implementation for
ARB_framebuffer_no_attachment in Mesa core: implement
GetFramebufferParameteriv, FramebufferParameteri and
Yes, I second that.
-Brian
On 04/24/2015 04:29 AM, Marek Olšák wrote:
I'd enable this if at least GLSL 1.30 was supported. I think drivers
like r300, nv30, i915, and svga shouldn't get this.
Marek
On Fri, Apr 24, 2015 at 3:42 AM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie
We have to use W/UW type for src1 of the multiply in the MUL/MACH macro,
but in order to read the low 16-bits of each 32-bit integer, we need to
set the appropriate stride.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git
---
docs/relnotes/10.6.0.html| 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 8 ++--
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/docs/relnotes/10.6.0.html b/docs/relnotes/10.6.0.html
index 48f76f9..dbf1229 100644
--- a/docs/relnotes/10.6.0.html
+++
This reverts commit 9f5e5bd34d8ba48c851b442fb88f742b1ba6a571.
I have no idea what made me believe these didn't apply to Gen 7. They
do, and without them we generate bad code that causes failures on Gen 8.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6 +++---
1 file changed, 3
Copy over from brw_fs_visitor.cpp.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 9564764..523e56d 100644
---
If a send message is emitted with a message length that is less than
required for the message then the remaining parameters default to
zero. We can take advantage of this to save a register when a shader
passes constant zeroes as the final coordinates to the sample
function.
I think this might be
On Friday, April 24, 2015 09:59:09 AM kevin.rogo...@intel.com wrote:
From: Kevin Rogovin kevin.rogo...@intel.com
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 7 +++
On Thu, Apr 23, 2015 at 04:50:00PM -0700, Ben Widawsky wrote:
AFAICT, none of the old data was wrong (the gen7 decoder), but it wa smissing
a
bunch of stuff.
Adds a tick (') to denote the beginning of the surface state for easier
reading.
This will be replaced later with some better, but
On Thu, Apr 23, 2015 at 04:50:02PM -0700, Ben Widawsky wrote:
Gen9 surface state is very similar to the previous generation. The important
changes here are aux mode, and the way clear colors work.
NOTE: There are some things intentionally left out of this decoding.
Signed-off-by: Ben
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Mesa 10.5.4 is now available. This release includes fixes for the mesa
state-tracker used by all the gallium drivers, a drirc workaround for
Second Life, plus i965 fixes. For the Android users out there, this release
includes many compilation fixes
On Thu, Apr 23, 2015 at 11:24:11PM -0700, Kenneth Graunke wrote:
This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs.
UMS/IMS differences and Sandybridge textureGather workarounds.
Previously, we just flagged them as Something else.
Signed-off-by: Kenneth Graunke
Now that ARB_texture_stencil8 is supported, this might happen.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/mesa/state_tracker/st_atom_framebuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_atom_framebuffer.c
Currently we're producing errors like
User error: GL_INVALID_OPERATION in glglDeleteProgramsARB(invalid call)
And noop_warn appears to be called with the full function name. Don't
prepend a gl prefix.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/mesa/main/context.c | 4 ++--
1 file
On Fri, Apr 24, 2015 at 05:12:34PM -0700, Anuj Phogat wrote:
On Fri, Apr 24, 2015 at 12:22 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:36PM -0700, Anuj Phogat wrote:
No other path currently supports uploading data to these surfaces.
Matt Turner matts...@gmail.com writes:
+ foreach_block_and_inst(block, fs_inst, inst, cfg) {
+ if ((inst-opcode == SHADER_OPCODE_TEX ||
+ inst-opcode == SHADER_OPCODE_TXF)
+ !inst-shadow_compare) {
+ fs_inst *load_payload = (fs_inst *) inst-prev;
+
+
On Fri, Apr 24, 2015 at 5:15 PM, Neil Roberts n...@linux.intel.com wrote:
Matt Turner matts...@gmail.com writes:
+ foreach_block_and_inst(block, fs_inst, inst, cfg) {
+ if ((inst-opcode == SHADER_OPCODE_TEX ||
+ inst-opcode == SHADER_OPCODE_TXF)
+
On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy axel.d...@ens.fr wrote:
Some applications assume the memory for multilevel
textures is allocated per continuous blocks.
This patch implements that behaviour.
Signed-off-by: Axel Davy axel.d...@ens.fr
---
Le 25/04/2015 00:02, Ilia Mirkin a écrit :
I'm having trouble understanding what you're changing here... perhaps
a better commit description could go a ways to clearing things up?
Were you allocating it a level at a time before? How did that work, I
don't see a per-level structure... I'm
On Fri, Apr 24, 2015 at 6:13 PM, Axel Davy axel.d...@ens.fr wrote:
Le 25/04/2015 00:02, Ilia Mirkin a écrit :
I'm having trouble understanding what you're changing here... perhaps
a better commit description could go a ways to clearing things up?
Were you allocating it a level at a time
On Fri, Apr 24, 2015 at 2:39 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:33PM -0700, Anuj Phogat wrote:
This function will be utilised in later patches.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_context.h
Pohjolainen, Topi topi.pohjolai...@intel.com writes:
On Fri, Feb 27, 2015 at 05:34:55PM +0200, Francisco Jerez wrote:
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +
src/mesa/drivers/dri/i965/brw_eu.h | 24 +++
src/mesa/drivers/dri/i965/brw_eu_emit.c
---
src/glsl/nir/nir_validate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c
index a7aa798..35a853d 100644
--- a/src/glsl/nir/nir_validate.c
+++ b/src/glsl/nir/nir_validate.c
@@ -236,6 +236,8 @@ validate_ssa_def(nir_ssa_def *def,
From: Paul Berry stereotype...@gmail.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/main/dd.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 0c1a13f..a329d9c 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_misc_state.c | 23 +--
src/mesa/drivers/dri/i965/brw_state.h| 12
src/mesa/drivers/dri/i965/brw_state_upload.c
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
git://people.freedesktop.org/~jljusten/mesa i965-cs-atomic-counters-v1
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_state.h| 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c |
Tested on Ivybridge, Haswell and Broadwell.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_compute.c | 39 -
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git
git://people.freedesktop.org/~jljusten/mesa i965-dispatch-compute-v1
Jordan Justen (4):
i965/cs: Emit state base address
i965/state: Emit pipeline select when changing pipelines
i965/cs: Implement brw_emit_gpgpu_walker
i965/cs: Emit MEDIA_STATE_FLUSH after WALKER
Paul Berry (3):
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
From: Paul Berry stereotype...@gmail.com
brw_emit_gpgpu_walker will be implemented in a subsequent patch.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_compute.c| 121 +
From: Paul Berry stereotype...@gmail.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/main/compute.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/compute.c b/src/mesa/main/compute.c
index 575..37a4ba7 100644
---
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_compute.c | 5 +
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index
On Fri, Apr 24, 2015 at 12:22 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:36PM -0700, Anuj Phogat wrote:
No other path currently supports uploading data to these surfaces.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
On Thu, Apr 23, 2015 at 6:10 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:34PM -0700, Anuj Phogat wrote:
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Chris Forbes chr...@ijw.co.nz
---
v2:
* Don't rely on brw_eu* to generate the send instruction. We now
generate the send here, and drop the i965/cs: Add support for the
SEND message that terminates a CS thread brw_eu* patch.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.h
On Fri, Apr 24, 2015 at 4:32 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
This commit switches us from the current setup of using hash sets for
use/def sets to using linked lists. Doing so should save us quite a bit of
memory because we aren't carrying around 3 hash sets per register and 2
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 6 ++
src/mesa/drivers/dri/i965/brw_cs.cpp | 28
src/mesa/drivers/dri/i965/brw_shader.cpp | 4
src/mesa/drivers/dri/i965/brw_shader.h | 3 +++
4
From: Paul Berry stereotype...@gmail.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/main/state.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/mesa/main/state.c b/src/mesa/main/state.c
index
Add some values for gen7 gen8. These are the number threads in a
subslice.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
src/mesa/drivers/dri/i965/brw_cs.cpp| 8
src/mesa/drivers/dri/i965/brw_fs.cpp| 11 +++
src/mesa/drivers/dri/i965/brw_program.c | 13 +++--
4 files
On Thu, Apr 23, 2015 at 6:05 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:35PM -0700, Anuj Phogat wrote:
Patch sets the alignments for texture and renderbuffer surfaces.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
From: Paul Berry stereotype...@gmail.com
jordan.l.jus...@intel.com:
* Added brw_cs_prog_key structure
* Added brw_cs_prog_data::dispatch_grf_start_reg_16
* Added brw_cs_prog_data::no_8
* Added brw_cs_prog_data::local_size
* Added brw_cs_prog_data::simd_size
Signed-off-by: Jordan Justen
git://people.freedesktop.org/~jljusten/mesa i965-cs-prog-v2
These patches could use review:
* [08/20] i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE
* [10/20] i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE
* [13/20] i965/fs: Support compute programs in fs_visitor
*
From: Paul Berry stereotype...@gmail.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/program/program.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/mesa/program/program.h
From: Paul Berry stereotype...@gmail.com
At the moment it's not wired up to anything. Later patches will hook
it up to the compute shader back-end.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/intel_debug.c
From: Paul Berry stereotype...@gmail.com
Also add code to brw_upload_state to set it when the compute program
changes.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
From: Paul Berry stereotype...@gmail.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/program/program.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 5 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index
v2:
* Do more work at the visitor level. g0 is loaded and sent to the
generator now.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 19 +++
2 files changed, 20
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_state_dump.c | 3 +++
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
3 files changed, 6
Suggested-by: Kristian Høgsberg k...@bitplanet.net
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 32
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
3
---
src/glsl/nir/nir_from_ssa.c | 11 +--
src/glsl/nir/nir_lower_locals_to_regs.c | 14 ++
src/glsl/nir/nir_lower_to_source_mods.c | 20
src/glsl/nir/nir_lower_vars_to_ssa.c| 3 ++-
src/glsl/nir/nir_opt_gcm.c | 14
This commit switches us from the current setup of using hash sets for
use/def sets to using linked lists. Doing so should save us quite a bit of
memory because we aren't carrying around 3 hash sets per register and 2 per
SSA value. It should also save us CPU time because adding/removing things
---
src/glsl/nir/glsl_to_nir.cpp | 2 +-
src/glsl/nir/nir.h | 13 +++--
src/glsl/nir/nir_builder.h | 6 ++
src/glsl/nir/nir_lower_samplers.cpp| 5 ++---
src/glsl/nir/nir_lower_tex_projector.c | 5 ++---
src/glsl/nir/nir_search.c
This patch series is an experiment that I ran this week to see what would
happen if we used a linked list instead of a hash set for use/def sets in
NIR. The first 5 patches are cleanups that we probably want anyway. The
6th adds a C-based linked list to NIR. The last 3, which need to be
squashed
This commit adds a C-based linked list implementation for NIR. Unlike
exec_list in glsl/list.h, there is no C++ API. Also, this list is based on
wl_list (from the Wayland project) which is, in turn, based on the kernel
list. As such, it should be fairly familiar to people who have done
anything
We were rolling our own rewrite_src variant in copy-propagation. Let's
stop doing that and use the ones in core NIR.
---
src/glsl/nir/nir_opt_copy_propagate.c | 71 +--
1 file changed, 10 insertions(+), 61 deletions(-)
diff --git
The out-of-SSA pass was one of the first passes written when getting SSA
up-and-going (for obvious reasons). As such, it came before a lot of the
nifty SSA-based helpers were introduced. This commit modernizes it so that
we're no longer doing nearly as much manual banging on use/def sets.
---
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 80
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_state.h| 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +
v2:
* Clean out some unneeded code copied from run_fs (krh)
* Always use NIR
* Split shader time out into a separate commit
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 61
v2:
* Don't bother checking for 'gen 5' (krh)
* Populate sampler data in key (krh)
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_cs.cpp | 224 +++
Remove comment These were copied from Haswell GT1, above.. Many of
these numbers have been modified by this point, so the HSW GT1
reference no longer seems helpful.
The comment Thread counts and URB limits are placeholders, and may
not be accurate. is retained for now.
Signed-off-by: Jordan
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_cs.cpp| 48 +
src/mesa/drivers/dri/i965/brw_cs.h | 2 ++
---
src/glsl/nir/nir.c | 22 ++
src/glsl/nir/nir.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 4cc074b..b8f5dd4 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -1895,6 +1895,28 @@
One of the side-effects of using a linked list for use/def sets is that you
can no longer simply copy them around. There were a couple of places in
the texture lowering passes that realloced or used memmove on lists of
sources. Instead, this commit adds a helper for moving a source and uses
it
https://bugs.freedesktop.org/show_bug.cgi?id=90167
Bug ID: 90167
Summary: [softpipe] piglit
depthstencil-default_fb-drawpixels-32f_24_8_rev
regression
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
On Fri, Apr 24, 2015 at 7:32 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
This commit adds a C-based linked list implementation for NIR. Unlike
exec_list in glsl/list.h, there is no C++ API. Also, this list is based on
wl_list (from the Wayland project) which is, in turn, based on the
On Thu, Apr 23, 2015 at 4:51 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:27PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++
On Fri, Feb 27, 2015 at 05:34:55PM +0200, Francisco Jerez wrote:
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +
src/mesa/drivers/dri/i965/brw_eu.h | 24 +++
src/mesa/drivers/dri/i965/brw_eu_emit.c| 169
+
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