On Thu, Jul 16, 2015 at 06:55:26PM +0200, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/si_compute.c | 2 +-
src/gallium/drivers/radeonsi/si_shader.c | 8 +++-
On Thu, Jul 16, 2015 at 06:55:27PM +0200, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Cc: 10.5 10.6 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_shader.c| 49
++---
On 2015-07-16 13:59:45, Jason Ekstrand wrote:
On Jul 16, 2015 2:00 PM, Jordan Justen jordan.l.jus...@intel.com
wrote:
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var num_vars' failed.
Best guess is
On Tue, Jul 14, 2015 at 9:56 AM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
This patch rewrites the logic for determining which method we using for
mapping
a miptree. It is my intention that that this patch, the required patches
before
this do not change functionality, or if they do,
On 13/07/15 13:06, Samuel Iglesias Gonsálvez wrote:
On 11/07/15 19:38, Renaud Gaubert wrote:
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void
On Wed, 2015-07-15 at 11:02 -0700, Connor Abbott wrote:
On Wed, Jul 15, 2015 at 7:49 AM, Iago Toral ito...@igalia.com wrote:
Hi,
when we sent the patches for the new nir-vec4 backend we mentioned that
we had a few dEQP tests that would fail to link because of register
spilling. Now that
Ping. Any possibility of a patch review? FWIW, the patch itself is
pretty small.
On 26/06/15 13:47, Alejandro Piñeiro wrote:
As functions are inlined, and nir_lower_global_vars_to_local gets
run, all global variables are lowered to local variables.
---
Jason Enkstrand already confirmed that
On Wed, Jul 15, 2015 at 12:20:15PM -0700, Kristian Høgsberg wrote:
On Wed, Jul 15, 2015 at 10:22 AM, Kenneth Graunke kenn...@whitecape.org
wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
The kernel actually waits forever when supplied a timeout value 0,
rather than returning
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
v2: The fix for the darkness in Ubuntu Unity is in the hunk
with the 4-line comment.
---
src/gallium/state_trackers/dri/dri2.c | 2 ++
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Anatoli Antonovitch anatoli.antonovi...@amd.com
---
src/gallium/state_trackers/dri/dri_query_renderer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/state_trackers/dri/dri_query_renderer.c
On Thu, Jul 16, 2015 at 3:06 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
v2: The fix for the darkness in Ubuntu Unity is in the hunk
with the 4-line comment.
---
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
v2: add missing break
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -285,6 +285,8 @@ struct dri2_egl_config
_EGLConfig base;
const
On 16/07/15 05:30, Matt Turner wrote:
---
This will go in before my double promotion series which uses exp2f.
include/c99_math.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/c99_math.h b/include/c99_math.h
index 7ed7cc2..0ca5a73 100644
--- a/include/c99_math.h
+++
On Thu, Jul 16, 2015 at 3:14 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Anatoli Antonovitch anatoli.antonovi...@amd.com
---
src/gallium/state_trackers/dri/dri_query_renderer.c | 14 ++
1 file changed, 14
On Wed, 2015-07-15 at 11:53 -0700, Eric Anholt wrote:
Timothy Arceri t_arc...@yahoo.com.au writes:
Hi guys,
As I've mentioned a couple of times in previous patches some of the cts
AoA
tests are taking very long time to compile. This is due to excessive
optimisation passes mainly
On 07/15/2015 07:15 PM, Ilia Mirkin wrote:
The reason why you chose to call select_tex_image() several times
through a get_tex_image flow eludes me. Why not just get it once at
the beginning and pass it around? The old APIs also used a
gl_texture_image and not a gl_texture_object. (Obviously the
On 16/07/15 14:38, Marek Olšák wrote:
On Thu, Jul 16, 2015 at 3:06 PM, Emil Velikov emil.l.veli...@gmail.com
wrote:
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
v2: The fix for the darkness in Ubuntu Unity is in the hunk
with the
I'm not familiar with DRI3, but it looks like sRGB visuals should work
with DRI3 too.
Now that I think about it, I can drop the change in
dri2_drawable_get_buffers, because it's not needed with the change in
dri_drawable_get_format.
Marek
On Thu, Jul 16, 2015 at 4:08 PM, Emil Velikov
Typically BAD_FILE sources are used to mark a source as not present
what implies that no registers are read. This will become much more
frequent with logical send opcodes which have a large number of
sources, many of them optionally used and marked as BAD_FILE when they
aren't applicable. It
On Jul 15, 2015 11:20 PM, Iago Toral ito...@igalia.com wrote:
On Wed, 2015-07-15 at 11:02 -0700, Connor Abbott wrote:
On Wed, Jul 15, 2015 at 7:49 AM, Iago Toral ito...@igalia.com wrote:
Hi,
when we sent the patches for the new nir-vec4 backend we mentioned
that
we had a few dEQP
When the width field was removed from fs_reg the BROADCAST handling
code in opt_algebraic() started to miss a number of trivial
optimization cases resulting in the ugly indirect-addressing sequence
to be emitted unnecessarily for some variable-indexed texturing and
UBO loads regardless of one of
This is essentially the same problem fixed in an earlier patch for
immediates. Setting the stride to zero will be particularly useful
for my future SIMD lowering pass, because we will be able to just
check whether the stride of a source register is zero and skip
emitting the copies required to
This fixes essentially the same problem as for immediates. Registers
of the UNIFORM file are typically accessed according to the formula:
read_uniform(r, channel_index, array_index) =
read_element(r, channel_index * 0 + array_index * 1)
Which matches the general direct addressing formula
This pass will house ad-hoc lowering code for several send
message-like virtual opcodes that will represent their logically
independent arguments as separate instruction sources rather than as a
single payload blob. This pass will basically just take the separate
arguments that are supposed to be
And start using it in fs_builder::LOAD_PAYLOAD(). This will be used
to emit logical send message opcodes which have an unusually large
number of arguments.
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git
This lowering pass implements an algorithm to expand SIMDN
instructions into a sequence of SIMDM instructions in cases where the
hardware doesn't support the original execution size natively for some
particular instruction. The most important use-cases are:
- Lowering send message instructions
In cases where the color0 argument wasn't being provided,
emit_single_fb_writes() would take the alpha channel directly from the
visitor state instead of taking it from its arguments. This sort of
hack didn't fit nicely into the logical send-message approach because
all parameters of the
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 --
src/mesa/drivers/dri/i965/brw_wm.c | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 08d9abf..c489010 100644
We were previously guessing the half based on the EOT flag which seems
rather gross.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
The logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
that make up the payload separately as individual sources, like:
fb_write_logical null, color0, color1, src0_alpha,
src_depth,
On 16/07/15 15:31, Marek Olšák wrote:
I'm not familiar with DRI3, but it looks like sRGB visuals should work
with DRI3 too.
Now that I think about it, I can drop the change in
dri2_drawable_get_buffers, because it's not needed with the change in
dri_drawable_get_format.
In theory one
It's surprising that we weren't checking for this already. A future
patch will cause code like the following to be emitted:
MOV(16) tmp1:uw, src
MOV(8) dst1:ud, tmp8,8,1:ud
The second MOV comes from the expansion of a LOAD_PAYLOAD header copy,
so I don't have control over its types. Copy
This is now unused.
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 -
src/mesa/drivers/dri/i965/brw_fs.h | 4 ---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 35 --
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 --
4 files changed, 42
This shouldn't have any effect because we don't emit logical
framebuffer writes yet.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ae050b7..70fdc5e 100644
---
There's no need to initialize the wrong half of oMask in the payload
when we're doing an 8-wide framebuffer write because it will be
ignored by the hardware anyway. By doing it this way we can let the
SIMD lowering pass split the sample_mask source as a regular
per-channel source, otherwise we
This does essentially the same thing as
fs_visitor::emit_single_fb_write(), with some slight differences:
- We don't have to worry about exec_size and use_2nd_half anymore,
16-wide sources have already been lowered to 8-wide thanks to the
previous commit and the manual argument unzipping
Flatten the if ladder to match the way that the ordering of these
fields is specified in the hardware documentation a bit more closely.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git
The only non-trivial thing it still has to do is figure out where to
take the src/dst depth values from and predicate the instruction if
discard is in use. The manual SIMD unrolling logic in the dual-source
case goes away because this is now handled transparently by the SIMD
lowering pass.
---
And update the comment.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index c489010..b5a42b1 100644
---
Sssort of. But drivers that were expecting this to happen will now
need to do the compare themselves. For example nv50 (and I assume
nvc0) just always copy the new values in and set the dirty flag.
Really you're just pushing this down into the driver, which is
reasonable, but in the process you're
Hi Marek,
On 12 July 2015 at 20:10, Marek Olšák mar...@gmail.com wrote:
Hi,
These are the last EGL 1.5 bits. I have fixed the Ubuntu Unity darkness issue
in patch 1 and dropped the ugly workaround from libGL.
Please help review the patches.
Aside from a small issue in patch #2 the series
From: Marek Olšák marek.ol...@amd.com
---
src/mesa/state_tracker/st_atom_sampler.c | 9 -
src/mesa/state_tracker/st_cb_drawpixels.c | 9 -
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_sampler.c
From: Marek Olšák marek.ol...@amd.com
There is no need for this.
---
src/gallium/auxiliary/cso_cache/cso_context.c | 44 ---
src/gallium/auxiliary/cso_cache/cso_context.h | 13
src/mesa/state_tracker/st_atom_clip.c | 2 +-
3 files changed, 1
From: Marek Olšák marek.ol...@amd.com
None of the draw states are used here.
This fixes a crash in piglit: ext_framebuffer_blit/blit-early
Calling st_manager_validate_framebuffers is the minimum requirement here.
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_cb_blit.c | 4
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/tgsi/tgsi_dump.c| 19 +++
src/gallium/auxiliary/tgsi/tgsi_dump.h| 5 +
src/gallium/auxiliary/util/u_dump_state.c | 7 +++
3 files changed, 23 insertions(+), 8 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
Not needed for other shader stages.
---
src/gallium/auxiliary/cso_cache/cso_context.c | 103 +-
src/gallium/auxiliary/cso_cache/cso_context.h | 4 +-
src/gallium/auxiliary/hud/hud_context.c | 4 +-
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/cso_cache/cso_context.c | 28 +++
src/gallium/auxiliary/cso_cache/cso_context.h | 4 ++--
src/gallium/auxiliary/hud/hud_context.c | 4 ++--
src/gallium/auxiliary/postprocess/pp_run.c| 4 ++--
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/cso_cache/cso_context.c | 39 +++
src/gallium/auxiliary/cso_cache/cso_context.h | 6 ++---
2 files changed, 12 insertions(+), 33 deletions(-)
diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/util/u_dump.h | 20 ++-
src/gallium/auxiliary/util/u_dump_defines.c | 41 +
src/gallium/auxiliary/util/u_dump_state.c | 233 ++--
3 files changed, 241 insertions(+), 53 deletions(-)
diff
From: Marek Olšák marek.ol...@amd.com
Drivers can do this better, because they can skip redundant state changes
at per-slot granularity.
---
src/gallium/auxiliary/cso_cache/cso_context.c | 28 ++-
1 file changed, 2 insertions(+), 26 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
Broken by f1be3d8cdde17a9b9ae283e1bab2f46b992d3bf3, which returns NULL
if no commands have been submitted.
---
src/gallium/include/pipe/p_context.h | 5 -
src/gallium/state_trackers/dri/dri2.c | 14 ++
2 files changed, 6 insertions(+), 13
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/tests/trivial/quad-tex.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/tests/trivial/quad-tex.c
b/src/gallium/tests/trivial/quad-tex.c
index daae577..c019c7bb 100644
---
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/postprocess/pp_colors.c | 4 ++--
src/gallium/auxiliary/postprocess/pp_mlaa.c | 23 ++-
src/gallium/auxiliary/util/u_blit.c | 6 --
3 files changed, 20 insertions(+), 13 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
and make si_init_config static
---
src/gallium/drivers/radeonsi/si_pipe.c | 13 ++---
src/gallium/drivers/radeonsi/si_state.c | 6 +-
src/gallium/drivers/radeonsi/si_state.h | 1 -
3 files changed, 7 insertions(+), 13 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
Copied from r600g. pipe_resource can be shared by multiple threads, so we
shouldn't change it.
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 -
src/gallium/drivers/radeonsi/si_blit.c| 201 +++---
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_compute.c | 2 +-
src/gallium/drivers/radeonsi/si_shader.c | 8 +++-
src/gallium/drivers/radeonsi/si_shader.h | 3 +--
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
Cc: 10.5 10.6 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_shader.c| 49 ++---
src/gallium/drivers/radeonsi/si_shader.h| 1 +
src/gallium/drivers/radeonsi/si_state_shaders.c | 8 +---
3 files
From: Marek Olšák marek.ol...@amd.com
buffer_unmap is currently a no-op on radeon and done correctly on amdgpu.
I plan to fix it for radeon, but before that, all occurences of buffer_unmap
that can negatively affect performance in the future must be removed.
There are 2 reasons for removing
From: Marek Olšák marek.ol...@amd.com
This has been a no-op due to performance concerns. From now on, drivers
should decide when they don't want to unmap, not the winsys.
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 29 +--
On Tue 14 Jul 2015, Ben Widawsky wrote:
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than
On Thu, Jul 16, 2015 at 8:05 PM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
There is no need for this.
v2: handle redundant clip state changes in st/mesa
---
src/gallium/auxiliary/cso_cache/cso_context.c | 44
---
On Tue 14 Jul 2015, Ben Widawsky wrote:
This patch rewrites the logic for determining which method we using for
mapping
a miptree. It is my intention that that this patch, the required patches
before
this do not change functionality, or if they do, it's in very obscure an
unobservable
From: Marek Olšák marek.ol...@amd.com
An alternative (and ugly) solution to the current clover issue.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 12
src/gallium/drivers/radeon/r600_pipe_common.h | 3 +++
src/gallium/drivers/radeonsi/si_hw_context.c | 10 --
3
From: Roland Scheidegger srol...@vmware.com
In particular, we were incorrectly accepting s3tc (and lots of others)
for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d
targets. At this time, the only allowed formats for these calls are the
bptc ones, since none of the specific
On 07/16/2015 03:15 PM, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
In particular, we were incorrectly accepting s3tc (and lots of others)
for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d
targets. At this time, the only allowed formats for these
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var num_vars' failed.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Jason Ekstrand ja...@jlekstrand.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ---
1
Thanks for the reviewing.
The patches that are missing Rbs are:
23-24, 26-43, 45-46.
The patches have been on the mailing list for one month. It looks like
I won't get any more reviews. :(
Marek
On Fri, Jun 19, 2015 at 12:46 PM, Kenneth Graunke kenn...@whitecape.org wrote:
I made some
From: Marek Olšák marek.ol...@amd.com
There is no need for this.
v2: handle redundant clip state changes in st/mesa
---
src/gallium/auxiliary/cso_cache/cso_context.c | 44 ---
src/gallium/auxiliary/cso_cache/cso_context.h | 13
On Sat, Jun 20, 2015 at 12:08 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On Wednesday, June 17, 2015 01:01:21 AM Marek Olšák wrote:
From: Fabian Bieler fabianbie...@fastmail.fm
Similar to gl_ClipDistance - gl_ClipDistanceMESA
---
src/glsl/Makefile.sources | 1 +
On Jul 16, 2015 2:00 PM, Jordan Justen jordan.l.jus...@intel.com wrote:
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var num_vars' failed.
Best guess is that you should just fix regs_read to return the right value
(1 in this
Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
On Thu, Jul 16, 2015 at 5:05 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:
This fixes a compilation warning introduced in commit 05a12c5
(gallium: add interface for writable shader images).
While we are at it, fix indentation and rename
On Sat, Jul 11, 2015 at 02:35:53PM +0300, Francisco Jerez wrote:
Tom Stellard thomas.stell...@amd.com writes:
pipe_context::flush() can return a NULL fence if the queue is already
empty, so we should not assume that an event with a NULL fence
has the status of CL_QUEUED.
This seems
On Wed 15 Jul 2015, Anuj Phogat wrote:
On Tue, Jul 14, 2015 at 9:56 AM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
At the crux of this change is moving whether or not we can even use the
hardware
blitter into the can_blit_slice check. Fundamentally this makes sense as
blitting a
This fixes a compilation warning introduced in commit 05a12c5
(gallium: add interface for writable shader images).
While we are at it, fix indentation and rename parameters according to
the gallium interface.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
On Tue, Jun 23, 2015 at 2:04 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On Wednesday, June 17, 2015 01:01:24 AM Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
There is no way to lower them, because the array sizes are unknown
at compile time.
Based on a patch from: Fabian
From: Marek Olšák marek.ol...@amd.com
There is no way to lower them, because the array sizes are unknown
at compile time.
Based on a patch from: Fabian Bieler fabianbie...@fastmail.fm
v2: add comments
---
src/glsl/ir_optimization.h | 5 +-
On Friday, July 03, 2015 10:00:33 AM Abdiel Janulgue wrote:
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
On Tuesday, July 07, 2015 11:53:29 AM Abdiel Janulgue wrote:
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When
On Tuesday, July 07, 2015 11:50:21 AM Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is
Both are
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Jul 16, 2015 5:12 PM, Jordan Justen jordan.l.jus...@intel.com wrote:
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var num_vars' failed.
Signed-off-by: Jordan
On Jul 16, 2015 4:35 PM, Jordan Justen jordan.l.jus...@intel.com wrote:
On 2015-07-16 13:59:45, Jason Ekstrand wrote:
On Jul 16, 2015 2:00 PM, Jordan Justen jordan.l.jus...@intel.com
wrote:
This prevents an assertion failure in brw_fs_live_variables.cpp,
On 2015-07-16 14:37:59, Jason Ekstrand wrote:
On Jul 16, 2015 4:35 PM, Jordan Justen jordan.l.jus...@intel.com
wrote:
On 2015-07-16 13:59:45, Jason Ekstrand wrote:
On Jul 16, 2015 2:00 PM, Jordan Justen
jordan.l.jus...@intel.com
wrote:
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var num_vars' failed.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Jason Ekstrand ja...@jlekstrand.net
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file
https://bugs.freedesktop.org/show_bug.cgi?id=91290
Vinson Lee v...@freedesktop.org changed:
What|Removed |Added
Keywords||bisected
--
You are
On Thu, Jul 16, 2015 at 11:49 AM, Chad Versace chad.vers...@intel.com wrote:
On Tue 14 Jul 2015, Ben Widawsky wrote:
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity,
I
chose not to touch
On Jul 16, 2015 5:03 PM, Jordan Justen jordan.l.jus...@intel.com wrote:
On 2015-07-16 14:37:59, Jason Ekstrand wrote:
On Jul 16, 2015 4:35 PM, Jordan Justen jordan.l.jus...@intel.com
wrote:
On 2015-07-16 13:59:45, Jason Ekstrand wrote:
On Jul 16, 2015 2:00 PM,
From: Connor Abbott connor.w.abb...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 0db1fc3..62cdbd4 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@
From: Connor Abbott connor.w.abb...@intel.com
This will split the block containing the instruction and put the CF node
in between.
v2: (by Kenneth Graunke)
- Simplify split_block_after_instr()'s implementation by using
split_block_end() rather than duplicating code.
- Fix a bug in
From: Connor Abbott connor.w.abb...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index e9a506c..0db1fc3 100644
--- a/src/glsl/nir/nir.h
+++
R-B me too
On Jul 16, 2015 5:19 PM, Kenneth Graunke kenn...@whitecape.org wrote:
From: Connor Abbott connor.w.abb...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/glsl/nir/nir.h
R-B me too
On Jul 16, 2015 5:19 PM, Kenneth Graunke kenn...@whitecape.org wrote:
From: Connor Abbott connor.w.abb...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir.h
On Jul 16, 2015 5:19 PM, Kenneth Graunke kenn...@whitecape.org wrote:
From: Connor Abbott connor.w.abb...@intel.com
This will split the block containing the instruction and put the CF node
in between.
v2: (by Kenneth Graunke)
- Simplify split_block_after_instr()'s implementation by using
On Friday, June 26, 2015 01:47:48 PM Alejandro Piñeiro wrote:
As functions are inlined, and nir_lower_global_vars_to_local gets
run, all global variables are lowered to local variables.
---
Jason Enkstrand already confirmed that global support is not needed
on the bug open for the nir/vec4
Seems reasonable.
Please, let me know the result of the full piglit run.
If everything is okay, this patch is :
Reviewed-by: Samuel Pitoiset samuel.pitoi...@gmail.com
On 13/07/2015 20:08, Ilia Mirkin wrote:
This was, btw, introduced in commit 3a8ae6ac243b (nvc0: adapt to new
clip state). Back
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_read: Assertion `var num_vars' failed.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Jason Ekstrand ja...@jlekstrand.net
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++
1 file changed, 3
On Friday, July 03, 2015 10:00:30 AM Abdiel Janulgue wrote:
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
execbuffer flags.
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