Re: [Mesa-dev] [PATCH] mesa: use strtok_s for strtok_r on windows

On 09/30/2015 04:06 PM, Brian Paul wrote: On 09/30/2015 12:19 AM, Tapani Pälli wrote: https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx Signed-off-by: Tapani Pälli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183 --- src/mesa/main/imports.h | 3 +++

Re: [Mesa-dev] [PATCH] i965/vec4: copy abs/negate modifiers on src/dst_reg conversion constructors

On Wed, Sep 30, 2015 at 10:38 AM, Jason Ekstrand wrote: > I'm not sure if this makes sense. I can see how it would be useful > (less information lost when going src_reg -> dst_reg -> src_reg). > However, it seems wrong to me to assume that dst_reg.abs or > dst_reg.negate

Re: [Mesa-dev] [PATCH 1/2] st/dri: don't use _ctx in client_wait_sync

On Sun, Sep 27, 2015 at 8:02 AM, Albert Freeman wrote: > On 25 September 2015 at 23:49, Marek Olšák wrote: >> From: Marek Olšák >> >> Not needed and it can be NULL. >> >> Cc: 10.6 11.0 >> ---

Re: [Mesa-dev] [PATCH 03/23] nir/lower_io: Switch on shader stage for inputs in load_op().

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote: > The next commit will introduce a new intrinsic for shaders which process > multiple vertices (i.e. geometry, tessellation). This plumbing allows > us to generate different intrinsics based on the shader stage.

Re: [Mesa-dev] [PATCH] i965/vec4: copy abs/negate modifiers on src/dst_reg conversion constructors

On Wed, Sep 30, 2015 at 11:03 AM, Alejandro Piñeiro wrote: > > > On 30/09/15 19:38, Jason Ekstrand wrote: >> I'm not sure if this makes sense. I can see how it would be useful >> (less information lost when going src_reg -> dst_reg -> src_reg). >> However, it seems wrong to

Re: [Mesa-dev] [PATCH 10/23] i965/vs: Simplify fs_visitor's ATTR file.

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote: > Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of > compilation, assign_vs_urb_setup() translated those into GRF units, > and converted ATTR to HW_REGs. > > This patch moves the transslation

[Mesa-dev] [Bug 92173] [regression, bisected] commit 266d05a broke WebGL-Water Caustics on NI/Turks (6670)

https://bugs.freedesktop.org/show_bug.cgi?id=92173 --- Comment #2 from Tapani Pälli --- (In reply to Tapani Pälli from comment #1) > this bug is likely a duplicate for #92122 having said that it seems unlikely that the bug would cause gpu hangs or slow downs but likely just

[Mesa-dev] [PATCH] i965/vec4: copy abs/negate modifiers on src/dst_reg conversion constructors

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index c61b385..121e698 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++

Re: [Mesa-dev] [PATCH] i965/vec4: copy abs/negate modifiers on src/dst_reg conversion constructors

On 30/09/15 19:38, Jason Ekstrand wrote: > I'm not sure if this makes sense. I can see how it would be useful > (less information lost when going src_reg -> dst_reg -> src_reg). > However, it seems wrong to me to assume that dst_reg.abs or > dst_reg.negate means anything useful. Hmm, true.

Re: [Mesa-dev] [PATCH 05/23] nir: Introduce new nir_intrinsic_load_per_vertex_input intrinsics.

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote: > Geometry and tessellation shaders process multiple vertices; their > inputs are arrays indexed by the vertex number. While GLSL makes > this look like a normal array, it can be very different behind the > scenes. >

Re: [Mesa-dev] [PATCH 12/23] i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke wrote: > diff --git a/src/mesa/drivers/dri/i965/brw_inst.h > b/src/mesa/drivers/dri/i965/brw_inst.h > index c5132ba..b551334 100644 > --- a/src/mesa/drivers/dri/i965/brw_inst.h > +++ b/src/mesa/drivers/dri/i965/brw_inst.h >

[Mesa-dev] [PATCH] radeonsi: don't set DATA_FORMAT if ADD_TID_ENABLE is set on VI (v2)

From: Marek Olšák This can cause incorrect address calculations and hangs. v2: do it properly Cc: mesa-sta...@lists.freedesktop.org Tested-and-Reviewed-by: Christian König --- src/gallium/drivers/radeonsi/si_descriptors.c | 9 - 1 file

Re: [Mesa-dev] [PATCH 0/3][RFC] Improve GLSL support of GL_ARB_separate_shader_objects

On Fri, 25 Sep 2015 16:40:31 -0700 Ian Romanick wrote: > On 09/20/2015 01:15 PM, Gregory Hainaut wrote: > > Current GLSL badly optimizes the code making it incompatible with the > > GL_ARB_separate_shader_objects extension. > > > > Typical example of the current behavior:

Re: [Mesa-dev] [PATCH 12/23] i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.

On Wednesday, September 30, 2015 11:23:48 AM Matt Turner wrote: > On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke > wrote: > > diff --git a/src/mesa/drivers/dri/i965/brw_inst.h > > b/src/mesa/drivers/dri/i965/brw_inst.h > > index c5132ba..b551334 100644 > > ---

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote: > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: > > Hi ilia, > > > > On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote: > >> Hi Samuel, and any other onlookers, > >> > >> I was wondering why the decision was made to

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote: > On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote: > > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote: > >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: > >> > Hi ilia, > >> > > >> > On Tue,

Re: [Mesa-dev] [PATCH 08/70] i965: Remove early release of DRI2 miptree

On 30/09/15 00:26, Chad Versace wrote: On Mon 28 Sep 2015, Martin Peres wrote: On 28/09/15 17:27, Emil Velikov wrote: Hi all, On 17 August 2015 at 19:06, Chad Versace wrote: On Fri 14 Aug 2015, Chris Wilson wrote: On Thu, Aug 13, 2015 at 09:58:52PM -0700, Kenneth

[Mesa-dev] [PATCH 14/23] i965: Introduce a brw_vue_prog_data::include_vue_handles flag.

Tessellation shaders and SIMD8 geometry shaders may need to resort to the pull model for inputs at times. When set, the state upload code will tell the hardware to provide URB handles for input data. Signed-off-by: Kenneth Graunke ---

[Mesa-dev] [PATCH 17/23] i965: Make emit_urb_writes() reserve space for GS header information.

Geometry shaders have additional header data at the beginning of their output URB entries. Shaders that use EndPrimitive() or multiple streams have a control data header; shaders with a dynamic vertex count have an additional vec4 slot to hold the 32-bit vertex count (and 96 bits of padding).

[Mesa-dev] [PATCH 21/23] i965: Implement gl_InvocationID.

It's stored in bits 31:27 of g1 (along with the URB handles). Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp

[Mesa-dev] [PATCH 18/23] i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.

This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs, which controls whether or not to use SIMD8 geometry shaders. For now, we control it via a new environment variable, INTEL_SCALAR_GS. This provides a convenient way to try it out. Signed-off-by: Kenneth Graunke

[Mesa-dev] [PATCH 15/23] i965: Make fs_visitor::emit_urb_writes reusable for scalar GS.

GS doesn't have ClampVertexColor, and we don't want to go through VS structures. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 08/23] i965/vs: Fix a subtlety in the nr_attributes == 0 workaround.

nr_attributes is used to compute first_non_payload_grf, which is the first register we're allowed to use for ordinary register allocation. The hardware requires us to read at least one pair of values, but we're completely free to overwrite that garbage register with whatever we like. Instead of

[Mesa-dev] [PATCH 10/23] i965/vs: Simplify fs_visitor's ATTR file.

Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of compilation, assign_vs_urb_setup() translated those into GRF units, and converted ATTR to HW_REGs. This patch moves the transslation earlier, making ATTR work in terms of GRF units from the beginning. assign_vs_urb_setup() simply

[Mesa-dev] [PATCH 02/23] i965/nir: Refactor input/output lowering setup into helpers.

The code for input lowering is going to get significantly more complicated shortly, so I wanted to pull it out. Vertex shader inputs are handled nearly identically regardless of vec4/scalar mode, so I opted to not split that. I thought about having each function actually do the lowering, but one

[Mesa-dev] [PATCH 11/23] i965/gs: Make MAX_GS_INPUT_VERTICES a #define in brw_context.h.

For scalar VS, I'll need this in brw_fs.cpp as well. It seems silly to redeclare it in three places. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 2 --

[Mesa-dev] [PATCH] mesa/uniforms: fix get_uniform for doubles

The initial glGetUniformdv support didn't cover all the casting cases that are apparantly legal, and cts seems to test for them. I've updated the piglit test to cover these cases now. cc: "11.0" Signed-off-by: Dave Airlie ---

Re: [Mesa-dev] [PATCH] i965/cs: Upload UBO/SSBO surfaces

Reviewed-by: Samuel Iglesias Gonsálvez On 30/09/15 02:12, Jordan Justen wrote: > Signed-off-by: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_context.h | 2 +- > src/mesa/drivers/dri/i965/brw_state.h| 1 + >

[Mesa-dev] [PATCH] mesa: use strtok_s for strtok_r on windows

https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx Signed-off-by: Tapani Pälli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183 --- src/mesa/main/imports.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/main/imports.h

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote: > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote: >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: >> > Hi ilia, >> > >> > On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote: >> >> Hi Samuel,

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote: > Ilia Mirkin writes: > > > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: > >> Hi ilia, > >> > >> On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote: > >>> Hi Samuel, and any other

[Mesa-dev] [PATCH 06/23] i965/fs: Print reg and reg_offset separately for ATTR files.

Reading this output was really confusing. reg represents attribute slots; reg_offset is the x/y/z/w component (0..3) within a vec4 slot. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Mesa-dev] [PATCH 09/23] i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.

Previously, we used nir_lower_io with the scalar type_size function, which mapped VERT_ATTRIB_* locations to...some numbers. Then, in fs_visitor::nir_setup_inputs(), we created temporaries indexed by those numbers, and emitted MOVs from the actual ATTR registers to those temporaries. This patch

[Mesa-dev] [PATCH 05/23] nir: Introduce new nir_intrinsic_load_per_vertex_input intrinsics.

Geometry and tessellation shaders process multiple vertices; their inputs are arrays indexed by the vertex number. While GLSL makes this look like a normal array, it can be very different behind the scenes. On Intel hardware, all inputs for a particular vertex are stored together - as if they

[Mesa-dev] [PATCH 16/23] i965: Make emit_urb_writes() only set EOT for the VS.

The GS will emit a bunch of vertices, and we don't want to do an EOT prematurely. We'll emit GS_OPCODE_THREAD_END when we want to terminate the thread. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +- 1 file changed, 1 insertion(+),

[Mesa-dev] [PATCH 13/23] i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.

In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth

[Mesa-dev] [PATCH 04/23] nir/lower_io: Make get_io_offset take a nir_deref, not a nir_deref_var.

We have a nir_deref_var, but it doesn't actually need that. Upcoming patches will make us call get_io_offset further down the dereference chain, so handling an arbitrary dereference will be nice. Signed-off-by: Kenneth Graunke --- src/glsl/nir/nir_lower_io.c | 8

[Mesa-dev] [PATCH 01/23] nir: Allow nir_lower_io() to only lower one type of variable.

We may want to use different type_size functions for (e.g.) inputs vs. uniforms. Passing in -1 for mode ignores this, handling all modes as before. Signed-off-by: Kenneth Graunke --- src/glsl/nir/nir.h | 1 + src/glsl/nir/nir_lower_io.c | 21

[Mesa-dev] [PATCH 00/23] i965 SIMD8 GS and NIR input refactors

Hello, Here's a respin of my SIMD8 VS input refactors, new GS input refactors, and finally the long-awaited SIMD8 GS support. Patches 1-10 are input refactoring. Patches 11-23 are SIMD8 GS support. To try out SIMD8 GS, set the INTEL_SCALAR_GS=1 environment variable. Note that the feature

[Mesa-dev] [PATCH 22/23] i965: Add scalar GS input lowering code.

We really ought to compute the VUE map at link time and stash it, rather than recomputing it here, but with the mess of program structures I wasn't sure where to put it. We can improve that later. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_nir.c |

[Mesa-dev] [PATCH 12/23] i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.

In the vec4 backend, we have a vec4_instruction::urb_write_flags field. There are many kinds of flags for SIMD4x2 messages. However, there are really only two (per-slot offset, use channel masks) for SIMD8 messages. Rather than adding a boolean flag for per-slot offsets (polluting all

[Mesa-dev] [PATCH 07/23] i965/vs: Unify URB entry size/read length calculations between backends.

Both the vec4 and scalar VS backends had virtually identical URB entry size and read length calculations. We can move those up a level to backend-agnostic code and reuse it for both. Unfortunately, the backends need to know nr_attributes to compute first_non_payload_grf, so I had to store that

[Mesa-dev] [PATCH 19/23] i965: Add a fs_visitor constructor that takes a brw_gs_compile.

Unlike the vs/wm structs, brw_gs_compile is actually useful: it contains the input VUE map and information about the control data headers. Passing this in allows us to share that code in brw_gs.c, and calculate them before deciding on vec4 vs. scalar mode, as it's independent of that choice.

[Mesa-dev] [PATCH 20/23] i965: Implement nir_intrinsic_load_primitive.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 2997e51..774ce86 100644 ---

[Mesa-dev] [PATCH 03/23] nir/lower_io: Switch on shader stage for inputs in load_op().

The next commit will introduce a new intrinsic for shaders which process multiple vertices (i.e. geometry, tessellation). This plumbing allows us to generate different intrinsics based on the shader stage. Signed-off-by: Kenneth Graunke --- src/glsl/nir/nir_lower_io.c |

[Mesa-dev] [PATCH 1/3] gallium/radeon: Use call_once() when initailizing LLVM targets

CC: "10.6 11.0" --- src/gallium/drivers/radeon/radeon_llvm_emit.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c

[Mesa-dev] [PATCH 2/3] gallivm: Allow drivers and state trackers to initialize gallivm LLVM targets v2

Drivers and state trackers that use LLVM for generating code, must register the targets they use with LLVM's global TargetRegistry. The TargetRegistry is not thread-safe, so all targets must be added to the registry before it can be queried for target information. When drivers and state trackers

Re: [Mesa-dev] [PATCH 2/2] dri/common: drop loading /etc/drirc

On Mon, Sep 28, 2015 at 5:56 AM, Michel Dänzer wrote: > On 03.09.2015 07:26, Marek Olšák wrote: >> On Wed, Sep 2, 2015 at 10:56 PM, Kenneth Graunke >> wrote: >>> On Wednesday, September 02, 2015 02:26:56 AM Marek Olšák wrote: From: Marek Olšák

[Mesa-dev] [RFC] pipe-loader: abstract GALLIUM_STATIC_TARGETS behind pipe_loader API

From: Rob Clark Not actually working yet, ie. doesn't even compile yet, but an idea. Initial motivation was for drm_gralloc/pipe, which is essentially a sort of mini state-tracker, that needs to be able to share pipe_screen with libGL linked into the same process (to

[Mesa-dev] [RFC] Vendor-neutral dispatch library for OpenGL

I'm working on libglvnd, a vendor-neutral dispatch library for OpenGL, and I wanted to see if anyone had any comments or suggestions about it. Right now, I'm trying to get the GLX interface wrapped up, but I'd like to get some feedback from the Mesa community before I'd be confidant in calling

[Mesa-dev] [PATCH 3/3] radeon/llvm: Initialize gallivm targets when initializing the AMDGPU target v2

This fixes a race condition in the glx-multithreaded-shader-compile test. v2: - Replace gallivm_init_llvm_{begin,end}() with gallivm_init_llvm_targets(). CC: "10.6 11.0" --- src/gallium/drivers/radeon/radeon_llvm_emit.c | 2 ++ 1 file changed, 2

[Mesa-dev] [PATCH 11/18] i830: Fix culling with user fbos on gen2

From: Ville Syrjälä Flip the cull bits when rendering to a user fbo on gen2. This was already done on gen3 (since before git history starts) but was missing from the gen2 code. Fixes rendering of the driver+kart model in supertuxkart kart selection screen.

[Mesa-dev] [PATCH 02/18] t_dd_dmatmp: Allow flat shaded polygons with tri fans

From: Ville Syrjälä We can allow rendering flat shaded polygons using tri fans if we check the provoking vertex convention. v2 (idr): Remove _EXT suffixes from GL_FIRST_VERTEX_CONVENTION. Signed-off-by: Ville Syrjälä Reviewed-by:

[Mesa-dev] [PATCH 06/18] i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLine

From: Ville Syrjälä _tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of what we want so use them. Signed-off-by: Ville Syrjälä Reviewed-by: Ian Romanick ---

[Mesa-dev] [PATCH 16/18] t_dd_dmatmp: Require HAVE_POINTS

From: Ian Romanick Two drivers use this file, and both support points. The i915 driver gained support for points only recently. Signed-off-by: Ian Romanick --- src/mesa/tnl_dd/t_dd_dmatmp.h | 34 +++--- 1 file

[Mesa-dev] [PATCH 01/18] t_dd_dmatmp: Replace fprintf with unreachable

From: Ian Romanick From http://lists.freedesktop.org/archives/mesa-dev/2015-May/084883.html: "There are no real error cases here, just dead code. validate_render() is supposed to make sure we never call these functions if the code can't actually render the

[Mesa-dev] [PATCH 12/18] mesa/i965: Refactor brw_is_front_buffer_{drawing, reading} to common code

From: Ian Romanick There are multiple similar implementations of these functions, and a later patch was going to add another. Signed-off-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_context.c | 15 ---

[Mesa-dev] [PATCH 18/18] t_dd_dmatmp: Use 'X &= ~N' instead of 'X -= X & N'

From: Ian Romanick Signed-off-by: Ian Romanick Suggested-by: Brian Paul --- src/mesa/tnl_dd/t_dd_dmatmp.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h

[Mesa-dev] [PATCH 10/18] i915: Adjust line size limits

From: Ville Syrjälä The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits to 1.0-7.0. The old limits seems to be from the era when i915 and i965 were sharing this code. Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as those are

[Mesa-dev] [PATCH 07/18] i915: Use c99 initializers for primitive arrays

From: Ville Syrjälä Using c99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ville Syrjälä Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i915/intel_render.c | 60

[Mesa-dev] [PATCH 04/18] t_dd_dmatmp: Check provoking vertex convention when rendering quads

From: Ville Syrjälä When drawing quads using triangles we need to be careful to make the provoking vertices match when flat shading. v2: Major rebase on top of Ian other t_dd_dmatmp.h work. Signed-off-by: Ville Syrjälä

[Mesa-dev] [PATCH 17/18] t_dd_dmatmp: Use C99 mixed code and declarations

From: Ian Romanick While this file lives in src/mesa/tnl_dd, it is built only in drivers that live in src/mesa/drivers/dri. We don't generally allow C99-isms in common code, but we have allowed C99-isms in src/mesa/drivers/dri for quite some time. Signed-off-by: Ian

[Mesa-dev] [PATCH 09/18] i915: Enable intel_render path for points

From: Ville Syrjälä The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so

[Mesa-dev] [PATCH 13/18] i915: Drop broken front_buffer_reading/drawing optimization

From: Ville Syrjälä Bring the following commit over to i915: commit ec542d74578bbef6b55125dd6aba1dc7f5079e65 Author: Eric Anholt Date: Mon Mar 3 10:43:10 2014 -0800 i965: Drop broken front_buffer_reading/drawing optimization. Not sure

[Mesa-dev] [PATCH 05/18] i915: Handle provoking vertex in intelFastRenderClippedPoly()

From: Ville Syrjälä intelFastRenderClippedPoly() renders the polygon using triangles. For polygons the provoking vertex is always the first one, and currently this function assumes that the provoking vertex for triangles is the last one. In case the user changed

[Mesa-dev] [PATCH 15/18] radeon: Drop broken front_buffer_reading/drawing optimization

From: Ian Romanick Signed-off-by: Ian Romanick --- src/mesa/drivers/dri/radeon/radeon_common.c| 37 -- .../drivers/dri/radeon/radeon_common_context.c | 10 +++--- .../drivers/dri/radeon/radeon_common_context.h

[Mesa-dev] [PATCH 08/18] i915: Use COPY_DWORDS for points

From: Ville Syrjälä The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so

[Mesa-dev] [PATCH 14/18] radeon: Use _mesa_is_front_buffer_drawing

From: Ian Romanick Signed-off-by: Ian Romanick --- src/mesa/drivers/dri/radeon/radeon_common.c | 21 - src/mesa/drivers/dri/radeon/radeon_common.h | 1 - src/mesa/drivers/dri/radeon/radeon_screen.h | 1 -

[Mesa-dev] [PATCH 03/18] t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri strips

From: Ville Syrjälä When rendering quad strips via tri strips we can't get the provoking vertex right, so disallow flat shading. v2: Major rebase on top of Ian's other t_dd_dmatmp.h work. Signed-off-by: Ville Syrjälä Signed-off-by:

[Mesa-dev] [PATCH 00/18] More t_dd_dmatmp janitor work and misc other

This is the last of the t_dd_dmatmp janitor work that I plan to do. The first patch is a change suggested by Ville while I was reviewing some of his patches to t_dd_dmatmp earlier this year. I re-found Ville's patches while I was searching my inbox for reviews to my previous t_dd_dmatmp series.

Re: [Mesa-dev] [PATCH v2] mesa: use strtok_s for strtok_r on windows

On 09/30/2015 11:38 AM, Tapani Pälli wrote: https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx v2: use _WIN32 instead of _MSC_VER (Brian Paul) Signed-off-by: Tapani Pälli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183 --- src/mesa/main/imports.h | 3

[Mesa-dev] [PATCH 2/4] i965: Define BRW_MAX_SSBO

Instead of using hard-coded values. --- src/mesa/drivers/dri/i965/brw_context.c | 14 +++--- src/mesa/drivers/dri/i965/brw_context.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c

Re: [Mesa-dev] [PATCH 6/7] i965: Only resolve the textures if a _NEW_STATE state change is flagged

Chris Wilson writes: > Only walk through the set of enabled TextureUnits looking for a texture > that needs to be resolved if the context state flags a new texture. > > Note that this will miss if the client is rendering into a texture that > it is reading from, though

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, 2015-09-30 at 11:54 +0300, Francisco Jerez wrote: > Iago Toral writes: > > > On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote: > >> Ilia Mirkin writes: > >> > >> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: >

[Mesa-dev] [PATCH 0/4] Reserve binding table space for SSBOs

This fixes a bug that Curro pointed out: we only allocate entries for UBOs at the moment. This a problem when a shader defines more than 12 combined UBO and SSBO surfaces. This is done with patch 3. patch 4 simply adds an assertion to make sure that we never try to exceed that limit for some

[Mesa-dev] [PATCH 3/4] i965: Reserve binding table space for SSBO surfaces

These share the space with UBO surfaces but we need to make sure we allocate enough space for both sets (12 of each) --- src/mesa/drivers/dri/i965/brw_context.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h

[Mesa-dev] [PATCH 1/4] i965: Define BRW_MAX_UBO

Instead of using hard-coded values. --- src/mesa/drivers/dri/i965/brw_context.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 5 - 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index

[Mesa-dev] [PATCH 4/4] i965: Assert on the number of combined UBO and SSBO binding table entries

In theory we can't break this assertion since the compiler frontend checks that we don't exceed any of the individual limits, but it does not hurt to be extra safe. --- src/mesa/drivers/dri/i965/brw_context.h | 3 +++ src/mesa/drivers/dri/i965/brw_shader.cpp | 1 + 2 files changed, 4

[Mesa-dev] [PATCH] mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()

Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect format specifier that operates on GLintptr indirect within the function _mesa_DispatchComputeIndirect(). This patch mitigates the introduced GCC warning: src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':

Re: [Mesa-dev] [PATCH 7/7] i965: Remove redundant test for NULL intel_texture_object

Ian Romanick writes: > On 09/09/2015 06:39 AM, Chris Wilson wrote: >> Having checked whether the base class (gl_texture_object) is NULL, we >> know that intel_texture_object itself cannot be NULL. >> >> Signed-off-by: Chris Wilson >> Cc: Jordan

Re: [Mesa-dev] SSBO's in UniformBlocks list?

Iago Toral writes: > On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote: >> Ilia Mirkin writes: >> >> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote: >> >> Hi ilia, >> >> >> >> On Tue, 2015-09-29 at 03:53 -0400, Ilia

Re: [Mesa-dev] Question: st/mesa and context-shareable shaders

On Mon, Sep 28, 2015 at 4:39 PM, Roland Scheidegger wrote: > > In short, for simplicity, only things were sharable which were really > required to be shared (pretty much just actual resources - and yes that > doesn't work too well for GL neither as you can't share sampler/rt >

Re: [Mesa-dev] [PATCH] configure.ac: handle llvm built with cmake in one shared library

On 29 September 2015 at 23:53, Dave Airlie wrote: > On 30 September 2015 at 01:34, Laurent Carlier wrote: >> llvm can be built with cmake in a libray with the name libLLVM.so.$version >> Tested with both llvm-3.7.0 and llvm-3.8.0svn >> >> v2: check and

Re: [Mesa-dev] [PATCH] radeonsi: don't set DATA_FORMAT if ADD_TID_ENABLE is set on VI

On Wed, Sep 30, 2015 at 5:51 AM, Michel Dänzer wrote: > On 29.09.2015 23:54, Marek Olšák wrote: >> From: Marek Olšák >> >> This can cause incorrect address calculations and hangs. >> >> Cc: mesa-sta...@lists.freedesktop.org > > IIRC without "10.6 11.0"

Re: [Mesa-dev] [PATCH] mesa: use strtok_s for strtok_r on windows

On 09/30/2015 12:19 AM, Tapani Pälli wrote: https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx Signed-off-by: Tapani Pälli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183 --- src/mesa/main/imports.h | 3 +++ 1 file changed, 3 insertions(+) diff

Re: [Mesa-dev] [PATCH 06/23] mesa: remove Driver.ResizeBuffers

On 09/27/2015 04:20 PM, Marek Olšák wrote: From: Marek Olšák Nothing overrides it. --- src/mesa/drivers/common/driverfuncs.c | 1 - src/mesa/drivers/dri/common/dri_util.c | 3 ++- src/mesa/main/dd.h | 7 --- 3 files changed, 2 insertions(+), 9

Re: [Mesa-dev] [PATCH] mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()

2015-09-30 19:15 GMT+08:00 Rhys Kidd : > Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect > format specifier that operates on GLintptr indirect within the function > _mesa_DispatchComputeIndirect(). > > This patch mitigates the introduced GCC warning: > >

[Mesa-dev] [PATCH v2] mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()

Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect format specifier that operates on GLintptr indirect within the function _mesa_DispatchComputeIndirect(). This patch mitigates the introduced GCC warning: src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':

[Mesa-dev] [PATCH 6/7] mesa: clean up #includes in sampler.cpp

--- src/mesa/program/sampler.cpp | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/mesa/program/sampler.cpp b/src/mesa/program/sampler.cpp index ea3024d..b1168fd 100644 --- a/src/mesa/program/sampler.cpp +++ b/src/mesa/program/sampler.cpp @@ -23,13 +23,12 @@ *

[Mesa-dev] [PATCH 3/7] mesa: clean up #includes in uniform_query.cpp

--- src/mesa/main/uniform_query.cpp | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index 0bee594..33c959d 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main/uniform_query.cpp @@

[Mesa-dev] [PATCH 2/7] mesa: clean up #includes in pipelineobj.c

--- src/mesa/main/pipelineobj.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index c2e1d29..51ee10f 100644 --- a/src/mesa/main/pipelineobj.c +++ b/src/mesa/main/pipelineobj.c @@ -31,6 +31,7 @@ *

[Mesa-dev] [PATCH 1/7] mesa: clean up #includes in ff_fragment_shader.cpp

Get rid of "../glsl/" paths. Sort alphabetically. --- src/mesa/main/ff_fragment_shader.cpp | 22 ++ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/mesa/main/ff_fragment_shader.cpp b/src/mesa/main/ff_fragment_shader.cpp index c682892..c0030bc 100644 ---

[Mesa-dev] [Bug 92122] [bisected] Regression with Assault Android Cactus

https://bugs.freedesktop.org/show_bug.cgi?id=92122 Dieter Nützel changed: What|Removed |Added CC|

[Mesa-dev] [Bug 92173] [regression, bisected] commit 266d05a broke WebGL-Water Caustics on NI/Turks (6670)

https://bugs.freedesktop.org/show_bug.cgi?id=92173 Dieter Nützel changed: What|Removed |Added Status|NEW |RESOLVED

Re: [Mesa-dev] [PATCH 2/2] dri/common: drop loading /etc/drirc

On Thu, Oct 01, 2015 at 01:46:10AM +0200, Marek Olšák wrote: > On Thu, Oct 1, 2015 at 1:21 AM, Marcin Ślusarz > wrote: > > On Thu, Oct 01, 2015 at 12:57:40AM +0200, Marek Olšák wrote: > >> On Thu, Oct 1, 2015 at 12:53 AM, Marcin Ślusarz > >>

[Mesa-dev] [Bug 92122] [bisected] Regression with Assault Android Cactus

https://bugs.freedesktop.org/show_bug.cgi?id=92122 --- Comment #8 from Dieter Nützel --- Please commit soon! ;-) -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list

[Mesa-dev] [PATCH 07.2/18] radeon: Use C99 initializers for primitive arrays

From: Ian Romanick Using C99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ian Romanick Suggested-by: Matt Turner --- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 40

Re: [Mesa-dev] [PATCH 3/3] radeon/llvm: Initialize gallivm targets when initializing the AMDGPU target v2

For the series: Reviewed-by: Marek Olšák Marek On Wed, Sep 30, 2015 at 8:59 PM, Tom Stellard wrote: > This fixes a race condition in the glx-multithreaded-shader-compile > test. > > v2: > - Replace gallivm_init_llvm_{begin,end}() with

Re: [Mesa-dev] [PATCH 09/23] i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.

On Wednesday, September 30, 2015 12:58:13 AM Kenneth Graunke wrote: [snip] > diff --git a/src/mesa/drivers/dri/i965/brw_nir.c > b/src/mesa/drivers/dri/i965/brw_nir.c > index 64763e0..56bd3d3 100644 > --- a/src/mesa/drivers/dri/i965/brw_nir.c > +++ b/src/mesa/drivers/dri/i965/brw_nir.c > @@ -33,15

Re: [Mesa-dev] [PATCH 2/2] st/mesa: try PIPE_BIND_RENDER_TARGET when choosing float texture formats

On Tue, Sep 29, 2015 at 7:50 PM, Brian Paul wrote: > > I was actually thinking of expanding this change to cover _all_ color formats > but wanted to take a small step first. What do you think? > I have some patches in this area sitting around here:

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