Re: [Mesa-dev] [PATCH 11/11] i965: Use nir_lower_tex for texture coordinate lowering

On Mon, 2015-11-16 at 07:55 -0800, Jason Ekstrand wrote: > On Mon, Nov 16, 2015 at 6:27 AM, Iago Toral wrote: > > On Mon, 2015-11-16 at 11:33 +0100, Iago Toral wrote: > >> On Wed, 2015-11-11 at 17:26 -0800, Jason Ekstrand wrote: > >> > Previously, we had a rescale_texcoords helper in the FS backen

Re: [Mesa-dev] [PATCH 07/11] i965: Move postprocess_nir to codegen time

Hi Jason, On Mon, 2015-11-16 at 07:50 -0800, Jason Ekstrand wrote: > > On Nov 16, 2015 2:01 AM, "Iago Toral" wrote: > > > > On Fri, 2015-11-13 at 07:34 -0800, Jason Ekstrand wrote: > > > > > > On Nov 13, 2015 5:53 AM, "Iago Toral" wrote: > > > > > > > > On Wed, 2015-11-11 at 17:26 -0800, Jason

[Mesa-dev] [PATCH 2/6] glsl/nir: initialize precision field in glsl_struct_field constructor

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/nir/glsl_types.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glsl/nir/glsl_types.h b/src/glsl/nir/glsl_types.h index 2d44059..d8a999a 100644 --- a/src/glsl/nir/glsl_types.h +++ b/src/glsl/nir/glsl_types.h @@ -851,

[Mesa-dev] [PATCH 4/6] glsl: copy each field's precision information when generating varying variables

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/builtin_variables.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp index b927d50..fc7a3c3 100644 --- a/src/glsl/builtin_variables.cpp +++ b/src/glsl/builtin_variables.cpp @

[Mesa-dev] [PATCH 3/6] glsl: initialize data.precision value in ir_variable constructor

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/ir.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp index 8933b23..8b5ba71 100644 --- a/src/glsl/ir.cpp +++ b/src/glsl/ir.cpp @@ -1676,6 +1676,7 @@ ir_variable::ir_variable(const struct glsl_type *type,

[Mesa-dev] [PATCH 6/6] glsl: copy each field's precision information in glsl_types's structure constructor

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/nir/glsl_types.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/glsl_types.cpp b/src/glsl/nir/glsl_types.cpp index 975b815..9cc3715 100644 --- a/src/glsl/nir/glsl_types.cpp +++ b/src/glsl/nir/glsl_types.cpp @@ -129,6 +129,7

[Mesa-dev] [PATCH 1/6] nir: reduce memory footprint of glsl_struct_field's precision

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/nir/glsl_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/nir/glsl_types.h b/src/glsl/nir/glsl_types.h index d841a32..2d44059 100644 --- a/src/glsl/nir/glsl_types.h +++ b/src/glsl/nir/glsl_types.h @@ -837,7

[Mesa-dev] [PATCH 5/6] glsl: copy each field's precision information from the old gl_PerVertex interface block

Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/ast_to_hir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index f529243..97554cb 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -6603,6 +6603,8 @@ ast_interfac

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On 17/11/15 07:38, Tapani Pälli wrote: > > > On 11/16/2015 03:12 PM, Samuel Iglesias Gonsálvez wrote: >> >> >> On 13/11/15 16:55, Tapani Pälli wrote: >>> On 11/13/2015 03:40 PM, Samuel Iglesias Gonsálvez wrote: On 13/11/15 11:32, Tapani Pälli wrote: > Patch adds additional mask fo

Re: [Mesa-dev] [PATCH 14/36] glsl ubo/ssbo: Use enum to track current buffer access type

On Mon, 2015-11-16 at 16:50 -0800, Jordan Justen wrote: > On 2015-11-16 03:06:37, Iago Toral wrote: > > On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > > > Signed-off-by: Jordan Justen > > > Cc: Samuel Iglesias Gonsalvez > > > Cc: Iago Toral Quiroga > > > --- > > > src/glsl/lower_ubo_

Re: [Mesa-dev] [PATCH 1/2] i965: Add INTEL_DEBUG=tcs, tes and hs, ds flags for tessellation shaders.

Both patches are Reviewed-by: Tapani Pälli On 11/17/2015 02:36 AM, Kenneth Graunke wrote: Even though both tessellation shader stages must be used together, I still think it makes sense to add separate debug flags for each stage. It makes it possible to read the TCS/HS, rule out problems, then

Re: [Mesa-dev] [PATCH 16/36] glsl ubo/ssbo: Add lower_buffer_access class

On Mon, 2015-11-16 at 17:52 -0800, Jordan Justen wrote: > On 2015-11-16 04:27:55, Iago Toral wrote: > > On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > > > This class has code that will be shared by lower_ubo_reference and > > > lower_shared_reference. (lower_shared_reference will be used

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On 11/16/2015 08:55 AM, Tapani Pälli wrote: On 11/13/2015 07:18 PM, Fredrik Höglund wrote: On Friday 13 November 2015, Tapani Pälli wrote: Patch adds additional mask for tracking which vertex buffer bindings are set. This array can be directly compared to which vertex arrays are enabled and

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On 11/16/2015 03:12 PM, Samuel Iglesias Gonsálvez wrote: On 13/11/15 16:55, Tapani Pälli wrote: On 11/13/2015 03:40 PM, Samuel Iglesias Gonsálvez wrote: On 13/11/15 11:32, Tapani Pälli wrote: Patch adds additional mask for tracking which vertex buffer bindings are set. This array can be d

Re: [Mesa-dev] [PATCH 1/2] nir: Add support for gl_HelperInvocation system value.

Reviewed-by: Tapani Pälli On 11/14/2015 04:05 AM, Matt Turner wrote: --- src/glsl/nir/nir.c| 4 src/glsl/nir/nir_intrinsics.h | 1 + 2 files changed, 5 insertions(+) diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c index bb7a5fa..974438b 100644 --- a/src/glsl/nir/nir.c

Re: [Mesa-dev] [PATCH] i965: Add assertion for src_stencil payload size

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965: Add assertion for src_stencil payload size

This helps address a coverity warning and prevents future questions about this code. Reported-by: Coverity (via Ilia) Cc: Matt Turner Cc: Ilia Mirkin Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/

Re: [Mesa-dev] [PATCH 16/36] glsl ubo/ssbo: Add lower_buffer_access class

On 2015-11-16 04:27:55, Iago Toral wrote: > On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > > This class has code that will be shared by lower_ubo_reference and > > lower_shared_reference. (lower_shared_reference will be used to > > support compute shader shared variables.) > > > > Signe

Re: [Mesa-dev] [PATCH 29/36] glsl: Allow atomic functions to be used with shared variables

Reviewed-by: Timothy Arceri ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 14/36] glsl ubo/ssbo: Use enum to track current buffer access type

On 2015-11-16 03:06:37, Iago Toral wrote: > On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > > Signed-off-by: Jordan Justen > > Cc: Samuel Iglesias Gonsalvez > > Cc: Iago Toral Quiroga > > --- > > src/glsl/lower_ubo_reference.cpp | 26 +- > > 1 file changed, 21

Re: [Mesa-dev] [PATCH 1/2] mesa: Add KBL PCI IDs and platform information.

On Mon, Nov 16, 2015 at 4:24 PM, Sarah Sharp wrote: > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken > directly from the Linux kernel patches, which are under review: > > http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html > http://cgit.freedesktop.org/~vivij

[Mesa-dev] [PATCH] i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_defines.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 0b8de63..ade3ede 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b

[Mesa-dev] [PATCH 1/2] i965: Add INTEL_DEBUG=tcs, tes and hs, ds flags for tessellation shaders.

Even though both tessellation shader stages must be used together, I still think it makes sense to add separate debug flags for each stage. It makes it possible to read the TCS/HS, rule out problems, then read the TES/DS separately, without sifting through as much printed text. I decided to add bo

[Mesa-dev] [PATCH 2/2] i965: Add INTEL_DEBUG=shader_time support for tessellation shaders.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_program.c | 12 2 files changed, 14 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 4b2db61..8d6bc19

[Mesa-dev] [PATCH 2/2] intel/kbl: Add Kabylake PCI ids

From: Rodrigo Vivi Also, following kernel definition Kabylake is skylake. Signed-off-by: Rodrigo Vivi Signed-off-by: Sarah Sharp --- intel/intel_chipset.h | 57 ++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/intel/intel_chips

[Mesa-dev] [PATCH 0/2] Mesa and DRM patches for Intel Kabylake platform

Sarah Sharp (1): mesa: Add KBL PCI IDs and platform information. include/pci_ids/i965_pci_ids.h | 22 +++ src/mesa/drivers/dri/i965/brw_device_info.c | 60 + 2 files changed, 82 insertions(+) Rodrigo Vivi (1): intel/kbl: Add Kabylake PCI ids

[Mesa-dev] [PATCH 1/2] mesa: Add KBL PCI IDs and platform information.

Add PCI IDs for the Intel Kabylake platforms. The IDs are taken directly from the Linux kernel patches, which are under review: http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 Please note that if this

Re: [Mesa-dev] [PATCH 1/2] i965: Convert scalar_* flags to a scalar_stage array.

On Monday, November 16, 2015 10:23:22 AM Pohjolainen, Topi wrote: > On Fri, Nov 13, 2015 at 11:29:00AM -0800, Kenneth Graunke wrote: > > On Friday, November 13, 2015 10:06:23 AM Pohjolainen, Topi wrote: > > > On Thu, Nov 12, 2015 at 03:38:51PM -0800, Kenneth Graunke wrote: > > > > I was going to ad

Re: [Mesa-dev] [PATCH 1/5] util/set: don't compare against deleted entries

On Sat, 2015-11-14 at 21:59 -0500, Connor Abbott wrote: > Not sure how this wasn't already caught by valgrind, but it fixes an > issue with the vectorizer. Can you give a more detailed description of the problem that is fixed? I'm assuming its something to do with the key_equals_function having is

Re: [Mesa-dev] [PATCH V2 05/12] glsl: add layout qualifier validation for the shader outside the parser

On Tue, 2015-11-10 at 12:29 +, Emil Velikov wrote: > Hi Tim, > > On 8 November 2015 at 22:34, Timothy Arceri > wrote: > > From: Timothy Arceri > > > > This is in preparation for compile-time constant support, a later > > patch > > will remove the validation from the shader. > > > > The glo

[Mesa-dev] [PATCH] i965/nir: Add hooks for testing nir_shader_clone

This commit adds code for testing nir_shader_clone by running it after each and every optimization pass and throwing away the old shader. Testing nir_shader_clone is hidden behind a new INTEL_CLONE_NIR environment variable. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++-- src/mes

Re: [Mesa-dev] [PATCH v2] i965: Prevent fast clears for MSRTs on SKL

On Mon 16 Nov 2015, Neil Roberts wrote: > There are currently a bunch of formats that behave strangely when > sampling the cleared color from the MCS buffer on SKL. They seem to > mostly be formats that don't have an alpha component, although it's > not all of them, and we haven't yet found anythin

Re: [Mesa-dev] [PATCH 3/7] [v2] i965/skl: skip fast clears for certain surface formats

On Mon 16 Nov 2015, Matt Turner wrote: > On Wed, Nov 11, 2015 at 2:06 PM, Ben Widawsky > wrote: > > Some of the information originally in this commit message is now in the > > patch > > before this. > > > > SKL adds compressible render targets and as a result mutates some of the > > programming f

Re: [Mesa-dev] [PATCH 2/2] i965/fs: Add support for gl_HelperInvocation system value.

On Fri, Nov 13, 2015 at 6:05 PM, Matt Turner wrote: > --- > This code generates > > mov(1) f0<1>UW g1.14<0,1,0>UW > mov(8) g2<1>UD 0xUD > (+f0) sel(8)g3<1>D g2<8,8,1>D -1D > > which I don't love because it uses the

Re: [Mesa-dev] [PATCH 1/2] radeon: fix bgrx8/xrgb8 blits

Reviewed-by: Marek Olšák Marek On Thu, Nov 12, 2015 at 8:00 PM, wrote: > From: Roland Scheidegger > > Since d21320f6258b2e1780a15c1ca718963d8a15ca18 the same txformat table entries > are used for "normal" texturing as well as for blits. However, I forgot to put > in an entry for the bgrx8 (le

Re: [Mesa-dev] [PATCH 2/2] r200: fix bgrx8/xrgb8 blits

Reviewed-by: Marek Olšák Marek On Thu, Nov 12, 2015 at 8:00 PM, wrote: > From: Roland Scheidegger > > Since 779cabfc7d022de8b7b9bc7fdac0caffa8646c51 the same txformat table entries > are used for "normal" texturing as well as for blits. However, I forgot to put > in an entry for the bgrx8 (le

Re: [Mesa-dev] [PATCH 1/2] radeonsi: Rename si_shader::ls_rsrc{1, 2} to si_shader::rsrc{1, 2}

For the series: Reviewed-by: Marek Olšák Marek On Mon, Nov 16, 2015 at 9:03 PM, Tom Stellard wrote: > In the future, these will be used by other shaders types. > > CC: > --- > src/gallium/drivers/radeonsi/si_shader.h| 4 ++-- > src/gallium/drivers/radeonsi/si_state_draw.c| 4 ++--

Re: [Mesa-dev] [Mesa-stable] [PATCH] meta/generate_mipmap: Don't leak the framebuffer object

On Mon, Nov 16, 2015 at 10:32 AM, Ian Romanick wrote: > From: Ian Romanick > > Signed-off-by: Ian Romanick > Cc: "10.6 11.0" > --- > src/mesa/drivers/common/meta_generate_mipmap.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c > b/

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] r200: fix bgrx8/xrgb8 blits

Tested-by: Ian Romanick On 11/12/2015 11:00 AM, srol...@vmware.com wrote: > From: Roland Scheidegger > > Since 779cabfc7d022de8b7b9bc7fdac0caffa8646c51 the same txformat table entries > are used for "normal" texturing as well as for blits. However, I forgot to put > in an entry for the bgrx8 (l

[Mesa-dev] [PATCH 2/2] radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values

The compiler has more information and is able to optimize the bits it sets in these registers. CC: --- src/gallium/drivers/radeonsi/si_compute.c | 37 ++- src/gallium/drivers/radeonsi/si_shader.c | 2 ++ 2 files changed, 9 insertions(+), 30 deletions(-) diff --git

[Mesa-dev] [PATCH 1/2] radeonsi: Rename si_shader::ls_rsrc{1, 2} to si_shader::rsrc{1, 2}

In the future, these will be used by other shaders types. CC: --- src/gallium/drivers/radeonsi/si_shader.h| 4 ++-- src/gallium/drivers/radeonsi/si_state_draw.c| 4 ++-- src/gallium/drivers/radeonsi/si_state_shaders.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff -

Re: [Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

On Mon 16 Nov 2015, Ben Widawsky wrote: > On Fri, Nov 13, 2015 at 12:29:47PM -0800, Chad Versace wrote: > > On Wed 11 Nov 2015, Ben Widawsky wrote: > > > Background: Prior to Skylake and since Ivybridge Intel hardware has had > > > the > > > ability to use a MCS (Multisample Control Surface) as au

Re: [Mesa-dev] [PATCH] r600g: Support TGSI_SEMANTIC_HELPER_INVOCATION

On Mon, Nov 16, 2015 at 6:03 PM, Ilia Mirkin wrote: > On Mon, Nov 16, 2015 at 8:31 AM, Nicolai Hähnle wrote: >> Hi Glenn, >> >> On 14.11.2015 00:11, Glenn Kennard wrote: >>> >>> On Fri, 13 Nov 2015 18:57:28 +0100, Nicolai Hähnle >>> wrote: >>> On 13.11.2015 00:14, Glenn Kennard wrote: >

Re: [Mesa-dev] [PATCH 1/2] i965: Convert scalar_* flags to a scalar_stage array.

On 2015-11-12 15:38:51, Kenneth Graunke wrote: > I was going to add scalar_tcs and scalar_tes flags, and then thought > better of it and decided to convert this to an array. Simpler. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/brw_compiler.h | 3 +-- > src/mes

Re: [Mesa-dev] [PATCH] i965: Set MaxCombinedUniformBlocks properly.

Reviewed-by: Jordan Justen On 2015-11-13 15:05:17, Kenneth Graunke wrote: > Up until now, we've been letting core Mesa initialize it to 36 for us > (which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)). > > With compute and tessellation, we need to increase this. > > Signed-off-by: Ke

Re: [Mesa-dev] [PATCH 2/2] i965: Clean up context constant initialization code.

On 2015-11-12 15:38:52, Kenneth Graunke wrote: > This was getting pretty out of hand, and with compute partially in place > and tessellation on the way, it was only going to get worse. > > This patch makes a "stage exists?" predicate and a "number of stages" > count and uses them to clean up a lot

[Mesa-dev] [PATCH] meta/generate_mipmap: Don't leak the framebuffer object

From: Ian Romanick Signed-off-by: Ian Romanick Cc: "10.6 11.0" --- src/mesa/drivers/common/meta_generate_mipmap.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c b/src/mesa/drivers/common/meta_generate_mipmap.c index ffd71b6..bde170f 100

Re: [Mesa-dev] [PATCH 1/2] glsl: initialize precision when adding per vertex record fields

On Monday, November 16, 2015 08:44:18 AM Tapani Pälli wrote: > Fixes issues with tessellation builtin variables since precision was > introduced to IR with commit f84bc57d7dc02fceb805803131426c791eadeff9. > > Signed-off-by: Tapani Pälli > --- > src/glsl/builtin_variables.cpp | 1 + > 1 file chan

Re: [Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

On Fri, Nov 13, 2015 at 12:29:47PM -0800, Chad Versace wrote: > On Wed 11 Nov 2015, Ben Widawsky wrote: > > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > > ability to use a MCS (Multisample Control Surface) as auxiliary data in > > "compression" operations on the sur

Re: [Mesa-dev] [PATCH 3/7] [v2] i965/skl: skip fast clears for certain surface formats

On Wed, Nov 11, 2015 at 2:06 PM, Ben Widawsky wrote: > Some of the information originally in this commit message is now in the patch > before this. > > SKL adds compressible render targets and as a result mutates some of the > programming for fast clears and resolves. There is a new internal surfa

Re: [Mesa-dev] [PATCH 3/7] [v2] i965/skl: skip fast clears for certain surface formats

On Fri, Nov 13, 2015 at 12:22:47PM -0800, Chad Versace wrote: > On Wed 11 Nov 2015, Ben Widawsky wrote: > > Some of the information originally in this commit message is now in the > > patch > > before this. > > > > SKL adds compressible render targets and as a result mutates some of the > > progr

Re: [Mesa-dev] [PATCH] r600g: Support TGSI_SEMANTIC_HELPER_INVOCATION

On Mon, Nov 16, 2015 at 8:31 AM, Nicolai Hähnle wrote: > Hi Glenn, > > On 14.11.2015 00:11, Glenn Kennard wrote: >> >> On Fri, 13 Nov 2015 18:57:28 +0100, Nicolai Hähnle >> wrote: >> >>> On 13.11.2015 00:14, Glenn Kennard wrote: Signed-off-by: Glenn Kennard --- Maybe there is

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 16/11/15 17:34, Ilia Mirkin wrote: > On Mon, Nov 16, 2015 at 11:29 AM, Samuel Iglesias Gonsálvez > wrote: >> >> >> On 16/11/15 13:07, Tapani Pälli wrote: >>> >>> On 11/16/2015 01:35 PM, Tapani Pälli wrote: On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: > Hello Ili

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On Mon, Nov 16, 2015 at 11:42 AM, Samuel Iglesias Gonsálvez wrote: > > > On 16/11/15 17:34, Ilia Mirkin wrote: >> On Mon, Nov 16, 2015 at 11:29 AM, Samuel Iglesias Gonsálvez >> wrote: >>> >>> >>> On 16/11/15 13:07, Tapani Pälli wrote: On 11/16/2015 01:35 PM, Tapani Pälli wrote: > >>

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On Mon, Nov 16, 2015 at 11:29 AM, Samuel Iglesias Gonsálvez wrote: > > > On 16/11/15 13:07, Tapani Pälli wrote: >> >> On 11/16/2015 01:35 PM, Tapani Pälli wrote: >>> >>> >>> On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: Hello Ilia, Tapani: I have reproduced the issue with

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 16/11/15 13:07, Tapani Pälli wrote: > > On 11/16/2015 01:35 PM, Tapani Pälli wrote: >> >> >> On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: >>> Hello Ilia, Tapani: >>> >>> I have reproduced the issue with a piglit test but not with the trace >>> uploaded in the bug report :-( >>> >>

Re: [Mesa-dev] [PATCH v3 07/14] glsl: move stream layout max validation

On 14/11/15 14:58, Timothy Arceri wrote: > On Sun, 2015-11-15 at 00:42 +1100, Timothy Arceri wrote: >> From: Timothy Arceri >> >> This validation is moved later so we can validate the >> max value when compile time constant support is added in a >> later patch. >> --- >> src/glsl/ast_to_hir.cpp

Re: [Mesa-dev] [PATCH 5/5] i965/nir: use vectorization for non-scalar stages

On Sat, Nov 14, 2015 at 6:59 PM, Connor Abbott wrote: > Shader-db results on bdw with INTEL_DEBUG=vec4: > > total instructions in shared programs: 1634044 -> 1612936 (-1.29%) > instructions in affected programs: 802502 -> 781394 (-2.63%) > helped: 5036 > HURT: 1442 > > total cycles in shared progr

Re: [Mesa-dev] [PATCH 11/11] i965: Use nir_lower_tex for texture coordinate lowering

On Mon, Nov 16, 2015 at 6:27 AM, Iago Toral wrote: > On Mon, 2015-11-16 at 11:33 +0100, Iago Toral wrote: >> On Wed, 2015-11-11 at 17:26 -0800, Jason Ekstrand wrote: >> > Previously, we had a rescale_texcoords helper in the FS backend for >> > handling rescaling of texture coordinates. Now that w

Re: [Mesa-dev] [PATCH 32/36] glsl: Translate atomic intrinsic functions on shared variables

hOn Sat, 2015-11-14 at 13:44 -0800, Jordan Justen wrote: > When an intrinsic atomic operation is used on a shared variable, we > translate it to a new 'share variable' specific intrinsic function > call. > > For example, add call to __intrinsic_atomic_add when used on a shared > variable will be t

Re: [Mesa-dev] [PATCH 00/11] i965/nir: Do texture rectangle lowering in NIR

On Sat, Nov 14, 2015 at 1:00 PM, Jason Ekstrand wrote: > On Sat, Nov 14, 2015 at 9:44 AM, Rob Clark wrote: >> On Sat, Nov 14, 2015 at 12:30 PM, Jason Ekstrand >> wrote: >>> On Sat, Nov 14, 2015 at 8:58 AM, Rob Clark wrote: On Sat, Nov 14, 2015 at 11:01 AM, Jason Ekstrand wrote: >>>

Re: [Mesa-dev] [PATCH 32/36] glsl: Translate atomic intrinsic functions on shared variables

On Sat, 2015-11-14 at 13:44 -0800, Jordan Justen wrote: > When an intrinsic atomic operation is used on a shared variable, we > translate it to a new 'share variable' specific intrinsic function > call. > > For example, add call to __intrinsic_atomic_add when used on a shared > variable will be tr

Re: [Mesa-dev] [PATCH 30/36] glsl: Replace atomic_ssbo and ssbo_atomic with atomic

Reviewed-by: Iago Toral Quiroga On Sat, 2015-11-14 at 13:44 -0800, Jordan Justen wrote: > The atomic functions can also be used with shared variables in compute > shaders. > > When lowering the intrinsic in lower_ubo_reference, we still create an > SSBO specific intrinsic since SSBO accesses can

Re: [Mesa-dev] [PATCH 31/36] glsl: Check for SSBO variable in SSBO atomic lowering

On Sat, 2015-11-14 at 13:44 -0800, Jordan Justen wrote: > When an atomic function is called, we need to check to see if it is > for an SSBO variable before lowering it to the SSBO specific intrinsic > function. > > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias Gonsalvez > Cc: Iago Toral Qui

Re: [Mesa-dev] llvm TGSI backend (WIP) questions

Hi, On 13-11-15 19:51, Tom Stellard wrote: On Fri, Nov 13, 2015 at 02:46:52PM +0100, Hans de Goede wrote: Hi All, So as discussed I've started working on a TGSI backend for llvm to use as a way to get compute going on nouveau (and other gpu-s). I'm still learning all the ins and outs of llvm

Re: [Mesa-dev] [PATCH 11/11] i965: Use nir_lower_tex for texture coordinate lowering

On Mon, 2015-11-16 at 11:33 +0100, Iago Toral wrote: > On Wed, 2015-11-11 at 17:26 -0800, Jason Ekstrand wrote: > > Previously, we had a rescale_texcoords helper in the FS backend for > > handling rescaling of texture coordinates. Now that we can do variants in > > NIR, we can use nir_lower_tex to

Re: [Mesa-dev] [PATCH] r600g: Support TGSI_SEMANTIC_HELPER_INVOCATION

Hi Glenn, On 14.11.2015 00:11, Glenn Kennard wrote: On Fri, 13 Nov 2015 18:57:28 +0100, Nicolai Hähnle wrote: On 13.11.2015 00:14, Glenn Kennard wrote: Signed-off-by: Glenn Kennard --- Maybe there is a better way to check if a thread is a helper invocation? Is ctx->face_gpr guaranteed to

[Mesa-dev] [Bug 92706] glBlitFramebuffer refuses to blit RGBA to RGB with MSAA

https://bugs.freedesktop.org/show_bug.cgi?id=92706 --- Comment #6 from Neil Roberts --- (In reply to EoD from comment #5) I think we would need some of the nouveau and radeon people to test the Piglit test on their drivers with the patch in order to ensure that it also works there before landing

Re: [Mesa-dev] [PATCH] mesa: error out in indirect draw when vertex bindings mismatch

On 13/11/15 16:55, Tapani Pälli wrote: > On 11/13/2015 03:40 PM, Samuel Iglesias Gonsálvez wrote: >> >> On 13/11/15 11:32, Tapani Pälli wrote: >>> Patch adds additional mask for tracking which vertex buffer bindings >>> are set. This array can be directly compared to which vertex arrays >>> are e

[Mesa-dev] [PATCH v2] i965: Prevent fast clears for MSRTs on SKL

There are currently a bunch of formats that behave strangely when sampling the cleared color from the MCS buffer on SKL. They seem to mostly be formats that don't have an alpha component, although it's not all of them, and we haven't yet found anything in the specs which would explain this. For now

Re: [Mesa-dev] [PATCH 2/2] mesa: do runtime validation of precision varyings only on ES

Please add the spec quote in the commit log. For example: From OpenGL 4.4, section 4.7 "Precision and Precision Qualifiers": "For the purposes of determining if an output from one shader stage matches an input of the next stage, the precision qualifier need not match." Other than that, Reviewed

Re: [Mesa-dev] [PATCH 18/36] glsl ubo/ssbo: Move common code into lower_buffer_access::setup_buffer_access

On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > This code will also be usable by the pass to lower shared variables. > > Note, that *const_offset is adjusted by setup_buffer_access so it must > be initialized before calling setup_buffer_access. > > Signed-off-by: Jordan Justen > Cc: Sa

Re: [Mesa-dev] [PATCH 17/36] glsl ubo/ssbo: Move is_dereferenced_thing_row_major into lower_buffer_access

Reviewed-by: Iago Toral Quiroga On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias Gonsalvez > Cc: Iago Toral Quiroga > --- > src/glsl/lower_buffer_access.cpp | 90 > > src/glsl/lower_buffer_ac

Re: [Mesa-dev] [PATCH 16/36] glsl ubo/ssbo: Add lower_buffer_access class

On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > This class has code that will be shared by lower_ubo_reference and > lower_shared_reference. (lower_shared_reference will be used to > support compute shader shared variables.) > > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias Gonsalv

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 11/16/2015 01:35 PM, Tapani Pälli wrote: On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: Hello Ilia, Tapani: I have reproduced the issue with a piglit test but not with the trace uploaded in the bug report :-( The piglit test was: bin/arb_shader_storage_buffer_object-maxblocks

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 16/11/15 12:35, Tapani Pälli wrote: > > > On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: >> Hello Ilia, Tapani: >> >> I have reproduced the issue with a piglit test but not with the trace >> uploaded in the bug report :-( >> >> The piglit test was: bin/arb_shader_storage_buffer_obj

Re: [Mesa-dev] [PATCH] nvc0: fix wrong value for NVC8_COMPUTE_CLASS

On 11/16/2015 11:55 AM, Emil Velikov wrote: On 9 October 2015 at 14:10, Samuel Pitoiset wrote: Compute class value for GF110+ is 0x91c0 and not 0x92c0. This fixes compute support and MP performance counters on GF110. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv_object

Re: [Mesa-dev] [PATCH 1/2] glsl: initialize precision when adding per vertex record fields

Reviewed-by: Samuel Iglesias Gonsálvez On 16/11/15 07:44, Tapani Pälli wrote: > Fixes issues with tessellation builtin variables since precision was > introduced to IR with commit f84bc57d7dc02fceb805803131426c791eadeff9. > > Signed-off-by: Tapani Pälli > --- > src/glsl/builtin_variables.cpp |

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 11/16/2015 01:29 PM, Samuel Iglesias Gonsálvez wrote: Hello Ilia, Tapani: I have reproduced the issue with a piglit test but not with the trace uploaded in the bug report :-( The piglit test was: bin/arb_shader_storage_buffer_object-maxblocks I have upload a branch with some fixes at Igal

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

Hello Ilia, Tapani: I have reproduced the issue with a piglit test but not with the trace uploaded in the bug report :-( The piglit test was: bin/arb_shader_storage_buffer_object-maxblocks I have upload a branch with some fixes at Igalia's mesa repo: Git repo: https://github.com/Igalia/mesa.git

Re: [Mesa-dev] [PATCH 15/36] glsl ubo/ssbo: Split buffer access to insert_buffer_access

Looks good to me, Reviewed-by: Iago Toral Quiroga On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > This allows the code in emit_access to be generic enough to also be > for lowering shared variables. > > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias Gonsalvez > Cc: Iago Toral Qu

Re: [Mesa-dev] [PATCH 00/36] Computer shader shared variables

I can confirm that this patch-set does not cause any regression for GLES 3.1 CTS test on HSW and BDW. > -Original Message- > From: Justen, Jordan L > Sent: Saturday, November 14, 2015 10:44 PM > To: mesa-dev@lists.freedesktop.org > Cc: Kristian Høgsberg Kristensen; Lofstedt, Marta; Palli,

Re: [Mesa-dev] [PATCH 14/36] glsl ubo/ssbo: Use enum to track current buffer access type

On Sat, 2015-11-14 at 13:43 -0800, Jordan Justen wrote: > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias Gonsalvez > Cc: Iago Toral Quiroga > --- > src/glsl/lower_ubo_reference.cpp | 26 +- > 1 file changed, 21 insertions(+), 5 deletions(-) > > diff --git a/src/glsl

Re: [Mesa-dev] [PATCH] nvc0: fix wrong value for NVC8_COMPUTE_CLASS

On 9 October 2015 at 14:10, Samuel Pitoiset wrote: > Compute class value for GF110+ is 0x91c0 and not 0x92c0. This fixes > compute support and MP performance counters on GF110. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nv_object.xml.h | 2 +- > 1 file changed, 1 inse

Re: [Mesa-dev] [PATCH 1/5] nv50: implement a basic compute support

On 11/16/2015 11:47 AM, Emil Velikov wrote: On 16 November 2015 at 10:39, Emil Velikov wrote: Hi Samuel, On 13 November 2015 at 00:04, Samuel Pitoiset wrote: This adds the ability to launch simple compute kernels like the one I will use to read out MP performance counters in the upcoming p

Re: [Mesa-dev] [PATCH 1/5] nv50: implement a basic compute support

On 16 November 2015 at 10:39, Emil Velikov wrote: > Hi Samuel, > > On 13 November 2015 at 00:04, Samuel Pitoiset > wrote: >> This adds the ability to launch simple compute kernels like the one I >> will use to read out MP performance counters in the upcoming patch. >> >> This compute support is

Re: [Mesa-dev] [PATCH 1/5] nv50: implement a basic compute support

Hi Samuel, On 13 November 2015 at 00:04, Samuel Pitoiset wrote: > This adds the ability to launch simple compute kernels like the one I > will use to read out MP performance counters in the upcoming patch. > > This compute support is based on the work of Francisco Jerez (aka curro) > that he did

Re: [Mesa-dev] [PATCH 00/11] i965/nir: Do texture rectangle lowering in NIR

On Wed, 2015-11-11 at 17:27 -0800, Jason Ekstrand wrote: > On Wed, Nov 11, 2015 at 5:23 PM, Jason Ekstrand wrote: > > On older hardware (Iron Lake and below), we can't support texture rectangle > > natively. Sandy Bridge through Haswell can support it but don't support > > the GL_CLAMP wrap mode

Re: [Mesa-dev] [PATCH 16/36] glsl ubo/ssbo: Add lower_buffer_access class

Hi Jordan, On 14 November 2015 at 21:43, Jordan Justen wrote: > This class has code that will be shared by lower_ubo_reference and > lower_shared_reference. (lower_shared_reference will be used to > support compute shader shared variables.) > > Signed-off-by: Jordan Justen > Cc: Samuel Iglesias

Re: [Mesa-dev] [PATCH 11/11] i965: Use nir_lower_tex for texture coordinate lowering

On Wed, 2015-11-11 at 17:26 -0800, Jason Ekstrand wrote: > Previously, we had a rescale_texcoords helper in the FS backend for > handling rescaling of texture coordinates. Now that we can do variants in > NIR, we can use nir_lower_tex to do the rescaling for us. This allows us > to delete the i96

Re: [Mesa-dev] [PATCH] radeonsi: enable optimal raster config setting for fiji (v2)

Reviewed-by: Marek Olšák Marek On Fri, Nov 13, 2015 at 10:53 PM, Alex Deucher wrote: > Requires proper kernel tiling configurarion so check the tiling > config registers. > > v2: send the right version of the patch > > Signed-off-by: Alex Deucher > Cc: mesa-sta...@lists.freedesktop.org > --- >

Re: [Mesa-dev] [PATCH] radeonsi: use proper GRBM_GFX_INDEX offset for CI+

Reviewed-by: Marek Olšák Marek On Fri, Nov 13, 2015 at 10:22 PM, Alex Deucher wrote: > The offset is different on CI and newer. > > Signed-off-by: Alex Deucher > --- > src/gallium/drivers/radeonsi/si_state.c | 16 > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --

Re: [Mesa-dev] [PATCH 10/10] radeon: count cs dwords separately for query begin and end

For the series: Reviewed-by: Marek Olšák Marek On Fri, Nov 13, 2015 at 5:10 PM, Nicolai Hähnle wrote: > This will be important for perfcounter queries. > --- > src/gallium/drivers/radeon/r600_query.c | 33 > +++-- > src/gallium/drivers/radeon/r600_query.h | 3 ++-

Re: [Mesa-dev] [PATCH 07/11] i965: Move postprocess_nir to codegen time

On Fri, 2015-11-13 at 07:34 -0800, Jason Ekstrand wrote: > > On Nov 13, 2015 5:53 AM, "Iago Toral" wrote: > > > > On Wed, 2015-11-11 at 17:26 -0800, Jason Ekstrand wrote: > > > --- > > > src/mesa/drivers/dri/i965/brw_fs.cpp | 11 > +-- > > > src/mesa/drivers/dri/i965/brw_nir

Re: [Mesa-dev] [PATCH v5 5/7] glsl: Add precision information to ir_variable

On 13/11/15 21:38, Ilia Mirkin wrote: > On Fri, Nov 13, 2015 at 2:37 PM, Ilia Mirkin wrote: >> Looks like valgrind hates this for some reason. I'm seeing lots of >> >> ==16821== Conditional jump or move depends on uninitialised value(s) >> ==16821==at 0xA074D09: glsl_type::record_compare(gls

Re: [Mesa-dev] [PATCH 03/36] i965: Define state flag to signal that the URB size has been altered.

Reviewed-by: Jordan Justen On 2015-11-14 13:43:39, Jordan Justen wrote: > From: Francisco Jerez > > This will make sure that we recalculate the URB layout anytime the URB > size is modified by the L3 partitioning code. > --- > src/mesa/drivers/dri/i965/brw_context.h | 2 ++ > src/mesa/dri

Re: [Mesa-dev] [PATCH 1/2] i965: Convert scalar_* flags to a scalar_stage array.

On Fri, Nov 13, 2015 at 11:29:00AM -0800, Kenneth Graunke wrote: > On Friday, November 13, 2015 10:06:23 AM Pohjolainen, Topi wrote: > > On Thu, Nov 12, 2015 at 03:38:51PM -0800, Kenneth Graunke wrote: > > > I was going to add scalar_tcs and scalar_tes flags, and then thought > > > better of it and