[Mesa-dev] [Bug 94564] [swrast] piglit attribs regression

https://bugs.freedesktop.org/show_bug.cgi?id=94564 Bug ID: 94564 Summary: [swrast] piglit attribs regression Product: Mesa Version: 11.2 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Keywords:

Re: [Mesa-dev] [PATCH 2/2] nir: Reuse nir_src_as_const_val() in one more place.

On Tue, Mar 15, 2016 at 8:41 PM, Eric Anholt wrote: > I copy and pasted this code before finding the helper. > --- > src/compiler/nir/nir_opt_constant_folding.c | 10 +++--- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 1/2] nir: Optimize out discard_ifs with a constant 0 argument.

On Tue, Mar 15, 2016 at 8:41 PM, Eric Anholt wrote: > I found this in a shader that was doing an alpha test when alpha is fixed > at 1.0. > > instructions in affected programs: 16 -> 15 (-6.25%) > total uniforms in shared programs: 28703 -> 28703 (0.00%) > --- >

Re: [Mesa-dev] [PATCH V3 2/2] glsl: disable varying packing when its not safe

Sorry please ignore this for the moment I also need to include rules for not packing tess amoung other things now that this is based off master. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

[Mesa-dev] [PATCH 2/2] nir: Reuse nir_src_as_const_val() in one more place.

I copy and pasted this code before finding the helper. --- src/compiler/nir/nir_opt_constant_folding.c | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index 8a353c2..190a509

[Mesa-dev] [PATCH 1/2] nir: Optimize out discard_ifs with a constant 0 argument.

I found this in a shader that was doing an alpha test when alpha is fixed at 1.0. instructions in affected programs: 16 -> 15 (-6.25%) total uniforms in shared programs: 28703 -> 28703 (0.00%) --- src/compiler/nir/nir_opt_constant_folding.c | 8 1 file changed, 8 insertions(+) diff

[Mesa-dev] [PATCH 22/20] radeonsi: disable early Z if the fragment shader writes to memory

From: Nicolai Hähnle Empirically, both the EXEC_ON_* flags and LATE_Z are necessary. --- src/gallium/drivers/radeonsi/si_state_shaders.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c

[Mesa-dev] [PATCH 21/20] tgsi/scan: add writes_memory to flag presence of stores or atomics

From: Nicolai Hähnle --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 12 src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c

[Mesa-dev] [PATCH 06.5/20] radeonsi: update shader image descriptor for invalidated buffer

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index

[Mesa-dev] [PATCH v2 3/3] vc4: Add partial NIR->QIR control flow graph loops

Fixes the following piglit tests: - shaders/complex-loop-analysis-bug - shaders/glsl-fs-discard-04 Converts the following piglit tests from crash to fail: - shaders/glsl-fs-continue-inside-do-while - shaders/glsl-fs-loop - shaders/glsl-fs-loop-continue - shaders/glsl-fs-loop-nested -

[Mesa-dev] [PATCH V3 2/2] glsl: disable varying packing when its not safe

In GL 4.4+ there is no guarantee that interpolation qualifiers will match between stages so we cannot safely pack varyings using the current packing pass in Mesa. We also disable packing on outward facing SSO as these too are outside the rule that guarantees the interpolation qualifiers match.

[Mesa-dev] [PATCH 1/2] glsl: pass disable_varying_packing bool to the lowering pass

This will allow us to choose to ignore the disable which will be useful for more fine grained control over when to enable or disable packing. Reviewed-by: Anuj Phogat Reviewed-by: Edward O'Callaghan Reviewed-by: Kenneth Graunke

Re: [Mesa-dev] [PATCH] radeonsi: fix Hyper-Z hangs on P2 configs

On Wed, Mar 16, 2016 at 12:05 AM, Nicolai Hähnle wrote: > If I understand your patch correctly, the only effect is that a larger HTILE > buffer is allocated, right? I'm surprised that only hangs were reported and > not VM faults. We should really introduce guard pages / gaps

[Mesa-dev] [Bug 94561] [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value on 32 bits (with 16GB ram)

https://bugs.freedesktop.org/show_bug.cgi?id=94561 --- Comment #3 from Roland Scheidegger --- FWIW even if the number reported wouldn't overflow, reporting 16GB on 32bit probably isn't really the right answer. If you'd try to use that much memory, it would not quite succeed -

[Mesa-dev] [Bug 94561] [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value on 32 bits (with 16GB ram)

https://bugs.freedesktop.org/show_bug.cgi?id=94561 --- Comment #2 from Roland Scheidegger --- At a very quick glance I would suspect it's os_get_total_physical_memory() which isn't working. This has phys_pages * page_size which are both just long which would overflow. If you

Re: [Mesa-dev] [PATCH] radeonsi: fix Hyper-Z hangs on P2 configs

If I understand your patch correctly, the only effect is that a larger HTILE buffer is allocated, right? I'm surprised that only hangs were reported and not VM faults. We should really introduce guard pages / gaps between mapped buffers. It seems like htile.{pitch, height, xalign, yalign} are

Re: [Mesa-dev] [PATCH] mesa: Ignore glPointSize when GL_POINT_SIZE_ARRAY_OES is enabled

On Tuesday, March 15, 2016 8:39:49 PM PDT Plamena Manolova wrote: > When a user defines a point size array and enables it, the point > size value set via glPointSize should be ignored. To achieve this, > we can simply omit point size when creating a batch inside > upload_sf_state for brw, gen6,

[Mesa-dev] [Bug 94561] [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value

https://bugs.freedesktop.org/show_bug.cgi?id=94561 --- Comment #1 from Axel Davy --- Actually, my test was 32 bits, and I just checked 64 bits and the issue is not there. I'm going to adjust the name of the bug to indicate this information. -- You are receiving this mail

[Mesa-dev] [Bug 94561] [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value on 32 bits (with 16GB ram)

https://bugs.freedesktop.org/show_bug.cgi?id=94561 Axel Davy changed: What|Removed |Added Summary|[llvmpipe] |[llvmpipe]

Re: [Mesa-dev] [PATCH 4/7] main: rework the compatibility check of visuals in glXMakeCurrent

On 03/04/2016 12:11 AM, Miklós Máté wrote: On 02/25/2016 08:20 PM, Ian Romanick wrote: On 02/25/2016 07:48 AM, Brian Paul wrote: On 02/25/2016 08:26 AM, Miklós Máté wrote: On 02/25/2016 02:37 AM, Brian Paul wrote: On 02/24/2016 04:35 PM, Miklós Máté wrote: Now it follows the GLX 1.4

[Mesa-dev] [Bug 94561] [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value

https://bugs.freedesktop.org/show_bug.cgi?id=94561 Bug ID: 94561 Summary: [llvmpipe] PIPE_CAP_VIDEO_MEMORY reports negative value Product: Mesa Version: git Hardware: Other OS: All Status: NEW

[Mesa-dev] [PATCH] radeonsi: fix Hyper-Z hangs on P2 configs

From: Marek Olšák Cc: 11.1 11.2 --- src/gallium/drivers/radeon/r600_texture.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c

[Mesa-dev] [PATCH 3/5] nvc0: remove unused data in driver CB at 0x0 for Kepler

This weird thing is there since 2013 and doesn't seem to be used (according to the codegent part). I have carefully read the code to make sure this is really unused but I will double-check with piglit. This frees the first 32 bytes of the driver constant buffer. Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH 4/5] nvc0: avoid using magic numbers for the uniform_bo offsets

Instead make use of constants to improve readability. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 13 +- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 22 +

[Mesa-dev] [PATCH 0/5] nvc0: driver constant buffer changes

Hi, This new series improves things related to the driver constant buffer which are useful for compute shaders on gk104+. I have still not tested the series. Please review, Thanks! Samuel Pitoiset (5): nv50,nvc0: replace resInfoCBSlot by auxCBSlot nv50/ir: make use of auxCBSlot instead of

[Mesa-dev] [PATCH 5/5] nvc0: shift driver constant buffer offsets by 32 bytes

The first 32 bytes of the driver constant buffer are currently unused. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 1/5] nv50, nvc0: replace resInfoCBSlot by auxCBSlot

Having two different variables for the driver constant buffer slot is confusing and really useless. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 3 +-- .../drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp|

[Mesa-dev] [PATCH 2/5] nv50/ir: make use of auxCBSlot instead of magic numbers

This avoids using magic numbers for the driver constbuf slot which is always 15 except for compute shaders on gk104+ where the slot 0 is used. For gk104+, some special compute-related values like the thread index are uploaded to screen->parm which is currently bound on c0. Signed-off-by: Samuel

Re: [Mesa-dev] [PATCH 01/10] i965: Remove incorrect cycle estimates.

Matt Turner writes: > These printed the cycle count the last basic block (sched.time is set > per basic block!). We have accurate, full program, data printed > elsewhere. Reviewed-by: Francisco Jerez > --- >

Re: [Mesa-dev] [PATCH 03/10] i965: Simplify full scheduling-barrier conditions.

Matt Turner writes: > All of these were simply code for "architecture register file" (and in > the case of destinations, "not the null register"). > --- > .../drivers/dri/i965/brw_schedule_instructions.cpp | 35 > +- > 1 file changed, 8 insertions(+), 27

Re: [Mesa-dev] [PATCH 7/9] i965/nir: Lower nir compute shader shared variables

On Mon, Mar 14, 2016 at 11:57 PM, Jordan Justen wrote: > Signed-off-by: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + > src/mesa/drivers/dri/i965/brw_nir.c | 8 > src/mesa/drivers/dri/i965/brw_nir.h | 1 + > 3

Re: [Mesa-dev] [PATCH v2 05/10] i965/vec4/tcs: Set conditional mod on TCS_OPCODE_SRC0_010_IS_ZERO.

Matt Turner writes: > Missing this causes an assertion failure in the scheduler with the next > patch. > --- > src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 - > src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 4 +++- > 2 files changed, 3 insertions(+), 2

Re: [Mesa-dev] [PATCH 6/9] nir: Lower shared var atomics during nir_lower_io

On Mon, Mar 14, 2016 at 11:57 PM, Jordan Justen wrote: > Signed-off-by: Jordan Justen > --- > src/compiler/nir/nir_lower_io.c | 86 > - > 1 file changed, 84 insertions(+), 2 deletions(-) > > diff

Re: [Mesa-dev] [PATCH 3/3] vc4: Add NIR->QIR control flow graph loops

Rhys Kidd writes: > Fixes the following piglit tests: > - shaders/complex-loop-analysis-bug > - shaders/glsl-fs-discard-04 > > Converts the following piglit tests from crash to fail: > - shaders/glsl-fs-continue-inside-do-while > - shaders/glsl-fs-loop > -

Re: [Mesa-dev] [PATCH 3/9] squash: Increase nir_variable_data::mode to 5 bits

Thanks for catching this! It came up before when I reworked function calls but, thanks to the order in which things got merged, it had to be done in your series. On Mon, Mar 14, 2016 at 11:56 PM, Jordan Justen wrote: > Prevents: > >

Re: [Mesa-dev] [PATCH v2 3/4] docs: Renormalize some extensions.

I sent a v2 of the patches with your proposition Nicolai. I think I don't have the rights to push patches, so it would be great if you could do it. 2016-03-15 16:14 GMT-04:00 Romain Failliot : > This fixes some exceptions I have to deal with in mesamatrix.net. > The

Re: [Mesa-dev] [PATCH 05/10] i965/vec4: Mark TCS_OPCODE_SRC0_010_IS_ZERO as writing the flag.

Kenneth Graunke writes: > On Monday, March 14, 2016 5:25:58 PM PDT Matt Turner wrote: >> On Mon, Mar 14, 2016 at 5:22 PM, Matt Turner wrote: >> > On Mon, Mar 14, 2016 at 5:10 PM, Francisco Jerez > wrote: >> >> Matt Turner

Re: [Mesa-dev] [PATCH 05/10] i965/vec4: Mark TCS_OPCODE_SRC0_010_IS_ZERO as writing the flag.

Matt Turner writes: > On Mon, Mar 14, 2016 at 9:32 PM, Kenneth Graunke > wrote: >> On Monday, March 14, 2016 5:25:58 PM PDT Matt Turner wrote: >>> On Mon, Mar 14, 2016 at 5:22 PM, Matt Turner wrote: >>> > On Mon, Mar 14, 2016 at

[Mesa-dev] [PATCH v2 2/4] docs: Realign the "Status" column.

The "Status" column was misaligned in some GL sections. This is a lot of diffs, but it's only spaces in the end. --- docs/GL3.txt | 278 +-- 1 file changed, 139 insertions(+), 139 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index

[Mesa-dev] [PATCH v2 3/4] docs: Renormalize some extensions.

This fixes some exceptions I have to deal with in mesamatrix.net. The extensions GL_ARB_texture_buffer_object had a comment between "DONE" and the brackets. And the extension GL_KHR_robustness (in GL 4.5 and GLES 3.1) was using "90% done" instead of "in progress". The "90% done" is still here

[Mesa-dev] [PATCH v2 4/4] docs: Renormalize older extensions.

For older extensions, there is an explanation first and the extension name in brackets, like that: Clamping controls (GL_ARB_color_buffer_float) I inverted that so we have the extension first and then the explanation in brackets, like that: GL_ARB_color_buffer_float (Clamping controls) It

[Mesa-dev] [PATCH v2 1/4] docs: howto to read and edit GL3.txt

Added a small guide on how to read and edit GL3.txt. I think this would help as much the devs as the users reading this file. --- docs/GL3.txt | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index ee7faca..1ed5c1a 100644

[Mesa-dev] [PATCH 7/7] nv50: add a new validation path for compute

From: Samuel Pitoiset This makes use of the new state validation interface to be consistent with 3d. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_compute.c | 25 + 1 file changed, 13

[Mesa-dev] [PATCH 4/7] nv50: rename 3d binding points to NV50_BIND_3D_XXX

From: Samuel Pitoiset Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_context.c| 24 +++--- src/gallium/drivers/nouveau/nv50/nv50_context.h| 20 +-

[Mesa-dev] [PATCH 2/7] nv50: rename NV50_COMPUTE to NV50_CP

From: Samuel Pitoiset Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 90 +++--- .../drivers/nouveau/nv50/nv50_query_hw_sm.c| 10 +--

[Mesa-dev] [PATCH 3/7] nv50: rename 3d dirty flags to NV50_NEW_3D_XXX

From: Samuel Pitoiset Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 2 +- src/gallium/drivers/nouveau/nv50/nv50_context.c| 10 +-- src/gallium/drivers/nouveau/nv50/nv50_context.h| 44

[Mesa-dev] [PATCH 6/7] nv50: rework nv50_compute_validate_program()

From: Samuel Pitoiset Reduce the amount of duplicated code by re-using nv50_program_validate(). While we are at it, change the prototype to return void. We don't check anymore if the translation fails but improving the state validation is a long process.

[Mesa-dev] [PATCH 5/7] nv50: rework the validation path for 3D

From: Samuel Pitoiset This exposes an interface for state validation that will be also used to rework the compute validation path. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_context.h| 10 +-

[Mesa-dev] [PATCH 1/7] nv50: rename nv50_context::dirty to nv50_context::dirty_3d

From: Samuel Pitoiset Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 2 +- src/gallium/drivers/nouveau/nv50/nv50_context.c| 10 +++--- src/gallium/drivers/nouveau/nv50/nv50_context.h| 2 +-

[Mesa-dev] [PATCH 0/7] nv50: rework compute/3d validation path

From: Samuel Pitoiset Hi, This is loosely based on what I did for nvc0 few weeks ago. I have not tested this series because I don't have access to a Tesla card, but this should not break anything. By the way, doing almost the same series twice is not so cool but...

Re: [Mesa-dev] [PATCH 3/4] docs: Renormalize some extensions.

Thanks for taking the time to clean up the patches! On 15.03.2016 07:45, Romain Failliot wrote: Hmm... I thought that was what it meant. I can add a new status like "paused" for instance. "not started" is probably more accurate. AFAIU, ARB_robustness is implemented, and that represents 90%

Re: [Mesa-dev] [PATCH] meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.

Indeed, none of nouveau_vieux, radeon, or r200 support GLSL. Of course, no classic driver except i965 supports #version 130, so those are clear. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH 05/10] i965/vec4: Mark TCS_OPCODE_SRC0_010_IS_ZERO as writing the flag.

On Mon, Mar 14, 2016 at 9:32 PM, Kenneth Graunke wrote: > On Monday, March 14, 2016 5:25:58 PM PDT Matt Turner wrote: >> On Mon, Mar 14, 2016 at 5:22 PM, Matt Turner wrote: >> > On Mon, Mar 14, 2016 at 5:10 PM, Francisco Jerez >

[Mesa-dev] [PATCH] i965: Account for TES in is_drawing_points().

Now that we implement tessellation shaders, the TES might be the last stage enabled. If it's outputting points, then the primitive type reaching the SF is points. We need to account for this. Caught by Ilia Mirkin. Signed-off-by: Kenneth Graunke ---

[Mesa-dev] [PATCH] meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.

This is cleaner than using glBindAttribLocation(). Not all drivers support the extension, but I don't think those drivers use GLSL in the first place. Apparently some Meta shaders already use GL_ARB_explicit_attrib_location, so I think it should be okay. Honestly, I'm not sure how the old code

[Mesa-dev] [Bug 94522] llvmpipe crash in rendering on Atom

https://bugs.freedesktop.org/show_bug.cgi?id=94522 --- Comment #11 from Roland Scheidegger --- FWIW the bug Stephane mentioned (which you'd hit near certainly too, unless you built without sse2 enabled, and the compositor itself might not hit it) is fixed by

[Mesa-dev] [Bug 94193] [llvmpipe] Line antialiasing looks different when GL_LINE_STIPPLE is enabled with pattern 0xffff

https://bugs.freedesktop.org/show_bug.cgi?id=94193 Roland Scheidegger changed: What|Removed |Added Resolution|--- |FIXED

[Mesa-dev] [Bug 94481] softpipe - access violation in img_filter_2d_nearest

https://bugs.freedesktop.org/show_bug.cgi?id=94481 Roland Scheidegger changed: What|Removed |Added Resolution|--- |FIXED

Re: [Mesa-dev] [PATCH 04/20] tgsi/scan: track which shader images are really buffers

Patches 1-4 are Reviewed-by: Ilia Mirkin On Tue, Mar 15, 2016 at 2:28 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +++ > src/gallium/auxiliary/tgsi/tgsi_scan.h | 4

[Mesa-dev] [PATCH] mesa: Ignore glPointSize when GL_POINT_SIZE_ARRAY_OES is enabled

When a user defines a point size array and enables it, the point size value set via glPointSize should be ignored. To achieve this, we can simply omit point size when creating a batch inside upload_sf_state for brw, gen6, gen7 and gen8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42187

[Mesa-dev] [PATCH 06/20] radeonsi: implement set_shader_images

From: Nicolai Hähnle Whether DCC is disabled depends on the access flags with which the image is bound: image_load supports DCC, but store and atomic don't. --- src/gallium/drivers/radeonsi/si_descriptors.c | 206 --

[Mesa-dev] [PATCH 16/20] radeonsi: implement volatile memory access

From: Nicolai Hähnle Prevent loads from being re-ordered or coalesced. Atomics don't need special handling by definition, and stores don't need special handling because LLVM is unable to detect dead image or buffer stores. --- src/gallium/drivers/radeonsi/si_shader.c |

[Mesa-dev] [PATCH 03/20] tgsi/scan: add images_writemask

From: Nicolai Hähnle --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 18 -- src/gallium/auxiliary/tgsi/tgsi_scan.h | 5 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c

[Mesa-dev] [PATCH 08/20] radeonsi: extract TXQ buffer size computation into its own function

From: Nicolai Hähnle This will allow it to be reused for RESQ. --- src/gallium/drivers/radeonsi/si_shader.c | 55 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c

[Mesa-dev] [PATCH 19/20] radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES

From: Edward O'Callaghan This enables ARB_shader_image_load_store and ARB_shader_image_size. Signed-off-by: Edward O'Callaghan [allow the same number of images for all shader stages and require LLVM 3.9] ---

[Mesa-dev] [PATCH 12/20] radeonsi: Lower TGSI_OPCODE_STORE down to LLVM op

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 83 ++-- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index

[Mesa-dev] [PATCH 14/20] radeonsi: Lower TGSI_OPCODE_MEMBAR down to LLVM op

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index deeda30..fcbab5f 100644 ---

[Mesa-dev] [PATCH 02/20] st/mesa: translate additional flags in MemoryBarrier

From: Nicolai Hähnle Re-order flags in the order in which they appear in the OpenGL spec in the description of MemoryBarrier(). --- src/mesa/state_tracker/st_cb_texturebarrier.c | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 10/20] radeonsi: extract the LLVM type name construction into its own function

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 373d4b4..b655e34

[Mesa-dev] [PATCH 20/20] docs: mark GL_ARB_shader_image_load_store/_size as done for radeonsi

From: Nicolai Hähnle --- docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index ee7faca..08ca8db 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -139,7 +139,7

[Mesa-dev] [PATCH 01/20] gallium: add additional PIPE_BARRIER_* bits

From: Nicolai Hähnle --- src/gallium/include/pipe/p_defines.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index bdd76ab..90af7a7 100644 --- a/src/gallium/include/pipe/p_defines.h

[Mesa-dev] [PATCH 18/20] radeonsi: force the DCC enable bit off in image descriptors for writing

From: Nicolai Hähnle This avoids a lockup at least on Tonga. --- src/gallium/drivers/radeonsi/si_shader.c | 53 +++- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c

[Mesa-dev] [PATCH 04/20] tgsi/scan: track which shader images are really buffers

From: Nicolai Hähnle --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +++ src/gallium/auxiliary/tgsi/tgsi_scan.h | 4 2 files changed, 7 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c b/src/gallium/auxiliary/tgsi/tgsi_scan.c index

[Mesa-dev] [PATCH 17/20] radeonsi: implement MemoryBarrier

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.c | 36 + 1 file changed, 36 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0c3fbdc..6dcd532 100644 ---

[Mesa-dev] [PATCH 13/20] radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 121 +-- 1 file changed, 113 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index

[Mesa-dev] [PATCH 15/20] radeonsi: implement coherent memory access

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index fcbab5f..22296fe 100644

[Mesa-dev] [PATCH 07/20] radeonsi: decompress shader images

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_blit.c | 36 +++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index

[Mesa-dev] [PATCH 11/20] radeonsi: Lower TGSI_OPCODE_LOAD down to LLVM op

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 141 +++ 1 file changed, 141 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index b655e34..e2ae39e 100644

[Mesa-dev] [PATCH 00/20] radeonsi: ARB_shader_image_load_store support

Hi, finally: ARB_shader_image_load_store (and ARB_shader_image_size) for radeonsi! You can also find this series at https://cgit.freedesktop.org/~nh/mesa/log/?h=images-radeonsi You will need bleeding edge LLVM for this to work correctly, and not all required LLVM changes have been pushed

[Mesa-dev] [PATCH 09/20] radeonsi: Lower TGSI_OPCODE_RESQ down to LLVM op

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 129 +++ 1 file changed, 129 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index a4352f1..373d4b4 100644

[Mesa-dev] [PATCH 05/20] gallium/radeon: make r600_texture_disable_dcc externally accessible

From: Nicolai Hähnle We will need it in radeonsi for shader images. --- src/gallium/drivers/radeon/r600_pipe_common.h | 2 ++ src/gallium/drivers/radeon/r600_texture.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 13/14] nir: propagate bitsize information in nir_search

On Tue, Mar 15, 2016 at 12:41 AM, Iago Toral wrote: > On Mon, 2016-03-14 at 17:33 -0700, Jason Ekstrand wrote: > > > > > > On Mon, Mar 7, 2016 at 12:46 AM, Samuel Iglesias Gonsálvez > > wrote: > > From: Connor Abbott >

Re: [Mesa-dev] [PATCH] mesa: Fix error condition for 1d array texture

On Sat, Mar 12, 2016 at 3:08 PM, Jason Ekstrand wrote: > > On Mar 11, 2016 12:33 PM, "Alejandro Piñeiro" > wrote: > > > > On 11/03/16 20:15, Anuj Phogat wrote: > > > yoffset is also applicable to 1d array textures. > > > > > > Signed-off-by: Anuj

[Mesa-dev] [Bug 94522] llvmpipe crash in rendering on Atom

https://bugs.freedesktop.org/show_bug.cgi?id=94522 --- Comment #10 from Roland Scheidegger --- Actually the asm snipped might be something different. You could try printing the whole jit prog (from the address from the caller, or use GALLIVM_DEBUG=asm). Using valgrind could

Re: [Mesa-dev] About border values in fp64 conversion tests

Not really an answer to your question, but you may be interested in this model of the NVIDIA Tesla FPU that mwk RE'd, including fp64 (which was available on the G200 only in that series). I have no reason to believe that Fermi+ are substantially different:

[Mesa-dev] [Bug 94522] llvmpipe crash in rendering on Atom

https://bugs.freedesktop.org/show_bug.cgi?id=94522 --- Comment #9 from Roland Scheidegger --- (In reply to comicfans44 from comment #8) > (In reply to Roland Scheidegger from comment #4) > > So, it crashed in the jit fragment shader code. > > Could you tell what the fb size

[Mesa-dev] About border values in fp64 conversion tests

Hi, as complementary work to the one done to "Add FP64 support to the i965 shader backends" at: https://bugs.freedesktop.org/show_bug.cgi?id=92760 I've been working to add piglit tests that would check the new features added by this addition. One of the topics we have been creating tests for is

Re: [Mesa-dev] [PATCH] draw: fix line stippling

Am 15.03.2016 um 08:20 schrieb Jose Fonseca: > On 13/03/16 20:40, srol...@vmware.com wrote: >> From: Roland Scheidegger >> >> The logic was comparing actual ints, not true/false values. >> This meant that it was emitting always multiple line segments instead >> of just >> one

Re: [Mesa-dev] About the usage of the "flat" interpolation qualifier with input (unsigned) integers and doubles in fragment shaders

Hi, I haven't had any input on this and I will welcome opinions from more knowledgeable developers :) Do you think my approach in this case would be the best? * To enforce the usage of the "flat" qualifier when in a member of an input block interface in a fragment shader for

Re: [Mesa-dev] [PATCH v2] st/mesa: honour sized internal formats in st_choose_format (v2)

On Tue, Mar 15, 2016 at 3:53 PM, Ilia Mirkin wrote: > > On Mar 15, 2016 7:23 AM, "Nicolai Hähnle" wrote: >> >> From: Nicolai Hähnle >> >> The bitcasting which is possible with shader images (and texture views?) >> requires that

Re: [Mesa-dev] [PATCH v2] st/mesa: honour sized internal formats in st_choose_format (v2)

On Mar 15, 2016 7:23 AM, "Nicolai Hähnle" wrote: > > From: Nicolai Hähnle > > The bitcasting which is possible with shader images (and texture views?) > requires that when the user specifies a sized internal format for a > texture, we really allocate

Re: [Mesa-dev] [PATCH 06/14] nir: handle different bit sizes when constant folding

On Tue, Mar 15, 2016 at 10:43 AM, Connor Abbott wrote: > On Tue, Mar 15, 2016 at 5:53 AM, Iago Toral wrote: >> On Mon, 2016-03-14 at 16:48 -0700, Jason Ekstrand wrote: >>> >>> >>> On Mon, Mar 7, 2016 at 12:46 AM, Samuel Iglesias Gonsálvez >>>

Re: [Mesa-dev] [PATCH 06/14] nir: handle different bit sizes when constant folding

On Tue, Mar 15, 2016 at 5:53 AM, Iago Toral wrote: > On Mon, 2016-03-14 at 16:48 -0700, Jason Ekstrand wrote: >> >> >> On Mon, Mar 7, 2016 at 12:46 AM, Samuel Iglesias Gonsálvez >> wrote: >> From: Connor Abbott >> >>

[Mesa-dev] [PATCH v2] st/mesa: honour sized internal formats in st_choose_format (v2)

From: Nicolai Hähnle The bitcasting which is possible with shader images (and texture views?) requires that when the user specifies a sized internal format for a texture, we really allocate that format. To this end: (1) find_exact_format should ignore sized internal

[Mesa-dev] [PATCH 36/37] mesa: add query support for GL_TRANSFORM_FEEDBACK_BUFFER interface

--- src/compiler/glsl/link_varyings.cpp | 1 + src/mesa/main/mtypes.h | 2 ++ src/mesa/main/program_resource.c| 16 +++- src/mesa/main/shader_query.cpp | 35 ++- 4 files changed, 52 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 35/37] glsl: add transform feedback buffers to resource list

--- src/compiler/glsl/linker.cpp | 14 +- src/compiler/glsl/program.h| 3 ++- src/mesa/drivers/dri/i965/brw_link.cpp | 2 +- src/mesa/program/ir_to_mesa.cpp| 2 +- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- 5 files changed, 18

[Mesa-dev] [PATCH 30/37] glsl: handle varyings that are not written to but have an xfb_offset

--- src/compiler/glsl/link_varyings.cpp | 34 -- src/compiler/glsl/link_varyings.h | 13 + 2 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index

[Mesa-dev] [PATCH 33/37] mesa: add support to query GL_OFFSET for GL_TRANSFORM_FEEDBACK_VARYING

--- src/compiler/glsl/link_varyings.cpp | 1 + src/mesa/main/mtypes.h | 1 + src/mesa/main/shader_query.cpp | 14 +++--- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index

[Mesa-dev] [PATCH 18/37] glsl: add helper to generate xfb varying names

--- src/compiler/glsl/link_varyings.cpp | 43 + 1 file changed, 43 insertions(+) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index 1044cba..fbf7626 100644 --- a/src/compiler/glsl/link_varyings.cpp +++

[Mesa-dev] [PATCH 10/37] glsl: add field to track if xfb_buffer is an explicit or implicit value

Since any of the xfb_* qualifiers trigger the shader to be in transform feedback mode we need an extra field to track if the xfb_buffer on interface members was set explicitly since xfb_buffer will always have a default value. --- src/compiler/glsl/ast_to_hir.cpp| 2 ++

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