[Mesa-dev] [PATCH v2] isl: add MCS width constraint 16 samples

Applies on top of Jason's patch : https://patchwork.freedesktop.org/patch/139603/ Signed-off-by: Lionel Landwerlin Cc: Jason Ekstrand --- src/intel/isl/isl.c | 9 + 1 file changed, 9 insertions(+) diff --git

Re: [Mesa-dev] [PATCH 4/4] r600/radeonsi: enable glsl/tgsi on-disk cache

On Mon, Feb 20, 2017 at 8:45 AM, Timothy Arceri wrote: > On 20/02/17 15:38, Edward O'Callaghan wrote: >> >> >> >> On 02/20/2017 11:15 AM, Timothy Arceri wrote: >>> >>> --- >>> src/gallium/drivers/r600/r600_pipe.c | 19 +++ >>>

[Mesa-dev] [Bug 99305] account creation request

https://bugs.freedesktop.org/show_bug.cgi?id=99305 Brian Paul changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop.

[Mesa-dev] [Bug 99849] Dashed lines (drawn via GLAMOR) are not rendered correctly

https://bugs.freedesktop.org/show_bug.cgi?id=99849 --- Comment #1 from Brian Paul --- (In reply to Max Staudt from comment #0) > This is a continuation of fdo#99708. > > Basically, since X server commit d18f5801, dashed lines with zero width are > accelerated through GLAMOR,

Re: [Mesa-dev] [PATCH 2/2] anv: Enable MSAA compression

On Feb 20, 2017 4:47 AM, "Lionel Landwerlin" wrote: On 18/02/17 00:03, Jason Ekstrand wrote: > This just enables basic MSAA compression (no fast clears) for all > multisampled surfaces. This improves the framerate of the Sascha > "multisampling" demo by 76% on my

Re: [Mesa-dev] [PATCH] isl: add MCS width constraint 16 samples

On Feb 20, 2017 4:44 AM, "Lionel Landwerlin" wrote: Applies on top of Jason's patch : https://patchwork.freedesktop.org/patch/139603/ Signed-off-by: Lionel Landwerlin Cc: Jason Ekstrand ---

[Mesa-dev] [Bug 99856] OpenCL Hello world returns "unsupported call to function get_local_size"

https://bugs.freedesktop.org/show_bug.cgi?id=99856 --- Comment #1 from Vedran Miletić --- This function should be provided by libclc. Do you have it installed? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

Re: [Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

On 02/20/2017 11:15 AM, Edward O'Callaghan wrote: > The name has become a little misleading now that it applies > to both r600g and radeonsi. > > V.2: Michel Dänzer - R600_DEBUG must continue to work. > > Signed-off-by: Edward O'Callaghan > --- >

[Mesa-dev] [Bug 98279] [vulkan/radeon] dota2 -vulkan hangs the GPU on R9-390

https://bugs.freedesktop.org/show_bug.cgi?id=98279 --- Comment #12 from Manuel Iglesias --- It seems like the bug it´s fioxed with the lastest mesa git -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the

Re: [Mesa-dev] [PATCH] radeonsi, r600g: Rename 'R600_DEBUG' -> 'RADEON_DEBUG'

I don't think this patch is necessary. I don't mind people getting confused by the name. Marek On Mon, Feb 20, 2017 at 9:42 AM, Edward O'Callaghan wrote: > The name has become a little misleading now that it applies > to both r600g and radeonsi. > > Signed-off-by:

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi: fix UINT/SINT clamping for 10-bit formats on <= CIK

For the series: Reviewed-by: Marek Olšák Marek On Mon, Feb 20, 2017 at 12:21 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > The same PS epilog workaround as for 8-bit integer formats is required, > since the CB doesn't

Re: [Mesa-dev] [PATCH] tgsi-dump: dump label if instruction has one

On 09/02/17 14:41, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau The instruction has an associated label when Instruction.Label == 1, as can be seen in ureg_emit_label() or tgsi_build_full_instruction(). This fixes dump generating extra :0 labels on

Re: [Mesa-dev] [PATCH] winsys/amdgpu: reduce max_alloc_size based on GTT limits

Reviewed-by: Marek Olšák Marek On Sun, Feb 19, 2017 at 8:25 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Allocating huge buffers in VRAM is not a problem, but when those buffers > start being migrated, the kernel runs

Re: [Mesa-dev] [PATCH] mesa: remove unused variable warning in release builds

Reviewed-by: Marek Olšák Marek On Mon, Feb 20, 2017 at 12:16 AM, Timothy Arceri wrote: > This assert might have made sense before but we no longer use > gl_linked_shader here. Unless the caller has really done something > crazy this assert is fairly

[Mesa-dev] [Bug 98833] [REGRESSION, bisected] Wayland revert commit breaks non-Vsync fullscreen frame updates

https://bugs.freedesktop.org/show_bug.cgi?id=98833 --- Comment #15 from Eero Tamminen --- Ok, as it happens on HSW, BDW & SKL, I would say that it's a generic problem. Is there any Mesa driver which non-vsynched frame updates are not broken by the indicated Mesa

Re: [Mesa-dev] [PATCH] i965: Placement of brw_set_src1 function definition

Reviewed-by: Samuel Iglesias Gonsálvez On Mon, 2017-02-20 at 15:28 +0200, Lonnberg, Toni wrote: > The function definition is now next to where the other similar > functions are > defined. > --- >  src/mesa/drivers/dri/i965/brw_eu.h | 3 +-- >  1 file changed, 1 insertion(+),

[Mesa-dev] [Bug 98833] [REGRESSION, bisected] Wayland revert commit breaks non-Vsync fullscreen frame updates

https://bugs.freedesktop.org/show_bug.cgi?id=98833 --- Comment #14 from Pekka Paalanen --- (In reply to Eero Tamminen from comment #9) > Created attachment 128240 [details] [review] > Patch to add frame swap delay option to weston-simple-egl > > That wasn't enough, nor was

[Mesa-dev] [PATCH 10/10] i965/disasm: 3-src instruction swizzle output

From: "Lonnberg, Toni" Pre-work for the new shader assember. To produce the exact same bit representation, the assembler needs to see the swizzle of the source operands even when RepCtrl is not set. --- src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++--- 1 file changed,

[Mesa-dev] [PATCH 09/10] i965/disasm: Message descriptor type change

From: "Lonnberg, Toni" Pre-work for the new shader assembler. To make it easier to read the shader disassembly, the message descriptor is typed as unsigned so it's easier to decode the individual parts from the disassembled hexadecimal value. ---

[Mesa-dev] [PATCH 07/10] i965/disasm: Immediate values as legible numbers

From: "Lonnberg, Toni" If the "disasm" flag is used in the INTEL_DEBUG debug flags, as all immediate values will be output as hexadecimals, the values are not easily understood when just looking at the disassembly so now the values are output in a legible format as a

[Mesa-dev] [PATCH 08/10] i965/disasm: Register region formatting

From: "Lonnberg, Toni" Pre-work for the new shader assembler. To follow more the style of the documentation and for the shader assembler parser to be able to handle different styles of register region definitions, the vertical stride is now delimited differently from

[Mesa-dev] [PATCH] i965: Placement of brw_set_src1 function definition

The function definition is now next to where the other similar functions are defined. --- src/mesa/drivers/dri/i965/brw_eu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index cd7b9db..99f8f75 100644

[Mesa-dev] [PATCH 00/10] i965/disasm: Shader disassembly formatting changes

From: "Lonnberg, Toni" This and the previous shader disassembly patches replace these previous patches: [PATCH 3/3] Changed shader disassembler number formatting to use integers when the "disasm" debug flag is used. Register types and regions are also now formatted

[Mesa-dev] [PATCH 04/10] i965/disasm: Support for disassembling SENDS and SENDSC

From: "Lonnberg, Toni" The shader disassembly now decodes SENDS/SENDSC instructions. Due to ambiguity in the documentation, the decoding of the version where a scalar register is used as the extra descriptor, this might need to be re-implemented. ---

[Mesa-dev] [PATCH 06/10] i965/disasm: Immediate value formatting

From: "Lonnberg, Toni" Pre-work for the new shader assembler. For the assembler to be able to produce the same bit representation for immediate values used by disassembled shaders, the disassembly needs to output the values as hexadecimals. To remove any ambiguity

[Mesa-dev] [PATCH 03/10] i965/disasm: Formatting of decoded descriptors in SEND/SENDC instructions

From: "Lonnberg, Toni" The decoded information about the message descriptors in SEND/SENDC instructions are formatted to the same line as the instruction in shader disassembly so that it's more readable and easier for the new shader assembler to parse. ---

[Mesa-dev] [PATCH 2/6] i965/disasm: Changed visibility of has_uip and has_jip

From: "Lonnberg, Toni" Pre-work for shader disassembly label support. --- src/mesa/drivers/dri/i965/brw_disasm.c | 12 ++-- src/mesa/drivers/dri/i965/brw_eu.h | 2 ++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 6/6] i965/disasm: Indentation correction

From: "Lonnberg, Toni" Corrected the indentation where tabs were being used. --- src/mesa/drivers/dri/i965/brw_eu.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu.c

[Mesa-dev] [PATCH 5/6] i965/disasm: Label support in shader disassembly for instructions with UIP/JIP

From: "Lonnberg, Toni" Shader instructions which use UIP/JIP now get formatted with a label instead of an immediate value if the "disasm" flag has been set in the INTEL_DEBUG debug flags, and the jump targets themselves also get printed as labels into the shader

[Mesa-dev] [PATCH 4/6] i965/disasm: Label support functions

From: "Lonnberg, Toni" Pre-work for shader disassembly label support. Introduction of the structures and functions used by the shader disassembly jump target labeling. --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_eu.c | 46

[Mesa-dev] [PATCH 05/10] i965/disasm: Register type formatting

From: "Lonnberg, Toni" Pre-work for the new shader assembler. To avoid ambiguity in the shader assembler when parsing, all immediate values will need a delimiter to describe the type of the value being used. For consistency, all register values are formatted with the

[Mesa-dev] [PATCH 3/6] i965/disasm: New debug flag for shader disassembly changes

From: "Lonnberg, Toni" Pre-work for shader disassembly label support. Setting the "disasm" flag in the INTEL_DEBUG flags will enable label support for the shader disassembly and change the formatting of immediate values to use hexadecimals for all types. ---

[Mesa-dev] [PATCH 01/10] i965/disasm: SFID and src1 decoding for SEND/SENDC instructions in shader disassembly

From: "Lonnberg, Toni" The shader disassembly now shows the SFID field and will always output the second source operand in the disassembled SEND and SENDC instructions. --- src/mesa/drivers/dri/i965/brw_disasm.c | 14 -- 1 file changed, 8 insertions(+), 6

[Mesa-dev] [PATCH 1/6] intel/aubinator: Use brw_defines.h for command buffer opcodes

From: "Lonnberg, Toni" Pre-work for shader disassembly label support. Adding label support of jump instructions for shader disassembly requires including brw_eu.h for the handling of the INTEL_DEBUG flags. brw_eu.h includes brw_defines.h which also defines the command

[Mesa-dev] [PATCH 02/10] i965/disasm: Instruction options field placement in shader disassembly

From: "Lonnberg, Toni" The instruction options are now output in front of the decoded descriptor information of SEND/SENDC instructions. --- src/mesa/drivers/dri/i965/brw_disasm.c | 99 +- 1 file changed, 50 insertions(+), 49 deletions(-)

[Mesa-dev] [PATCH 0/6] i965/disasm: Shader disassembly label support

From: "Lonnberg, Toni" This and the following other patch set replace these previous patches: [PATCH 3/3] Changed shader disassembler number formatting to use integers when the "disasm" debug flag is used. Register types and regions are also now formatted more

[Mesa-dev] [Bug 99246] [d3dadapter+radeonsi & bisect] EVE-Online : hang on wormhole sight

https://bugs.freedesktop.org/show_bug.cgi?id=99246 Mathieu Belanger changed: What|Removed |Added Status|RESOLVED|REOPENED

Re: [Mesa-dev] [PATCH 2/2] anv: Enable MSAA compression

On 18/02/17 00:03, Jason Ekstrand wrote: This just enables basic MSAA compression (no fast clears) for all multisampled surfaces. This improves the framerate of the Sascha "multisampling" demo by 76% on my Sky Lake laptop. Running Talos on medium settings with 8x MSAA, this improves the

Re: [Mesa-dev] [PATCH] android: define HAVE_DL_ITERATE_PHDR for build-id code

On 02/20/2017 11:31 AM, Tapani Pälli wrote: Reviewed-by: Tapani Pälli FYI while this fixes the build errors it seems that there is some issue within the code that this enables, I'm getting a segfault within dl_iterate_phdr, will investigate why this is. On

[Mesa-dev] [PATCH] isl: add MCS width constraint 16 samples

Applies on top of Jason's patch : https://patchwork.freedesktop.org/patch/139603/ Signed-off-by: Lionel Landwerlin Cc: Jason Ekstrand --- src/intel/isl/isl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/isl/isl.c

[Mesa-dev] [ANNOUNCE] mesa 13.0.5

Mesa 13.0.5 is now available. In this release we have: On the GLX/EGL front we have a GLVND fix for "The Binding of Isaac: Rebirth" and other games, EGL Wayland buffer age rendering is back to normal. Over a dozen of GLSL patches, addressing multiple CTS/dEQP tests. A couple Vulkan WSI

Re: [Mesa-dev] [PATCH v2 1/3] i965/fs: fix indirect load DF uniforms on BSW/BXT

On Mon, 2017-02-20 at 08:58 +0100, Samuel Iglesias Gonsálvez wrote: > On Sat, 2017-02-18 at 18:58 -0800, Francisco Jerez wrote: > > Samuel Iglesias Gonsálvez writes: > > > > > The lowered BSW/BXT indirect move instructions had incorrect > > > source types, which luckily

Re: [Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

On 02/20/2017 10:41 PM, Gustaw Smolarczyk wrote: > 2017-02-20 11:19 GMT+01:00 Edward O'Callaghan : >> >> On 02/20/2017 09:15 PM, Edward O'Callaghan wrote: >>> The name has become a little misleading now that it applies >>> to both r600g and radeonsi. >>> >>> V.2:

Re: [Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

2017-02-20 11:19 GMT+01:00 Edward O'Callaghan : > > On 02/20/2017 09:15 PM, Edward O'Callaghan wrote: >> The name has become a little misleading now that it applies >> to both r600g and radeonsi. >> >> V.2: Michel Dänzer - R600_DEBUG must continue to work. >> >>

[Mesa-dev] [PATCH 2/2] radeonsi: fix UINT/SINT clamping for 10-bit formats on <= CIK

From: Nicolai Hähnle The same PS epilog workaround as for 8-bit integer formats is required, since the CB doesn't do clamping. Fixes GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels*. Cc: mesa-sta...@lists.freedesktop.org ---

[Mesa-dev] [PATCH 1/2] radeonsi: handle MultiDrawIndirect in si_get_draw_start_count

From: Nicolai Hähnle Also handle the GL_ARB_indirect_parameters case where the count itself is in a buffer. Use transfers rather than mapping the buffers directly. This anticipates the possibility that the buffers are sparse (once ARB_sparse_buffer is implemented), in

Re: [Mesa-dev] [PATCH] anv/query: clflush the bo map on non-LLC platforms

On 18/02/17 21:32, Jason Ekstrand wrote: Found by inspection Cc: "13.0 17.0" --- src/intel/vulkan/anv_query.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/anv_query.c b/src/intel/vulkan/anv_query.c index 293257b..d674e83 100644 ---

Re: [Mesa-dev] [PATCH 1/4] genxml: Make MI_STORE_DATA_IMM more consistent

I have a tiny suggestion below and also one on patch 2. Regardless, this series is : Reviewed-by: Lionel Landwerlin On 18/02/17 23:59, Jason Ekstrand wrote: --- src/intel/genxml/gen7.xml | 2 +- src/intel/genxml/gen75.xml | 2 +- 2 files changed, 2

Re: [Mesa-dev] [PATCH 2/4] anv/query: Perform CmdResetQueryPool on the GPU

On 18/02/17 23:59, Jason Ekstrand wrote: This fixes a some rendering corruption in The Talos Principle Cc: "13.0 17.0" --- src/intel/vulkan/anv_query.c | 22 -- src/intel/vulkan/genX_cmd_buffer.c | 27 +++ 2

Re: [Mesa-dev] [PATCH] mesa/blit: only error when the stencil and depth bits do not match (v3)

NVM this patch, the error was caused by an issue in Wine. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 97921] Mesa-only glBlitFrameBuffer error

https://bugs.freedesktop.org/show_bug.cgi?id=97921 Maxqia changed: What|Removed |Added Resolution|INVALID |NOTOURBUG -- You are

[Mesa-dev] [Bug 97921] Mesa-only glBlitFrameBuffer error

https://bugs.freedesktop.org/show_bug.cgi?id=97921 --- Comment #5 from Maxqia --- Sorry, Nevermind. This was an issue with Wine... -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the

[Mesa-dev] [Bug 97921] Mesa-only glBlitFrameBuffer error

https://bugs.freedesktop.org/show_bug.cgi?id=97921 Maxqia changed: What|Removed |Added Status|NEW |RESOLVED

Re: [Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

On 02/20/2017 09:15 PM, Edward O'Callaghan wrote: > The name has become a little misleading now that it applies > to both r600g and radeonsi. > > V.2: Michel Dänzer - R600_DEBUG must continue to work. > > Signed-off-by: Edward O'Callaghan > --- >

[Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

The name has become a little misleading now that it applies to both r600g and radeonsi. V.2: Michel Dänzer - R600_DEBUG must continue to work. Signed-off-by: Edward O'Callaghan --- src/gallium/drivers/r600/r600_pipe.c | 1 +

Re: [Mesa-dev] [PATCH] android: define HAVE_DL_ITERATE_PHDR for build-id code

Reviewed-by: Tapani Pälli On 02/19/2017 12:10 AM, Mauro Rossi wrote: Required due to d4fa083 "util: Add utility build-id code." to avoid following build error and warnings: external/mesa/src/intel/vulkan/anv_device.c:60:32: error: incompatible integer to pointer

Re: [Mesa-dev] [PATCH] android: glsl: build shader cache sources

On 02/19/2017 03:06 AM, Timothy Arceri wrote: I would have thought this commit [1] should have fixed it for android as weel as scons. [1] https://cgit.freedesktop.org/mesa/mesa/commit/?id=172c48cc15e2a7b42a7de8ff9164ad8733155667 Problem is that we have ENABLE_SHADER_CACHE on because it is

[Mesa-dev] [PATCH 3/5] radv: Special case the initial preamble.

For flushing we don't want to flush every third IB. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 6 +++--- src/amd/vulkan/radv_radeon_winsys.h | 3 ++- src/amd/vulkan/radv_wsi.c | 2 +-

[Mesa-dev] [PATCH 2/5] radv: Split emitting the cache flush out.

So that we can use it without a cmd_buffer. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/si_cmd_buffer.c | 141 ++--- 1 file changed, 77 insertions(+), 64 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c

[Mesa-dev] [PATCH 1/5] radv: Free empty_cs on device destruction.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 7900ece9c89..4ec62a73585 100644 --- a/src/amd/vulkan/radv_device.c +++

[Mesa-dev] [PATCH 5/5] radv: Don't flush at the start of a command buffer.

The preamble flushes now and the rest is the responsibility of the app. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 15 --- 1 file changed, 15 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [PATCH 4/5] radv: Flush in the initial preamble CS.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 224 + src/amd/vulkan/radv_private.h | 12 ++- src/amd/vulkan/si_cmd_buffer.c | 2 +- 3 files changed, 148 insertions(+), 90 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] radeonsi, r600g: Rename 'R600_DEBUG' -> 'RADEON_DEBUG'

On 20/02/17 05:42 PM, Edward O'Callaghan wrote: > The name has become a little misleading now that it applies > to both r600g and radeonsi. R600_DEBUG must continue to work. Making RADEON_DEBUG work as well may be a good idea though. -- Earthling Michel Dänzer |

[Mesa-dev] [PATCH] radeonsi, r600g: Rename 'R600_DEBUG' -> 'RADEON_DEBUG'

The name has become a little misleading now that it applies to both r600g and radeonsi. Signed-off-by: Edward O'Callaghan --- src/gallium/drivers/r600/r600_pipe.c | 2 +- src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-

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