Re: [Mesa-dev] [PATCH 15/30] i965/miptree: Add new entrypoints for resolve management

On Fri 26 May 2017, Jason Ekstrand wrote: > This commit adds a new unified interface for doing resolves. The basic > format is that, prior to any surface access such as texturing or > rendering, you call intel_miptree_prepare_access. If the surface was > written, you call

Re: [Mesa-dev] [PATCH 16/30] i965: Use the new resolve function for several simple cases

On Fri 26 May 2017, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_context.c| 2 +- > src/mesa/drivers/dri/i965/intel_blit.c | 14 -- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +--- > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18

Re: [Mesa-dev] [PATCH 15/30] i965/miptree: Add new entrypoints for resolve management

On Fri 26 May 2017, Jason Ekstrand wrote: > This commit adds a new unified interface for doing resolves. The basic > format is that, prior to any surface access such as texturing or > rendering, you call intel_miptree_prepare_access. If the surface was > written, you call

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue, Jun 6, 2017 at 10:11 PM, Chad Versace wrote: > On Tue 06 Jun 2017, Jason Ekstrand wrote: > > On Tue, Jun 6, 2017 at 6:00 PM, Chad Versace wrote: > > > > > On Tue 06 Jun 2017, Jason Ekstrand wrote: > > > > On Tue, Jun 6, 2017 at 1:32 PM, Jason

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue 06 Jun 2017, Jason Ekstrand wrote: > On Tue, Jun 6, 2017 at 6:00 PM, Chad Versace wrote: > > > On Tue 06 Jun 2017, Jason Ekstrand wrote: > > > On Tue, Jun 6, 2017 at 1:32 PM, Jason Ekstrand > > wrote: > > > > > > > On Tue, Jun 6, 2017 at 1:22 PM,

Re: [Mesa-dev] [PATCH 04/10] i965/blorp: Inline gen6_blorp_exec

On Tue, Jun 6, 2017 at 10:54 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Tue, Jun 06, 2017 at 08:35:06PM +0300, Pohjolainen, Topi wrote: > > On Mon, Jun 05, 2017 at 05:55:39PM -0700, Jason Ekstrand wrote: > > > --- > > > src/mesa/drivers/dri/i965/brw_blorp.c | 29 >

[Mesa-dev] [PATCH 08/11] i965/blorp: Do a depth flush/stall prior to HiZ operations

Without this stall, the test group ES3-CTS.functional.fbo.msaa.\* hangs about 1 out of every 2 or 3 times on my Sky Lake GT3 laptop. With the flush and stall, I can run it 6 times in a row without a hang. Cc: "17.1" --- src/mesa/drivers/dri/i965/brw_blorp.c |

[Mesa-dev] [PATCH 07/11] i965/blorp: Set no_depth_or_stencil correctly

--- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index 3451d71..0de3038 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++

[Mesa-dev] [PATCH 10/11] i965: Set step_rate == 0 for interleaved vertex buffers

Before, we weren't setting step rate so we got whatever old value happened to be lying around. This can lead to some interesting rendering errors. In particular, if you run the OpenGL ES CTS with dEQP-GLES3.functional.instanced.types.mat2x4 immediately followed by one of the

[Mesa-dev] [PATCH 11/11] i965: Use blorp for depth/stencil clears on gen6+

--- src/mesa/drivers/dri/i965/brw_blorp.c | 106 ++ src/mesa/drivers/dri/i965/brw_blorp.h | 4 ++ src/mesa/drivers/dri/i965/brw_clear.c | 6 ++ 3 files changed, 116 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH 05/11] i965: Remove some of the remnants of meta

--- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_wm.c| 2 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h

[Mesa-dev] [PATCH 04/11] intel/isl: Properly set SeparateStencilBufferEnable on gen5-6

On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. --- src/intel/isl/isl_emit_depth_stencil.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 06/11] i965: Remove some unneeded fields from brw_context

--- src/mesa/drivers/dri/i965/brw_context.h | 12 1 file changed, 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 3f4b86a..965c7b9 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++

[Mesa-dev] [PATCH 09/11] i965: Disable the interleaved vertex optimization when instancing

Instance divisor is a property of the vertex buffer and not the vertex element so if we ever see anything other than 0, bail. Cc: "17.1" --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff

[Mesa-dev] [PATCH 01/11] i965/blorp: Set aux_usage to NONE for miplevels without HiZ

--- src/mesa/drivers/dri/i965/brw_blorp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 28be620..763ce05 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH 00/11] i965: Use BLORP for depth/stencil clears

This little series switches the GL driver to use BLORP for depth and stencil clears. BLORP has had depth/stencil clear support ever since we started using it in the Vulkan driver but we didn't hook it up in GL because of a few very hard-to-debug CTS fails. Patches 10 takes care of those and we

[Mesa-dev] [PATCH 02/11] mesa: Add a BUFFER_BITS mask for depth+stencil

--- src/mesa/main/mtypes.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 7ec0123..d77c26a 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -187,6 +187,9 @@ typedef enum BUFFER_BIT_COLOR6

[Mesa-dev] [PATCH 03/11] i965/miptree: Choose the stencil layout in miptree_create_layout

This ensures that we get the correct layout for all stencil buffers, not just those which are created as separate stencil for a depth buffer. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] intel: Fix broxton 2x6 way size computation

Tested-by: Mark Janes Anuj Phogat writes: > This patch is undoing the changes to way size computation > in broxton 2x6, made by below commit: > > Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 > Author: Anuj Phogat >

[Mesa-dev] [PATCH] radv: optimise compute dispatch to avoid looking up the sgpr repeatedly.

From: Dave Airlie Same as we did for draw dispatch and vertex sgprs. --- src/amd/vulkan/radv_cmd_buffer.c | 23 +-- src/amd/vulkan/radv_pipeline.c | 6 ++ src/amd/vulkan/radv_private.h| 4 3 files changed, 19 insertions(+), 14

[Mesa-dev] [PATCH 1/2] radv: move the pipeline static pieces of ia multi vgt calcs to pipeline.

From: Dave Airlie This shifts a bunch of the pipeline specific calcs into pipeline creation. This should allow better optimising of the multi vgt calcs --- src/amd/vulkan/radv_pipeline.c | 62 ++ src/amd/vulkan/radv_private.h | 6

[Mesa-dev] [PATCH 2/2] radv: only update ia_multi_vgt_param if something changes.

From: Dave Airlie This in theory should reduce the number of calculations for this register per draw. --- src/amd/vulkan/radv_private.h | 2 ++ src/amd/vulkan/si_cmd_buffer.c | 11 +++ 2 files changed, 13 insertions(+) diff --git a/src/amd/vulkan/radv_private.h

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue, Jun 6, 2017 at 6:00 PM, Chad Versace wrote: > On Tue 06 Jun 2017, Jason Ekstrand wrote: > > On Tue, Jun 6, 2017 at 1:32 PM, Jason Ekstrand > wrote: > > > > > On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace > > > > wrote:

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue, Jun 6, 2017 at 5:41 PM, Chad Versace wrote: > On Tue 06 Jun 2017, Jason Ekstrand wrote: > > On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace > > wrote: > > > > > On Fri 26 May 2017, Jason Ekstrand wrote: > > > > This enum describes all of the

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue 06 Jun 2017, Jason Ekstrand wrote: > On Tue, Jun 6, 2017 at 1:32 PM, Jason Ekstrand wrote: > > > On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace > > wrote: > > > >> On Fri 26 May 2017, Jason Ekstrand wrote: > > How about a section after the

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue 06 Jun 2017, Jason Ekstrand wrote: > On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace > wrote: > > > On Fri 26 May 2017, Jason Ekstrand wrote: > > > This enum describes all of the states that a auxiliary compressed > > > surface can have. All of the states as well

Re: [Mesa-dev] [PATCH 3/4] configure.ac: remove unused Android specifics

On Mon 05 Jun 2017, Emil Velikov wrote: > From: Emil Velikov > > The HAVE_ANDROID conditional has been unused as of commit 51accecce77 > ("mesa/dri: always link against shared glapi") and with that one gone we > no longer need the host detection. > > Cc: Chad Versace

[Mesa-dev] [PATCH] radv: don't do divide in si_get_ia_multi_vgt_param unless needed.

From: Dave Airlie We only need the num_prims for instanced and geometry cases. Bas, I know you've got some more ideas for this area, so feel free to include this or do it better. --- src/amd/vulkan/si_cmd_buffer.c | 12 1 file changed, 8 insertions(+), 4

Re: [Mesa-dev] [PATCH v2 1/1] radeonsi: Use libdrm to get chipset name

Reviewed-by: Marek Olšák Marek On Wed, Jun 7, 2017 at 12:21 AM, Samuel Li wrote: > v2: Add a func pointer to radeon_winsys to support radeon later. > > Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f > Signed-off-by: Samuel Li >

Re: [Mesa-dev] [PATCH 1/3] ac/nir: mark some arguments const

This series is Reviewed-by: Bas Nieuwenhuizen On Wed, Jun 7, 2017 at 1:31 AM, Grazvydas Ignotas wrote: > Most functions are only inspecting nir, so nir related arguments can be > marked const. Some more can be done if/when some nir changes are >

Re: [Mesa-dev] [PATCH 1/3] radv: rename and make global some functions.

This series is Reviewed-by: Bas Nieuwenhuizen On Wed, Jun 7, 2017 at 1:18 AM, Dave Airlie wrote: > From: Dave Airlie > > I want to use these in the pipeline setup stage. > > Signed-off-by: Dave Airlie > ---

Re: [Mesa-dev] [PATCH] radv: move chip_class extraction down further.

On Wed, Jun 7, 2017 at 1:35 AM, Dave Airlie wrote: > From: Dave Airlie > > This seems to matter here in a profile, without this we spend a lot > more time exiting this function with no flush bits. > > Signed-off-by: Dave Airlie > --- >

Re: [Mesa-dev] [PATCH] intel: Fix broxton 2x6 way size computation

On Tuesday, June 6, 2017 4:34:36 PM PDT Anuj Phogat wrote: > This patch is undoing the changes to way size computation > in broxton 2x6, made by below commit: > > Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 > Author: Anuj Phogat > i965: Simplify l3 way size

Re: [Mesa-dev] [PATCH v2 58/64] radeonsi: track use of bindless samplers/images from tgsi_shader_info

On Tue, May 30, 2017 at 10:36 PM, Samuel Pitoiset wrote: > This adds some new helper functions to know if the current draw > call (or dispatch compute) is using bindless samplers/images, > based on TGSI analysis. > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v2 56/64] radeonsi: decompress resident textures/images before graphics/compute

On Wed, Jun 7, 2017 at 1:27 AM, Marek Olšák wrote: > On Tue, May 30, 2017 at 10:36 PM, Samuel Pitoiset > wrote: >> Similar to the existing decompression code path except that it >> loops over the list of resident textures/images. >> >> v2: - store

Re: [Mesa-dev] [PATCH 4/5] mesa: add scissor() and scissor_array() helpers

On 07/06/17 05:58, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/mesa/main/scissor.c | 57 - 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/src/mesa/main/scissor.c

[Mesa-dev] [PATCH] intel: Fix broxton 2x6 way size computation

This patch is undoing the changes to way size computation in broxton 2x6, made by below commit: Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 Author: Anuj Phogat i965: Simplify l3 way size computations By making use of l3_banks field in gen_device_info struct

[Mesa-dev] [PATCH] radv: move chip_class extraction down further.

From: Dave Airlie This seems to matter here in a profile, without this we spend a lot more time exiting this function with no flush bits. Signed-off-by: Dave Airlie --- src/amd/vulkan/si_cmd_buffer.c | 15 ++- 1 file changed, 10

[Mesa-dev] [PATCH 1/3] ac/nir: mark some arguments const

Most functions are only inspecting nir, so nir related arguments can be marked const. Some more can be done if/when some nir changes are accepted. Signed-off-by: Grazvydas Ignotas --- does *not* depend on the nir patch src/amd/common/ac_nir_to_llvm.c | 61

[Mesa-dev] [PATCH 2/3] ac/nir: convert several ifs to a switch

Also solve "outinfo may be used uninitialized" warning by putting in an unreachable(). Signed-off-by: Grazvydas Ignotas --- src/amd/common/ac_nir_to_llvm.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] radv/meta: remove an unused variable

Trivial. Signed-off-by: Grazvydas Ignotas --- src/amd/vulkan/radv_meta_clear.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index f4cb787..d7e7c5b 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++

Re: [Mesa-dev] [PATCH v2 13/23] mesa: add KHR_no_error support for glBlitFramebuffer()

1-13: Reviewed-by: Timothy Arceri On 06/06/17 07:44, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/mapi/glapi/gen/ARB_framebuffer_object.xml | 2 +- src/mesa/main/blit.c | 15 +++

Re: [Mesa-dev] [PATCH v2] mesa: wrap blit_framebuffer() into blit_framebuffer_err()

Thanks. Reviewed-by: Timothy Arceri On 07/06/17 05:57, Samuel Pitoiset wrote: Also add ALWAYS_INLINE to blit_framebuffer(). v2: - use correct parameters Signed-off-by: Samuel Pitoiset --- src/mesa/main/blit.c | 34

Re: [Mesa-dev] [PATCH v2 56/64] radeonsi: decompress resident textures/images before graphics/compute

On Tue, May 30, 2017 at 10:36 PM, Samuel Pitoiset wrote: > Similar to the existing decompression code path except that it > loops over the list of resident textures/images. > > v2: - store pipe_sampler_view instead of si_sampler_view > > Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH] nir: make various getters take const pointers

This will allow to constify other things. Signed-off-by: Grazvydas Ignotas --- src/compiler/nir/nir.h | 25 + src/compiler/nir/nir_lower_io.c | 2 +- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir.h

[Mesa-dev] XDC 2017 : Call for paper

Hello, I have the pleasure to announce that the X.org Developer Conference 2017 will be held in Mountain View, California from September 20th to September 22nd. The venue is located at the Googleplex. The official page for the event is http://www.x.org/wiki/Events/XDC2017 while the call for

[Mesa-dev] [PATCH 3/3] radv: move lots of index related things into the bind.

From: Dave Airlie This just moves lots of stuff to the bind stage rather than dealing with it in the draw stage. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_cmd_buffer.c | 29 - src/amd/vulkan/radv_private.h| 4

[Mesa-dev] [PATCH 1/3] radv: rename and make global some functions.

From: Dave Airlie I want to use these in the pipeline setup stage. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_cmd_buffer.c | 24 src/amd/vulkan/radv_private.h| 5 + 2 files changed, 17 insertions(+), 12

[Mesa-dev] [PATCH 2/3] radv: move calculating the vertex sgpr to the pipeline.

From: Dave Airlie There is no need to calculate this at draw time. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_cmd_buffer.c | 63 ++-- src/amd/vulkan/radv_pipeline.c | 10 +++

Re: [Mesa-dev] [PATCH 2/2] mesa: inline update_image_transfer_state() into _mesa_update_pixel()

With Ian's suggestion series: Reviewed-by: Timothy Arceri On 07/06/17 06:58, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/mesa/main/pixel.c | 19 +-- 1 file changed, 5 insertions(+), 14 deletions(-) diff

[Mesa-dev] [PATCH v2 1/1] radeonsi: Use libdrm to get chipset name

v2: Add a func pointer to radeon_winsys to support radeon later. Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f Signed-off-by: Samuel Li --- src/gallium/drivers/radeon/r600_pipe_common.c | 11 ++- src/gallium/drivers/radeon/radeon_winsys.h| 2 ++

Re: [Mesa-dev] [PATCH 1/6] mesa: Add _mesa_format_fallback_rgba_to_rgbx()

Quoting Chad Versace (2017-06-06 15:11:18) > On Tue 06 Jun 2017, Dylan Baker wrote: > > Quoting Chad Versace (2017-06-06 13:36:55) > > > The new function takes a mesa_format and, if the format is an alpha > > > format with a non-alpha variant, returns the non-alpha format. > > > Otherwise, it

Re: [Mesa-dev] [PATCH 2/2] mesa: inline update_image_transfer_state() into _mesa_update_pixel()

On 06/06/2017 01:58 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/mesa/main/pixel.c | 19 +-- > 1 file changed, 5 insertions(+), 14 deletions(-) > > diff --git a/src/mesa/main/pixel.c b/src/mesa/main/pixel.c > index

Re: [Mesa-dev] [PATCH mesa] tree-wide: remove trailing backslash

On 06/01/2017 06:48 AM, Eric Engestrom wrote: > Simple search for a backslash followed by two newlines. > If one of the newlines were to be removed, this would cause issues, so > let's just remove these trailing backslashes. > > Signed-off-by: Eric Engestrom > --- > >

Re: [Mesa-dev] [PATCH 5/5] r100: Silence numerous unused this or that warnings

On 06/01/2017 09:26 AM, Marek Olšák wrote: > For the series: > > Reviewed-by: Marek Olšák > > About your r100-r200 coding style question, I don't have a specific > answer. It's up to you what you wanna do with it. Okay. I think I'm going to just start using the same style

Re: [Mesa-dev] [PATCH 1/6] mesa: Add _mesa_format_fallback_rgba_to_rgbx()

On Tue 06 Jun 2017, Dylan Baker wrote: > Quoting Chad Versace (2017-06-06 13:36:55) > > The new function takes a mesa_format and, if the format is an alpha > > format with a non-alpha variant, returns the non-alpha format. > > Otherwise, it returns the original format. > > > > Example: > >

Re: [Mesa-dev] [PATCH] svga: fix git_sha1.h include path in Android.mk

And here is last (v3) version tested by building nougat-x86 >From 052df48ae71b82b04ed8f634101d0ec919b497e5 Mon Sep 17 00:00:00 2001 From: Mauro Rossi Date: Tue, 6 Jun 2017 23:15:05 +0200 Subject: [PATCH 1/5] svga: fix git_sha1.h include path in Android.mk (v3) Adds

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue, Jun 6, 2017 at 1:32 PM, Jason Ekstrand wrote: > On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace > wrote: > >> On Fri 26 May 2017, Jason Ekstrand wrote: >> > This enum describes all of the states that a auxiliary compressed >> > surface can

Re: [Mesa-dev] [PATCH 4/4] nir: add ARB_shader_ballot and ARB_shader_group_vote instructions

On Tue, Jun 6, 2017 at 1:48 PM, Connor Abbott wrote: > On Tue, Jun 6, 2017 at 1:45 PM, Jason Ekstrand wrote: >> >> >> On Mon, Jun 5, 2017 at 9:52 PM, Jason Ekstrand wrote: >>> >>> On Mon, Jun 5, 2017 at 6:37 PM, Connor Abbott

Re: [Mesa-dev] [PATCH 2/6] i965: Add a RGBX->RGBA fallback for glEGLImageTextureTarget2D()

Hi Chad, On 6 June 2017 at 21:36, Chad Versace wrote: > @@ -254,8 +255,22 @@ create_mt_for_dri_image(struct brw_context *brw, > struct gl_context *ctx = >ctx; > struct intel_mipmap_tree *mt; > uint32_t draw_x, draw_y; > + mesa_format format =

Re: [Mesa-dev] [PATCH v2 52/64] radeonsi: implement ARB_bindless_texture

On Tue, May 30, 2017 at 10:36 PM, Samuel Pitoiset wrote: > This implements the Gallium interface. Decompression of resident > textures/images will follow in the next patches. > > v2: - fix a memleak related to util_copy_image_view() > - remove "texture" parameter

Re: [Mesa-dev] [PATCH v2 51/64] radeonsi: add a slab allocator for bindless descriptors

On Tue, May 30, 2017 at 10:36 PM, Samuel Pitoiset wrote: > For each texture/image handles, we need to allocate a new > buffer for the bindless descriptor. But when the number of > buffers added to the current CS becomes high, the overhead > in the winsys (and in the

[Mesa-dev] [PATCH 2/2] mesa: inline update_image_transfer_state() into _mesa_update_pixel()

Signed-off-by: Samuel Pitoiset --- src/mesa/main/pixel.c | 19 +-- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/src/mesa/main/pixel.c b/src/mesa/main/pixel.c index 218e9fdd6b..a3f04d5688 100644 --- a/src/mesa/main/pixel.c +++

[Mesa-dev] [PATCH 1/2] mesa: remove useless check in _mesa_update_pixel()

The only caller is _mesa_update_state_locked() which already checks if _NEW_PIXEL is set before calling _mesa_update_pixel(). Signed-off-by: Samuel Pitoiset --- src/mesa/main/pixel.c | 5 ++--- src/mesa/main/pixel.h | 2 +- src/mesa/main/state.c | 2 +- 3 files

[Mesa-dev] [Bug 95346] Stellaris - Black/super dark planets

https://bugs.freedesktop.org/show_bug.cgi?id=95346 nikolai.va...@gmail.com changed: What|Removed |Added CC||nikolai.va...@gmail.com --

Re: [Mesa-dev] [PATCH] svga: fix git_sha1.h include path in Android.mk

2017-06-05 2:29 GMT+02:00 Emil Velikov : > On 4 June 2017 at 22:47, Mauro Rossi wrote: >> 2017-05-29 14:30 GMT+02:00 Emil Velikov : >>> On 26 May 2017 at 16:15, Mauro Rossi wrote: Fixes the

Re: [Mesa-dev] [PATCH 1/6] mesa: Add _mesa_format_fallback_rgba_to_rgbx()

Quoting Chad Versace (2017-06-06 13:36:55) > The new function takes a mesa_format and, if the format is an alpha > format with a non-alpha variant, returns the non-alpha format. > Otherwise, it returns the original format. > > Example: > input -> output > > // Fallback exists >

Re: [Mesa-dev] [PATCH 4/4] nir: add ARB_shader_ballot and ARB_shader_group_vote instructions

On Tue, Jun 6, 2017 at 1:45 PM, Jason Ekstrand wrote: > > > On Mon, Jun 5, 2017 at 9:52 PM, Jason Ekstrand wrote: >> >> On Mon, Jun 5, 2017 at 6:37 PM, Connor Abbott wrote: >>> >>> I pushed a v2 at >>>

Re: [Mesa-dev] [PATCH 4/4] nir: add ARB_shader_ballot and ARB_shader_group_vote instructions

On Mon, Jun 5, 2017 at 9:52 PM, Jason Ekstrand wrote: > On Mon, Jun 5, 2017 at 6:37 PM, Connor Abbott wrote: > >> I pushed a v2 at >> https://cgit.freedesktop.org/~cwabbott0/mesa/log/?h=nir-divergence-v2. >> I'm not sure if I like this version better,

[Mesa-dev] [PATCH 0/6] i965: Add RGBX, RGBA configs, even on gen9

More patches to break your formats... again ;) The Android framework requires support for EGLConfigs with HAL_PIXEL_FORMAT_RGBX_ and HAL_PIXEL_FORMAT_RGBA_. This prevents Chrome OS from updating its Android drivers, because earlier this year Intel disabled all rgbx formats for gen >=9 in

[Mesa-dev] [PATCH 3/6] i965: Rename some vague format members of brw_context

I'm swimming in a vortex of formats. Mesa formats, isl formats, DRI formats, GL formats, etc. It's easy to misinterpret the following brw_context members unless you've recently read their definition. In upcoming patches, I change them from embedded arrays to simple pointers; after that, even

[Mesa-dev] [PATCH 2/6] i965: Add a RGBX->RGBA fallback for glEGLImageTextureTarget2D()

This enables support for importing RGBX EGLImage textures on Skylake. Chrome OS needs support for RGBX EGLImage textures because because the Android framework produces HAL_PIXEL_FORMAT_RGBX winsys surfaces, which the Chrome OS compositor consumes as dma_bufs. On hardware for which

[Mesa-dev] [PATCH 5/6] i965: Move brw_context format arrays to intel_screen

This allows us to query the driver's supported formats in i965's DRI code, where often there is available a DRIscreen but no GL context. To reduce diff noise, this patch does not completely remove brw_context's format arrays. It just redeclares them as pointers which point to the arrays in

[Mesa-dev] [PATCH 6/6] i965/dri: Support R8G8B8A8 and R8G8B8X8 configs

The Android framework requires support for EGLConfigs with HAL_PIXEL_FORMAT_RGBX_ and HAL_PIXEL_FORMAT_RGBA_. Even though all RGBX formats are disabled on gen9 by brw_surface_formats.c, the new configs work correctly on Broxton thanks to _mesa_format_fallback_rgbx_to_rgba(). On GLX, this

Re: [Mesa-dev] [PATCH 13/30] i965: Combine render target resolve code

On Tue, Jun 6, 2017 at 12:54 PM, Chad Versace wrote: > There's a patch on your branch I didn't see on mesa-dev. >Subject: i965: Be a bit more conservative about certain resolves > It has my r-b. > > I have comments on this patch... > > On Fri 26 May 2017, Jason

[Mesa-dev] [PATCH 4/6] i965/dri: Add intel_screen param to intel_create_winsys_renderbuffer

The param is currently unused. It will later be used it to support R8G8B8X8 EGLConfigs on Skylake. --- src/mesa/drivers/dri/i965/intel_fbo.c| 8 +--- src/mesa/drivers/dri/i965/intel_fbo.h| 6 -- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 3 files changed, 17

[Mesa-dev] [PATCH 1/6] mesa: Add _mesa_format_fallback_rgba_to_rgbx()

The new function takes a mesa_format and, if the format is an alpha format with a non-alpha variant, returns the non-alpha format. Otherwise, it returns the original format. Example: input -> output // Fallback exists MESA_FORMAT_R8G8B8X8_UNORM -> MESA_FORMAT_R8G8B8A8_UNORM

[Mesa-dev] [PATCH 3/6] radv: Add early exit for cache flushes.

No sense checking each bit separately in the common case of none being set. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/si_cmd_buffer.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c

[Mesa-dev] [PATCH 4/6] radv: Move pipeline stuff from flush_state to emit_graphics_pipeline.

No functional changes. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 21 ++--- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

[Mesa-dev] [PATCH 1/6] radv: Don't use a divide by index_size.

Divides are pretty slow, and this is in the hot path of a draw. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [PATCH 6/6] radv: Remove SI num RB override for occlusion queries.

radeonsi doesn't have it anymore either. Signed-off-by: Bas Nieuwenhuizen Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_query.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_query.c

[Mesa-dev] [PATCH 5/6] radv: Split out updating the vertex descriptors.

Simple refactor. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

[Mesa-dev] [PATCH 2/6] radv: Remove vertex_descriptors_dirty.

Redundant. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 4 +--- src/amd/vulkan/radv_private.h| 1 - 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Tue, Jun 6, 2017 at 1:22 PM, Chad Versace wrote: > On Fri 26 May 2017, Jason Ekstrand wrote: > > This enum describes all of the states that a auxiliary compressed > > surface can have. All of the states as well as normative language for > > referring to each of the

Re: [Mesa-dev] [PATCH 14/30] intel/isl: Add an enum for describing auxiliary compression state

On Fri 26 May 2017, Jason Ekstrand wrote: > This enum describes all of the states that a auxiliary compressed > surface can have. All of the states as well as normative language for > referring to each of the compression operations is provided in the > truly colossal comment for the new

[Mesa-dev] [PATCH 2/3] mesa: make use of NewScissorRect driver flags

Signed-off-by: Samuel Pitoiset --- src/mesa/main/scissor.c | 2 ++ src/mesa/state_tracker/st_context.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/scissor.c b/src/mesa/main/scissor.c index 808cb4d5fe..fb7cf0ebb2

[Mesa-dev] [PATCH 1/3] mesa: add gl_driver_flags::NewScissor{Rect, Test}

_NEW_SCISSOR mesa flag is set when a scissor test is enabled/disabled or when a new rectangle is defined. However, it triggers too much changes in the state tracker. Actually, ST_NEW_RASTERIZER should only be called when a scissor test is enabled/disabled, while ST_NEW_SCISSOR should be called in

Re: [Mesa-dev] [PATCH] i965: Don't try to resolve CCS with MESA_FORMAT_NONE.

On Sun 04 Jun 2017, Jason Ekstrand wrote: > On June 4, 2017 5:36:57 PM Kenneth Graunke wrote: > > > On Sunday, June 4, 2017 3:27:04 PM PDT Jason Ekstrand wrote: > > > How does the texture even have a format of MESA_FORMAT_NONE? That seems > > > like the first question to

[Mesa-dev] [PATCH 3/3] mesa: make use of NewScissorTest driver flags

Signed-off-by: Samuel Pitoiset --- src/mesa/main/enable.c | 2 ++ src/mesa/state_tracker/st_context.c | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c index ef278a318a..394c9e13c4

[Mesa-dev] [PATCH 5/5] mesa: add KHR_no_error support for glScissor*()

Signed-off-by: Samuel Pitoiset --- src/mapi/glapi/gen/ARB_viewport_array.xml | 6 +++--- src/mapi/glapi/gen/gl_API.xml | 2 +- src/mesa/main/scissor.c | 31 +++ src/mesa/main/scissor.h | 13

[Mesa-dev] [PATCH 4/5] mesa: add scissor() and scissor_array() helpers

Signed-off-by: Samuel Pitoiset --- src/mesa/main/scissor.c | 57 - 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/src/mesa/main/scissor.c b/src/mesa/main/scissor.c index 5cf02168bd..d94663c6e4 100644 ---

[Mesa-dev] [PATCH 3/5] mesa: rename ScissorIndexed() to scissor_indexed_err()

And move GET_CURRENT_CONTEXT() into the APIENTRY calls for consistency. Signed-off-by: Samuel Pitoiset --- src/mesa/main/scissor.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mesa/main/scissor.c b/src/mesa/main/scissor.c

[Mesa-dev] [PATCH 1/5] mesa: make _mesa_scissor_bounding_box() static

Signed-off-by: Samuel Pitoiset --- src/mesa/main/framebuffer.c | 10 +- src/mesa/main/framebuffer.h | 4 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c index 5069d37394..993cd37137

[Mesa-dev] [PATCH 2/5] mesa: use _mesa_set_scissor() in ScissorIndexed()

Signed-off-by: Samuel Pitoiset --- src/mesa/main/scissor.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mesa/main/scissor.c b/src/mesa/main/scissor.c index 13934f9ca2..0dd956c9e3 100644 --- a/src/mesa/main/scissor.c +++

[Mesa-dev] [PATCH v2] mesa: wrap blit_framebuffer() into blit_framebuffer_err()

Also add ALWAYS_INLINE to blit_framebuffer(). v2: - use correct parameters Signed-off-by: Samuel Pitoiset --- src/mesa/main/blit.c | 34 +- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/src/mesa/main/blit.c

Re: [Mesa-dev] [PATCH 13/30] i965: Combine render target resolve code

There's a patch on your branch I didn't see on mesa-dev. Subject: i965: Be a bit more conservative about certain resolves It has my r-b. I have comments on this patch... On Fri 26 May 2017, Jason Ekstrand wrote: > We have two different bits of resolve code for render targets: one in >

Re: [Mesa-dev] [PATCH 12/30] i965/blorp: Move MCS allocation earlier for clears

Patches 10-12 are Reviewed-by: Chad Versace ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 08/30] i965: Inline renderbuffer_att_set_needs_depth_resolve

On Fri 02 Jun 2017, Jason Ekstrand wrote: > On Fri, Jun 2, 2017 at 2:41 PM, Chad Versace <[1]chadvers...@chromium.org> > wrote: > > I believe you could simplify this by eliminating the 'else' branch. As > long as depth_irb->layer_count == 1 for non-layered renderbuffers (and > I

Re: [Mesa-dev] [PATCH 8/8] radeonsi: don't update dependent states if it has no effect

I really like the idea. :-) Though, I have two general comments: 1) I think it would be better to introduce some sort of compare helper functions for the different state changes. Also, for correctness it might be safer to do the opposite checks (if someone introduce a new field and forget to

Re: [Mesa-dev] [PATCH 04/10] i965/blorp: Inline gen6_blorp_exec

On Tue, Jun 06, 2017 at 08:35:06PM +0300, Pohjolainen, Topi wrote: > On Mon, Jun 05, 2017 at 05:55:39PM -0700, Jason Ekstrand wrote: > > --- > > src/mesa/drivers/dri/i965/brw_blorp.c | 29 +++-- > > 1 file changed, 11 insertions(+), 18 deletions(-) > > Patches 1-4: > >

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