[Mesa-dev] [PATCH v3 6/7] ac: handle subgroup intrinsics

--- src/amd/common/ac_nir_to_llvm.c | 69 - 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7c2bd5c0cc..3a3aa72988 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/

[Mesa-dev] [PATCH v3 4/7] ac: make ballot and umsb capable of 64bit inputs

Reviewed-by: Marek Olšák --- src/amd/common/ac_llvm_build.c | 34 +- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 32d8a02f56..2fb8aeaac6 100644 --- a/src/amd/common/ac_llvm_buil

[Mesa-dev] [PATCH v3 0/7] radv: add support for new subgroup capabilities

Third version of the series: - rebased to master - lower_shuffle_to_32bit now only lowers shuffles and nothing else - removed constant values from quad intrinsics Previous Version can be found here https://lists.freedesktop.org/archives/mesa-dev/2018-March/189116.html Daniel Schürmann (7): nir:

[Mesa-dev] [PATCH v3 7/7] radv: enable subgroup capabilities

--- src/amd/vulkan/radv_device.c | 10 -- src/amd/vulkan/radv_shader.c | 7 ++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4fc7392e65..e50b661cac 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/

[Mesa-dev] [PATCH v3 1/7] nir: adjust subgroups instructions for 64bit ballot sizes

--- src/compiler/nir/nir_lower_subgroups.c | 5 ++--- src/compiler/nir/nir_opcodes.py| 12 ++-- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/compiler/nir/nir_lower_subgroups.c b/src/compiler/nir/nir_lower_subgroups.c index 0d3c83b795..9dc7be7947 100644 --- a

[Mesa-dev] [PATCH v3 2/7] nir/spirv: Fix warning and add missing breaks.

--- src/compiler/spirv/spirv_to_nir.c | 2 ++ src/compiler/spirv/vtn_subgroup.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 78c1e9ff59..28274311c2 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compil

Re: [Mesa-dev] [PATCH] mesa: fix glsl version mismatch in compat profile

What about GL 2.1 and 2.0 (and earlier where you could still have GLSL as an ext)? And does the GLSL version have to line up exactly for those? Or does this just need to be default: if (ctx->Version < 31) ctx->Const.GLSLVersion = MIN2(ctx->Const.GLSLVersion, 130) else ctx->Const.GLSLVersion =

[Mesa-dev] [Bug 105807] [Regression, bisected]: 3D Rendering not working correctly in Warhammer 40k: Dawn of War II

https://bugs.freedesktop.org/show_bug.cgi?id=105807 Alan Swanson changed: What|Removed |Added Assignee|intel-3d-bugs@lists.freedes |mesa-dev@lists.freedesktop.

[Mesa-dev] [PATCH] glsl: properly handle bindless sampler and image parameters

fixes a piglit test I sent to the list: spec@arb_bindless_texture@execution@samplers@basic-arithmetic-func-call-uvec2-texture2D Signed-off-by: Karol Herbst --- src/compiler/glsl/opt_function_inlining.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/opt_fu

Re: [Mesa-dev] [PATCH] radv: move save/restore operations close to the slow clears

On 04/10/2018 11:20 AM, Bas Nieuwenhuizen wrote: Reviewed-by: Bas Nieuwenhuizen I'm wondering though, doesn't this result in more saves/restores, as we now do it for each part of a subpass clear separately? Yes, possibly. I'm actually not sure myself if it's the right thing to do. I will p

[Mesa-dev] [PATCH] radv: fix picking the method for resolve subpass

The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 2 +- 1 file changed, 1 insertion(+), 1 d

Re: [Mesa-dev] [PATCH v3 057/104] nir,spirv: Rework function calls

On Mon, Apr 9, 2018 at 10:52 PM, Jason Ekstrand wrote: > + A bunch of potentially interested parties. > > On Mon, Apr 9, 2018 at 4:25 PM, Caio Marcelo de Oliveira Filho > wrote: >> >> Hi, >> >> > typedef struct { >> > - nir_parameter_type param_type; >> > - const struct glsl_type *type; >> >

[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

https://bugs.freedesktop.org/show_bug.cgi?id=105846 l...@protonmail.ch changed: What|Removed |Added Status|NEEDINFO|RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH] i965: Check result of make_surface() for miptree_create

CCing: Jason Ekstrand and Topi Pohjolainen. 2018-04-09 13:36 GMT+02:00 : > From: Andrea Azzarone > > Since make_surface() can fail we need to check the result before > dereferencing it. > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --

Re: [Mesa-dev] [PATCH] radv: add shader BOs to the list at pipeline bind time

Reviewed-by: Bas Nieuwenhuizen On Tue, Apr 10, 2018 at 2:09 PM, Samuel Pitoiset wrote: > Otherwise, the shader BOs are not added to the list on SI because > prefetching isn't supported. Calling radv_cs_add_buffer() in the > prefetch codepath was a bad idea. > > Bugzilla: https://bugs.freedesktop

[Mesa-dev] [PATCH] radv: add shader BOs to the list at pipeline bind time

Otherwise, the shader BOs are not added to the list on SI because prefetching isn't supported. Calling radv_cs_add_buffer() in the prefetch codepath was a bad idea. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105952 Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_pref

Re: [Mesa-dev] [PATCH v2] nv50/ir: make a copy of tex src if it's referenced multiple times

On Tue, Apr 10, 2018 at 6:08 AM, Karol Herbst wrote: > I guess this fixes a bug somewhere? Yeah... I describe it in the commit description, I thought. Here's the situation: %r1 = 5 %r2 = texsize %r1 %r3 = texsize %r1 Now, let's not worry about why those didn't get CSE'd. (Let's say they refer t

[Mesa-dev] [PATCH] mesa: fix glsl version mismatch in compat profile

Drivers that only support compat 3.0 were reporting GLSL 1.40 support. This fixes issues with the menu of Dawn of War II. Fixes: a0c8b49284ef "mesa: enable OpenGL 3.1 with ARB_compatibility" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105807 --- src/mesa/main/version.c | 8 ++-- 1

Re: [Mesa-dev] [PATCH 00/22] VP9 support

Nice work. Series is Acked-by: Christian König . Christian. Am 09.04.2018 um 18:35 schrieb Leo Liu: This series will enable VP9 support for profile0 and profile2 on VCN. It will support players with VP9 VA-API enabled. Leo Liu (22): vl: add VP9 profile0 and format vl: add VP9 picture des

[Mesa-dev] [Bug 105832] radeonsi NIR missing bindless textures support

https://bugs.freedesktop.org/show_bug.cgi?id=105832 --- Comment #21 from Timothy Arceri --- (In reply to Karol Herbst from comment #19) > how can you make dow2 use bindless_textures? This kind of looks like a mesa > issue and not really related to radeonsi at all (the shader compile fails) DoW3

[Mesa-dev] [Bug 105832] radeonsi NIR missing bindless textures support

https://bugs.freedesktop.org/show_bug.cgi?id=105832 --- Comment #20 from Karol Herbst --- (In reply to Karol Herbst from comment #19) > how can you make dow2 use bindless_textures? This kind of looks like a mesa > issue and not really related to radeonsi at all (the shader compile fails) ohh com

[Mesa-dev] [Bug 105832] radeonsi NIR missing bindless textures support

https://bugs.freedesktop.org/show_bug.cgi?id=105832 --- Comment #19 from Karol Herbst --- how can you make dow2 use bindless_textures? This kind of looks like a mesa issue and not really related to radeonsi at all (the shader compile fails) -- You are receiving this mail because: You are the QA

Re: [Mesa-dev] [PATCH v2] nv50/ir: make a copy of tex src if it's referenced multiple times

I guess this fixes a bug somewhere? On Tue, Apr 10, 2018 at 6:11 AM, Ilia Mirkin wrote: > For nv50 we coalesce the srcs and defs into a single node. As such, we > can end up with impossible constraints if the source is referenced > after the tex operation (which, due to the coalescing of values,

Re: [Mesa-dev] [PATCH 1/4] ac/surface: don't set the display flag for obviously unsupported cases (v2)

On 2018-04-06 07:12 PM, Marek Olšák wrote: > From: Marek Olšák > > This enables the tile swizzle for some cases of the displayable micro mode, > and it also fixes an addrlib assertion failure on Vega. [...] > diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c > index dd3189c

Re: [Mesa-dev] [PATCH] radv: move save/restore operations close to the slow clears

Reviewed-by: Bas Nieuwenhuizen I'm wondering though, doesn't this result in more saves/restores, as we now do it for each part of a subpass clear separately? On Mon, Apr 9, 2018 at 11:10 PM, Samuel Pitoiset wrote: > This removes the emission of unnecessary states, for example > when performing

[Mesa-dev] [Bug 105952] radv causes GPU hang on SI

https://bugs.freedesktop.org/show_bug.cgi?id=105952 --- Comment #10 from Turo Lamminen --- I did a little experiment, I rebased locally and removed the broken commit (4ad7595f350462c704fbe5b2bd2ca406c904e78e) and then the followups (942fdfe357, f1d7c16e85, 04e609f1f8) because they no longer appli

[Mesa-dev] [Bug 105952] radv causes GPU hang on SI

https://bugs.freedesktop.org/show_bug.cgi?id=105952 --- Comment #9 from Turo Lamminen --- Still happens in 4381be4648b9ebb15b0a06885489998d5daac482 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.__

Re: [Mesa-dev] [PATCH] i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

Reviewed-by: Iago Toral Quiroga On Tue, 2018-04-10 at 01:33 -0700, Kenneth Graunke wrote: > I'd like to drop this pre-isl function. This drops one of the two > uses. > --- > src/mesa/drivers/dri/i965/intel_screen.c | 14 -- > 1 file changed, 4 insertions(+), 10 deletions(-) > > dif

Re: [Mesa-dev] [PATCH 3/3] egl/x11: Handle both depth 30 formats for eglCreateImage().

On 2018-04-10 10:22 AM, Mario Kleiner wrote: > On 04/09/2018 12:12 PM, Michel Dänzer wrote: >> On 2018-04-06 08:56 PM, Mario Kleiner wrote: >> >> I'm interested in the full xdpyinfo *at screen depth 30*, in particular >> whether it lists only one variant of depth 30 visuals. If so, one >> possibili

[Mesa-dev] [PATCH] i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

I'd like to drop this pre-isl function. This drops one of the two uses. --- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 29cb7

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

On 07/04/18 08:21, Jason Ekstrand wrote: On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick > wrote: From: Antia Puentes mailto:apuen...@igalia.com>> We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID vertex element. The previous Vertex Eleme

Re: [Mesa-dev] [PATCH 3/3] egl/x11: Handle both depth 30 formats for eglCreateImage().

On 04/09/2018 12:12 PM, Michel Dänzer wrote: On 2018-04-06 08:56 PM, Mario Kleiner wrote: On 04/06/2018 06:41 PM, Michel Dänzer wrote: On 2018-04-06 06:18 PM, Mario Kleiner wrote: On Fri, Apr 6, 2018 at 12:01 PM, Michel Dänzer wrote: On 2018-03-27 07:53 PM, Daniel Stone wrote: On 12 March 2

Re: [Mesa-dev] [PATCH] ac/nir: Use an array instead of hashtable for SSA defs.

On 10/04/18 18:17, Timothy Arceri wrote: On 10/04/18 17:33, Bas Nieuwenhuizen wrote: Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. ---   src/amd/c

Re: [Mesa-dev] [PATCH] ac/nir: Use an array instead of hashtable for SSA defs.

On 10/04/18 17:33, Bas Nieuwenhuizen wrote: Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. --- src/amd/common/ac_nir_to_llvm.c | 22 +---

Re: [Mesa-dev] [PATCH] dri3: Prevent multiple freeing of buffers.

Hello, i've updated patch simply, but that seems requires additional checking because in call *dri3_handle_present_event *potentially may happens reset of '*busy*' with condition '*buf->pixmap == ie->pixmap*' On Fri, Apr 6, 2018 at 9:03 PM, Thomas Hellstrom wrote: > Hi, > > > On 04/06/2018 04:51

Re: [Mesa-dev] [PATCH] radeonsi: correct si_vgt_param_key on big endian machines

On 2018-04-10 10:03 AM, Bas Vermeulen wrote: > On Mon, Apr 9, 2018 at 11:19 PM, Gert Wollny wrote: >> Am Montag, den 09.04.2018, 14:03 -0400 schrieb Marek Olšák: >>> On Mon, Apr 9, 2018 at 10:51 AM, Bas Vermeulen > >> There is another option: Check at configuration time whether the bit >> field

Re: [Mesa-dev] [PATCH] docs/release-calendar: update to include 18.1 and 18.2

On Mon, 2018-04-09 at 19:02 +0100, Emil Velikov wrote: > From: Emil Velikov > > Dylan has kindly stepped up to help with 18.1.0, while I've taken the > liberty to nominate Andres for 18.2.0 ;-) > I would like to replace Andres for the 18.0.x releases. We already talked about that and both think

Re: [Mesa-dev] [PATCH] radeonsi: correct si_vgt_param_key on big endian machines

On Mon, Apr 9, 2018 at 11:19 PM, Gert Wollny wrote: > Am Montag, den 09.04.2018, 14:03 -0400 schrieb Marek Olšák: > > On Mon, Apr 9, 2018 at 10:51 AM, Bas Vermeulen > > wrote: > Which solution is better depends on what is done more often: reading > the index or writing to the bit fields. > The

Re: [Mesa-dev] [PATCH] radeonsi: correct si_vgt_param_key on big endian machines

On 2018-04-10 08:38 AM, Gert Wollny wrote: > Am Montag, den 09.04.2018, 17:26 -0400 schrieb Marek Olšák: >> On Mon, Apr 9, 2018 at 5:19 PM, Gert Wollny >> wrote: >>> >>> There is another option: Check at configuration time whether the >>> bit field layout is like the low or the high endian layout

[Mesa-dev] [Bug 105942] Graphical artefacts after update to mesa 18.0.0-2

https://bugs.freedesktop.org/show_bug.cgi?id=105942 Samuel Pitoiset changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH] ac/nir: Use an array instead of hashtable for SSA defs.

Reviewed-by: Samuel Pitoiset On 04/10/2018 09:33 AM, Bas Nieuwenhuizen wrote: Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. --- src/amd/common/ac_n

[Mesa-dev] [PATCH v2] dri3: Prevent multiple freeing of buffers.

Commit 3160cb86aa92 adds optimization with flag 'reallocate'. Processing of flag causes buffers freeing while pointer is still hold in caller stack and than again used to be freed. Fixes: 3160cb86aa92 "egl/x11: Re-allocate buffers if format is suboptimal" v2: used flag 'busy' instead of introduc

[Mesa-dev] [PATCH] egl/x11: Handle both depth 30 formats for eglCreateImage(). (v2)

We need to distinguish if the backing storage of a pixmap is XRGB2101010 or XBGR2101010, as different gpu hw supports different formats. NVidia hw prefers XBGR, whereas AMD and Intel are happy with XRGB. Use the red channel mask of the first depth 30 visual of the x-screen to distinguish which hw

[Mesa-dev] [PATCH] ac/nir: Use an array instead of hashtable for SSA defs.

Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. --- src/amd/common/ac_nir_to_llvm.c | 22 +- 1 file changed, 13 insertions(+), 9 delet

[Mesa-dev] [Bug 105807] [Regression, bisected]: 3D Rendering not working correctly in Warhammer 40k: Dawn of War II

https://bugs.freedesktop.org/show_bug.cgi?id=105807 Timothy Arceri changed: What|Removed |Added Component|Mesa core |Drivers/DRI/i965 QA Contact|me

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