[Mesa-dev] [PATCH 3/9] nir/opt_peephole_select: Don't peephole_select expensive math instructions

From: Ian Romanick On some GPUs, especially older Intel GPUs, some math instructions are very expensive. On those architectures, don't reduce flow control to a csel if one of the branches contains one of these expensive math instructions. This prevents a bunch of cycle count regressions on

[Mesa-dev] [PATCH 8/9 v2] nir: Add partial redundancy elimination for compares

From: Ian Romanick This pass attempts to dectect code sequences like if (x < y) { z = y - x; ... } and replace them with sequences like t = x - y; if (t < 0) { z = t; ... } On architectures where the subtract can generate the flags used by

[Mesa-dev] [PATCH 6/9] nir: Add nir_const_value_negative_equal

From: Ian Romanick Signed-off-by: Ian Romanick --- src/compiler/nir/meson.build| 12 + src/compiler/nir/nir.h | 6 + src/compiler/nir/nir_instr_set.c| 98 + src/compiler/nir/tests/negative_equal_tests.cpp | 278

[Mesa-dev] [PATCH 5/9] nir: Add helper functions to get the instruction that generated a nir_src

From: Ian Romanick Signed-off-by: Ian Romanick --- src/compiler/nir/nir.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index feb69be6b59..9bca6d487e9 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h

[Mesa-dev] [RESEND PATCH 0/9] Partial redundancy elimination for compares

This is mostly a resend of this series. Several patches, noted with "v#", have been updated. Patches 3 and 4 are new. Right before sending the series, I decided to update the shader-db results AND update shader-db. The update to shader-db added a bunch of new shaders hurt by patch 4. It may

[Mesa-dev] [PATCH 1/9 v3] nir/opt_peephole_select: Don't try to remove flow control around indirect loads

From: Ian Romanick That flow control may be trying to avoid invalid loads. On at least some platforms, those loads can also be expensive. No shader-db changes on any Intel platform (even with the later patch "intel/compiler: More peephole select"). NOTE: I've tried to CC everyone whose driver

[Mesa-dev] [PATCH 7/9 v2] nir: Add nir_alu_srcs_negative_equal

From: Ian Romanick v2: Move bug fix in get_neg_instr from the next patch to this patch (where it was intended to be in the first place). Noticed by Caio. Signed-off-by: Ian Romanick --- src/compiler/nir/nir.h | 4 + src/compiler/nir/nir_instr_set.c|

[Mesa-dev] [PATCH 4/9] intel/compiler: More peephole_select for pre-Gen6

From: Ian Romanick No shader-db changes on any Gen6+ platform. All of the shaders with cycles hurt by more than ~2% are from Master of Orion. All of the shaders have instructions helped. It looks like the pass enables some control flow to be converted to bcsels, then the scheduler does dumb

[Mesa-dev] [PATCH 2/9 v2] intel/compiler: More peephole select

From: Ian Romanick Shader-db results: The one shader hurt for instructions is a compute shader that had both spills and fills hurt. v2: Fix typo in comment noticed by Caio. Skylake, Broadwell, and Haswell had similar results. (Skylake shown) total instructions in shared programs: 15108590 ->

[Mesa-dev] [PATCH 9/9] intel/compiler: Use partial redundancy elimination for compares

From: Ian Romanick Almost all of the hurt shaders are repeated instances of the same shader in synmark's compilation speed tests. shader-db results: All Gen6+ platforms had similar results. (Skylake shown) total instructions in shared programs: 15083798 -> 15083033 (<.01%) instructions in

Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: allow GL_UNSIGNED_BYTE type for SNORM reads

On 08/30/2018 01:04 AM, Andres Gomez wrote: On Wed, 2018-08-29 at 08:22 -0700, Dylan Baker wrote: Quoting Tapani Pälli (2018-08-27 04:46:37) OpenGL ES spec states: "For normalized fixed-point rendering surfaces, the combination format RGBA and type UNSIGNED_BYTE is accepted." This

Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: allow GL_UNSIGNED_BYTE type for SNORM reads

On 08/29/2018 06:22 PM, Dylan Baker wrote: Quoting Tapani Pälli (2018-08-27 04:46:37) OpenGL ES spec states: "For normalized fixed-point rendering surfaces, the combination format RGBA and type UNSIGNED_BYTE is accepted." This fixes following failing VK-GL-CTS tests:

Re: [Mesa-dev] [PATCH] gallivm: Detect VSX separately from Altivec

Am 24.08.2018 um 18:22 schrieb Vicki Pfau: > Is there anything else I need to do on this? This is my first mesa patch > so I'm not entirely clear what next steps are for getting it committed. No that's all needed, pushed, sorry for the delay. Thanks! Roland > > > On 08/20/2018 02:44 PM,

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On 30/08/18 12:56, Jason Ekstrand wrote: On Wed, Aug 29, 2018 at 9:45 PM Timothy Arceri > wrote: On 30/08/18 10:57, Ian Romanick wrote: > On 08/27/2018 02:08 AM, Timothy Arceri wrote: >> Since we know what side of the branch we ended up on we can just

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #18 from Clément Guérin --- I confirm it works. I'm able to run the game at Ultra settings without any visible glitches. Thanks for your hard work! There's another small issue with inverted reflections, it's still unclear if it's a

[Mesa-dev] [PATCH 0/2] freedreno: fix crashes of deqp gles31

This series fixes some crashes of tests from deqp gles31 on freedreno. Thanks for review. Hyunjun Ko (2): freedreno/ir3: make immediates array dynamic freedreno/ir3: insert mov if same instruction in the outputs. .../drivers/freedreno/ir3/ir3_compiler_nir.c | 14 ++

[Mesa-dev] [PATCH 1/2] freedreno/ir3: make immediates array dynamic

Since most shaders wouldn't need that large array of immediates, making the array dynamic could save unnecessary spaces. In addition, sometimes we can potentially have a much larger array of immediates to be lowered, which might be more than 64. --- src/gallium/drivers/freedreno/ir3/ir3_cp.c

[Mesa-dev] [PATCH 2/2] freedreno/ir3: insert mov if same instruction in the outputs.

For example, result0 = texture(sampler[indexBase + 5], coords); result1 = texture(sampler[indexBase + 0], coords); result2 = texture(sampler[indexBase + 0], coords); out_result0 = result0; out_result1 = result1; out_result2 = result2; In this kind of case we need to

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On Wed, Aug 29, 2018 at 9:45 PM Timothy Arceri wrote: > On 30/08/18 10:57, Ian Romanick wrote: > > On 08/27/2018 02:08 AM, Timothy Arceri wrote: > >> Since we know what side of the branch we ended up on we can just > >> replace the use with a constant. > >> > >> All the spill changes in

Re: [Mesa-dev] [PATCH v3] nir: propagates if condition evaluation down some alu chains

On 30/08/18 11:05, Ian Romanick wrote: I feel like this would be a good candidate for some unit tests. As a follow up, you might also consider adding bcsel. I have seen quite a few cases of bcsel(bool, bool, bool). Ah yes that is probably a good one to try. I'll give it a go. On

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On 30/08/18 10:57, Ian Romanick wrote: On 08/27/2018 02:08 AM, Timothy Arceri wrote: Since we know what side of the branch we ended up on we can just replace the use with a constant. All the spill changes in shader-db are from Dolphin uber shaders, despite some small regressions the change is

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On Wed, Aug 29, 2018 at 7:58 PM Ian Romanick wrote: > On 08/27/2018 02:08 AM, Timothy Arceri wrote: > > Since we know what side of the branch we ended up on we can just > > replace the use with a constant. > > > > All the spill changes in shader-db are from Dolphin uber shaders, > > despite some

Re: [Mesa-dev] [PATCH v3] nir: propagates if condition evaluation down some alu chains

On Wed, Aug 29, 2018 at 6:48 PM Timothy Arceri wrote: > v2: > - only allow nir_op_inot or nir_op_b2i when alu input is 1. > - use some helpers as suggested by Jason. > > v3: > - evaluate alu op for single input alu ops > - add helper function to decide if to propagate through alu > - make

Re: [Mesa-dev] [PATCH v4 6/7] nir: add loop unroll support for wrapper loops

On 08/27/2018 02:08 AM, Timothy Arceri wrote: > This adds support for unrolling the classic > > do { > // ... > } while (false) > > that is used to wrap multi-line macros. GLSL IR also wraps switch > statements in a loop like this. Yes! This has been several items down on my

Re: [Mesa-dev] [PATCH v3] nir: propagates if condition evaluation down some alu chains

I feel like this would be a good candidate for some unit tests. As a follow up, you might also consider adding bcsel. I have seen quite a few cases of bcsel(bool, bool, bool). On 08/29/2018 04:48 PM, Timothy Arceri wrote: > v2: > - only allow nir_op_inot or nir_op_b2i when alu input is 1. > -

Re: [Mesa-dev] [PATCH] glsl/linker: Link all out vars from a shader objects on a single stage

On 30/08/18 08:16, Andres Gomez wrote: Vadym, should we also include this in the stable queues ? Yes. It should be fine to add this to stable. Thanks. On Mon, 2018-08-27 at 15:20 +0300, Vadym Shovkoplias wrote: From: "vadym.shovkoplias" During intra stage linking some out variables can

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 --- Comment #4 from Timothy Arceri --- (In reply to Mark Janes from comment #3) > Vadym, can you make a piglit test for this bug? Hi Mark, this was already done :) commit c98669cbd1f801c8fda25aceab23b5c54de76b9e Author: Vadym Shovkoplias

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On 08/27/2018 02:08 AM, Timothy Arceri wrote: > Since we know what side of the branch we ended up on we can just > replace the use with a constant. > > All the spill changes in shader-db are from Dolphin uber shaders, > despite some small regressions the change is clearly positive. > > V2:

[Mesa-dev] [PATCH] radv/meta: Set num_components on image_store intrinsics

Now that image load/store intrinsics are variable-width, we need to set num_components accordingly. In 15d39f474b890, both glsl_to_nir and spirv_to_nir were updated to properly set num_components but radv meta was left behind. Fixes: 15d39f474b890 "nir: Make image load/store intrinsics..." ---

[Mesa-dev] [PATCH] intel: limit urb size for SKL/KBL/CFL GT1

The documentation puts the URB size for SKL GT1 as "128K - 192K". I guess this means we can't tell which one it is, so we have to go for the lower bound. This change also changes the max VS URB entries which is lower on GT1 skus. Fixes a CTS test :

[Mesa-dev] [ANNOUNCE] mesa 18.2.0-rc5

Hello list, The fifth release candidate for the Mesa 18.2.0 is now available. As per the issue tracker [1] we still have a number of outstanding bugs blocking the release. [1] https://bugs.freedesktop.org/show_bug.cgi?id=107457 Currently we have: - 23 queued - 11 nominated (outstanding) -

[Mesa-dev] [PATCH 1/9] mesa: move legacy TCL dri config options

--- src/mesa/drivers/dri/radeon/radeon_screen.c | 10 + src/mesa/drivers/dri/radeon/radeon_screen.h | 5 + src/util/xmlpool/ca.po | 23 - src/util/xmlpool/de.po | 23 - src/util/xmlpool/es.po

[Mesa-dev] [PATCH 6/9] mesa: move legacy dri config option no_neg_lod_bias

--- src/mesa/drivers/dri/radeon/radeon_screen.c | 5 + src/util/xmlpool/ca.po | 6 -- src/util/xmlpool/de.po | 4 src/util/xmlpool/es.po | 4 src/util/xmlpool/fr.po | 4

[Mesa-dev] [PATCH 8/9] mesa: move legacy dri config option fthrottle_mode

--- src/mesa/drivers/dri/radeon/radeon_screen.h | 12 src/util/xmlpool/ca.po | 17 - src/util/xmlpool/de.po | 17 - src/util/xmlpool/es.po | 17 - src/util/xmlpool/fr.po

[Mesa-dev] [PATCH 4/9] mesa: remove unused dri option float_depth

This seems to have only been used by DRI1 drivers which were removed with e4344161bde2. --- src/util/xmlpool/ca.po | 4 src/util/xmlpool/de.po | 4 src/util/xmlpool/es.po | 4 src/util/xmlpool/fr.po | 4 src/util/xmlpool/nl.po | 4

[Mesa-dev] [PATCH 3/9] mesa: move legacy dri config option dither_mode

--- src/mesa/drivers/dri/radeon/radeon_screen.h | 12 src/util/xmlpool/ca.po | 16 src/util/xmlpool/de.po | 16 src/util/xmlpool/es.po | 16 src/util/xmlpool/fr.po

[Mesa-dev] [PATCH 7/9] mesa: move legacy dri config option def_max_anisotropy

--- src/mesa/drivers/dri/radeon/radeon_screen.c | 5 + src/util/xmlpool/ca.po | 4 src/util/xmlpool/de.po | 4 src/util/xmlpool/es.po | 4 src/util/xmlpool/fr.po | 4 src/util/xmlpool/nl.po

[Mesa-dev] [PATCH 2/9] mesa: move legacy dri config option color_reduction

--- src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++ src/util/xmlpool/ca.po | 12 src/util/xmlpool/de.po | 12 src/util/xmlpool/es.po | 12 src/util/xmlpool/fr.po

[Mesa-dev] [PATCH 5/9] mesa: move legacy dri config option round_mode

--- src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++ src/util/xmlpool/ca.po | 12 src/util/xmlpool/de.po | 12 src/util/xmlpool/es.po | 12 src/util/xmlpool/fr.po

[Mesa-dev] [PATCH 9/9] mesa: move legacy dri config option texture_depth

--- src/mesa/drivers/dri/radeon/radeon_screen.h | 13 + src/util/xmlpool/ca.po | 20 src/util/xmlpool/de.po | 20 src/util/xmlpool/es.po | 20

[Mesa-dev] [PATCH v3] nir: propagates if condition evaluation down some alu chains

v2: - only allow nir_op_inot or nir_op_b2i when alu input is 1. - use some helpers as suggested by Jason. v3: - evaluate alu op for single input alu ops - add helper function to decide if to propagate through alu - make use of nir_before_src in another spot shader-db IVB results: total

Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

On Wednesday, August 29, 2018 1:12:28 PM PDT Ian Romanick wrote: > From: Ian Romanick > > Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid > range of the offset is [0, 0FFFh]. > > Signed-off-by: Ian Romanick > Cc: mesa-sta...@lists.freedesktop.org > Cc: Kenneth

[Mesa-dev] [PATCH 2/2] gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi

From: Marek Olšák --- docs/relnotes/18.3.0.html| 1 + src/gallium/docs/source/screen.rst | 4 src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c

[Mesa-dev] [PATCH 1/2] gallium: split depth_clip into depth_clip_near & depth_clip_far

From: Marek Olšák for AMD_depth_clamp_separate. --- src/gallium/auxiliary/draw/draw_context.c | 2 +- src/gallium/auxiliary/driver_trace/tr_dump_state.c | 3 ++- src/gallium/auxiliary/hud/hud_context.c | 3 ++- src/gallium/auxiliary/postprocess/pp_program.c | 3 ++-

Re: [Mesa-dev] [PATCH] glsl/linker: Link all out vars from a shader objects on a single stage

Vadym, should we also include this in the stable queues ? On Mon, 2018-08-27 at 15:20 +0300, Vadym Shovkoplias wrote: > From: "vadym.shovkoplias" > > During intra stage linking some out variables can be dropped because > it is not used in a shader with the main function. But these out vars >

Re: [Mesa-dev] [PATCH 2/2] st/mesa, gallium: add a workaround for No Mans Sky

Reviewed-by: Marek Olšák Marek On Wed, Aug 29, 2018 at 1:48 AM, Timothy Arceri wrote: > The spec seems clear this is not allowed but the Nvidia binary > forces apps to add layout qualifiers so this works around the > issue for No Mans Sky until the CTS can be sorted out. > --- >

Re: [Mesa-dev] [PATCH 1/2] glsl: add a mechanism to allow layout qualifiers on function params

Uh. Reviewed-by: Marek Olšák Marek On Wed, Aug 29, 2018 at 1:48 AM, Timothy Arceri wrote: > The spec is quite clear this is not allowed: > > From Section 4.4. (Layout Qualifiers) of the GLSL 4.60 spec: > >"Layout qualifiers can appear in several forms of declaration. >They

Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: allow GL_UNSIGNED_BYTE type for SNORM reads

On Wed, 2018-08-29 at 08:22 -0700, Dylan Baker wrote: > Quoting Tapani Pälli (2018-08-27 04:46:37) > > OpenGL ES spec states: > >"For normalized fixed-point rendering surfaces, the combination format > > RGBA and type UNSIGNED_BYTE is accepted." > > > > This fixes following failing

Re: [Mesa-dev] [PATCH] gallivm/radeonsi: allow to pass two swizzles into fetches.

Reviewed-by: Marek Olšák Marek On Mon, Aug 27, 2018 at 5:16 PM, Dave Airlie wrote: > From: Dave Airlie > > This hijacks the top 16-bits of swizzle, to pass in the swizzle > for the second channel. > > This fixes handling .yx swizzles of 64-bit values. > > This should fixup radeonsi and

Re: [Mesa-dev] [PATCH] docs/relnotes: Add AMD_depth_clamp_separate for i965

Hi Marek, Thanks for reviewing but I don't have commit rights yet. :( -- Sagar On 08/29/2018 02:34 PM, Marek Olšák wrote: > Looks good. You can push this without an Rb. > > Marek > > On Tue, Aug 28, 2018 at 5:53 PM, Sagar Ghuge wrote: >> Signed-off-by: Sagar Ghuge >> --- >>

Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

On Wed, Aug 29, 2018 at 4:32 PM Ian Romanick wrote: > On 08/29/2018 02:22 PM, Jason Ekstrand wrote: > > Have you seen this cause an actual problem? There's no way we can > > actually end up with an input array that big... I guess this is for the > > crazy OOB case? > > The array can't be that

Re: [Mesa-dev] [PATCH] mesa/state_tracker: explicitely handle case ir_intrinsic_begin_fragment_shader_ordering in visit_generic_intrinsic()

Reviewed-by: Marek Olšák Marek On Tue, Aug 28, 2018 at 2:07 PM, wrote: > From: Kevin Rogovin > > --- > src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp >

Re: [Mesa-dev] [PATCH] docs/relnotes: Add AMD_depth_clamp_separate for i965

Looks good. You can push this without an Rb. Marek On Tue, Aug 28, 2018 at 5:53 PM, Sagar Ghuge wrote: > Signed-off-by: Sagar Ghuge > --- > docs/relnotes/18.3.0.html | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html > index

Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

On 08/29/2018 02:22 PM, Jason Ekstrand wrote: > Have you seen this cause an actual problem?  There's no way we can > actually end up with an input array that big...  I guess this is for the > crazy OOB case? The array can't be that big due to other compiler limits. This is just to prevent a

Re: [Mesa-dev] [Mesa-stable] [PATCH] ac/radeonsi: fix CIK copy max size

Reviewed-by: Marek Olšák Marek On Tue, Aug 28, 2018 at 11:53 PM, Dave Airlie wrote: > From: Dave Airlie > > While adding transfer queues to radv, I started writing some tests, > the first test I wrote fell over copying a buffer larger than this > limit. > > Checked AMDVLK and found the

Re: [Mesa-dev] [Mesa-stable] [PATCH] ac/radeonsi: fix CIK copy max size

Thanks. Not surprising though. :) Marek On Tue, Aug 28, 2018 at 11:53 PM, Dave Airlie wrote: > From: Dave Airlie > > While adding transfer queues to radv, I started writing some tests, > the first test I wrote fell over copying a buffer larger than this > limit. > > Checked AMDVLK and found

Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

Have you seen this cause an actual problem? There's no way we can actually end up with an input array that big... I guess this is for the crazy OOB case? On Wed, Aug 29, 2018 at 3:12 PM Ian Romanick wrote: > From: Ian Romanick > > Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says

Re: [Mesa-dev] [PATCH] radv: Add missing checks in radv_get_image_format_properties.

Sounds reasonable to me. Reviewed-by: Samuel Pitoiset On 8/29/18 5:14 PM, Bas Nieuwenhuizen wrote: CC: --- src/amd/vulkan/radv_formats.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #17 from Samuel Pitoiset --- Here's the real fix: https://patchwork.freedesktop.org/patch/246462/ Can you confirm that fixes the issue on your side? Thanks! -- You are receiving this mail because: You are the QA Contact for the

[Mesa-dev] [PATCH v2] radv: fix passing clip/cull distances from VS to PS

CTS doesn't test input clip/cull distances for the fragment shader stage, which explains why this was totally broken. I wrote a simple test locally that works now. This fixes a crash with GTA V and DXVK. Note that we are exporting unused parameters from the vertex shader now, but this can't be

Re: [Mesa-dev] [PATCH 5/9] nir: Add a local dead write vars removal pass

On Wed, Aug 29, 2018 at 3:19 PM Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > Jason Ekstrand writes: > > >> >> +static bool > >> >> +remove_dead_write_vars_local(struct state *state, nir_block *block) > >> >> +{ > >> >> + bool progress = false; > >> >> + > >> >> + struct

[Mesa-dev] [PATCH v2] i965/gen7_urb: Re-emit PUSH_CONSTANT_ALLOC on some gen9

According to internal docs, some gen9 platforms have a pixel shader push constant synchronization issue. Although not listed among said platforms, this issue seems to be present on the GeminiLake 2x6's we've tested. We consider the available workarounds to be too detrimental on performance.

Re: [Mesa-dev] [PATCH 5/9] nir: Add a local dead write vars removal pass

Jason Ekstrand writes: >> >> +static bool >> >> +remove_dead_write_vars_local(struct state *state, nir_block *block) >> >> +{ >> >> + bool progress = false; >> >> + >> >> + struct util_dynarray unused_writes; >> >> + util_dynarray_init(_writes, state->mem_ctx); >> >> + >> >> +

[Mesa-dev] [PATCH 10/15] radeonsi: merge SI and CI dma_clear_buffer and remove the callback

From: Marek Olšák also use assertions for the requirements that offset and size are a multiple of 4. --- src/gallium/drivers/radeon/radeon_video.c | 3 +- src/gallium/drivers/radeonsi/cik_sdma.c | 41 - src/gallium/drivers/radeonsi/si_cp_dma.c | 2 +-

[Mesa-dev] [PATCH 01/15] radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI

From: Marek Olšák VI uses addrlib so it's unaffected. Cc: 18.1 18.2 --- src/gallium/drivers/radeonsi/si_texture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index

[Mesa-dev] [PATCH 14/15] radeonsi: flush when an IB uses more VRAM than available

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 29d7e555a0c..b3d607b93e3 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++

[Mesa-dev] [PATCH 13/15] radeonsi: adjust and simplify max_alloc_size determination

From: Marek Olšák --- src/amd/common/ac_gpu_info.c | 16 .../winsys/radeon/drm/radeon_drm_winsys.c| 8 +--- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index

[Mesa-dev] [PATCH 15/15] radeonsi/nir: port some bindless and sampler code from TGSI

From: Marek Olšák These might be all missing changes for bindless textures. --- src/gallium/drivers/radeonsi/si_shader_nir.c | 80 1 file changed, 50 insertions(+), 30 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c

[Mesa-dev] [PATCH 12/15] radeonsi: split si_copy_buffer

From: Marek Olšák compute and SDMA will be added into it. --- src/gallium/drivers/radeonsi/si_blit.c| 2 +- src/gallium/drivers/radeonsi/si_cp_dma.c | 33 --- src/gallium/drivers/radeonsi/si_pipe.c| 3 +- src/gallium/drivers/radeonsi/si_pipe.h| 8

[Mesa-dev] [PATCH 11/15] radeonsi: don't call VBO prefetch with size=0

From: Marek Olšák for the next commit. --- src/gallium/drivers/radeonsi/si_cp_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 598d5ecf0dc..ad53682b1b2 100644 ---

[Mesa-dev] [PATCH 08/15] ac: remove deprecated use of LLVMInt1Type()

From: Marek Olšák --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 192ef079215..18644107eb4 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 06/15] ac: add radeon_info::num_good_cu_per_sh

From: Marek Olšák --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + src/gallium/drivers/radeonsi/si_state.c | 4 +--- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 4 files changed, 9 insertions(+), 3

[Mesa-dev] [PATCH 09/15] radeonsi: fix GPU hangs with bindless textures and LLVM 7.0

From: Marek Olšák --- src/amd/common/ac_llvm_build.c| 52 +-- src/amd/common/ac_llvm_build.h| 4 ++ .../drivers/radeonsi/si_shader_internal.h | 3 +- src/gallium/drivers/radeonsi/si_shader_nir.c | 12 -

[Mesa-dev] [PATCH 07/15] ac: use iN_0/1 constants

From: Marek Olšák --- src/amd/common/ac_llvm_build.c| 23 +-- src/amd/common/ac_nir_to_llvm.c | 4 ++-- src/gallium/drivers/radeonsi/si_shader.c | 4 ++-- .../drivers/radeonsi/si_shader_tgsi_alu.c | 2 +- 4 files changed, 16

[Mesa-dev] [PATCH 05/15] ac: revert new LLVM 7.0 behavior for fdiv

From: Marek Olšák Cc: 18.1 18.2 --- src/amd/common/ac_llvm_build.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c741a1ab62d..629cd2a7527 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 04/15] radeonsi: fix printing a BO list into ddebug reports

From: Marek Olšák important for debugging Cc: 18.1 18.2 --- src/gallium/drivers/radeonsi/si_gfx_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index c39564ecbe5..38b85ce6243 100644

[Mesa-dev] [PATCH 02/15] winsys/radeon: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI

From: Marek Olšák Cc: 18.1 18.2 --- src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index fda1ba7870e..20cfc86ebe0

[Mesa-dev] [PATCH 00/15] RadeonSI Fixes and Cleanups

Hi, There are HTILE and CMASK allocator fixes, a GPU hang fix for bindless textures with LLVM 7.0, partial NIR support for bindless textures, ddebug fix, and much more. Please review. Thanks, Marek ___ mesa-dev mailing list

[Mesa-dev] [PATCH 03/15] r600: fix HTILE for NPOT textures with mipmapping

From: Marek Olšák Cc: 18.1 18.2 --- src/gallium/drivers/r600/r600_texture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 08db6bab04c..d08c6e5637c 100644 ---

[Mesa-dev] [PATCH 2/2] i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

From: Ian Romanick Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid range of the offset is [0, 0FFFh]. Signed-off-by: Ian Romanick Cc: mesa-sta...@lists.freedesktop.org Cc: Kenneth Graunke --- src/intel/compiler/brw_vec4_tes.cpp | 12 +++- 1 file changed, 11

[Mesa-dev] [PATCH 1/2] i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset

From: Ian Romanick Fixes failure in the new piglit test tes-patch-input-array-vec2-index-invalid-rd.shader_test. Signed-off-by: Ian Romanick Cc: mesa-sta...@lists.freedesktop.org Cc: Kenneth Graunke --- src/intel/compiler/brw_vec4_generator.cpp | 15 ++- 1 file changed, 14

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 --- Comment #3 from Mark Janes --- Vadym, can you make a piglit test for this bug? -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #16 from Samuel Pitoiset --- Yeah, it was just a workaround for a weird issue but I fixed it since. I'm improving the patch for supporting cull distances as well. -- You are receiving this mail because: You are the QA Contact for

[Mesa-dev] [PATCH] radv: fix passing clip distances from VS to FS

CTS doesn't test input clip distances with the fragment shader stage, which explains why it was broken. I wrote a simple test locally that does pass now. I'm quite sure that cull distances are broken as well but that can be fixed later. This fixes a crash with GTA V and DXVK. Cc:

[Mesa-dev] [PATCH 1/5] i965/vec4: Silence unused parameter warnings in vec4 compiler tests

From: Ian Romanick src/intel/compiler/test_vec4_copy_propagation.cpp: In member function ‘virtual brw::dst_reg* copy_propagation_vec4_visitor::make_reg_for_system_value(int)’: src/intel/compiler/test_vec4_copy_propagation.cpp:57:51: warning: unused parameter ‘location’ [-Wunused-parameter]

[Mesa-dev] [PATCH 5/5] i965/vec4: Propagate conditional modifiers from more compares to other compares

From: Ian Romanick If there is a CMP.NZ that compares a single component (via a . swizzle, for example) with 0, it can propagate its conditional modifier back to a previous CMP that writes only that component. The specific case that I saw was: cmp.l.f0(8) g42<1>.xF g61<4>.xF

[Mesa-dev] [PATCH 2/5] i965/vec4/dce: Don't narrow the write mask if the flags are used

From: Ian Romanick In an instruction sequence like cmp(8).ge.f0.0 vgrf17:D, vgrf2.:D, vgrf9.:D (+f0.0) sel(8) vgrf1:UD, vgrf8.xyzw:UD, vgrf1.xyzw:UD The other fields of vgrf17 may be unused, but the CMP still needs to generate the other flag bits. To my surprise,

[Mesa-dev] [RESEND PATCH 0/5] i965: More cmod propagation

This is mostly a resend of a series that I originally sent out around the end of June. I updated some of the shader-db results, and I dropped one patch (i965/fs: Allow Boolean conditions in CSEL generation). I decided that I want to try to acomplish that with a different method. That's going to

[Mesa-dev] [PATCH 4/5] i965/fs: Relax type matching rules in cmod propagation from MOV instructions

From: Ian Romanick To allow cmod propagation from a MOV in a sequence like: and(16) g31<1>UD g20<8,8,1>UD g22<8,8,1>UD mov.nz.f0(16) null<1>F g31<8,8,1>D A similar change to the vec4 backend had no effect. Somewhere between c1ec5820593 and 40fc4b5acd6 (1,094

[Mesa-dev] [PATCH 3/5] i965/fs: Eliminate unary op on operand of compare-with-zero

From: Ian Romanick All Gen7+ platforms had similar results. (Broadwell shown) total instructions in shared programs: 14715715 -> 14715709 (<.01%) instructions in affected programs: 474 -> 468 (-1.27%) helped: 6 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 1.12%

Re: [Mesa-dev] [PATCH 1/2] st/nine: do not double-close the fd on teardown

Hi Emil, This patch and the nine part of the second patch look fine. Reviewed-by: Axel Davy for them. Yours, Axel On 29/08/2018 19:13, Emil Velikov wrote: From: Emil Velikov As the newly introduced comment says: The pipe loader takes ownership of the fd Thus, there's no need to close

Re: [Mesa-dev] [PATCH 2/2] pipe-loader: move dup(fd) within pipe_loader_drm_probe_fd

Hi, Emil, On 08/29/2018 07:13 PM, Emil Velikov wrote: From: Emil Velikov Currently pipe_loader_drm_probe_fd takes ownership of the fd given. To match that, pipe_loader_release closes it. Yet we have many instances which do not want the change of ownership, and thus duplicate the fd before

Re: [Mesa-dev] [PATCH v3] intel/tools: new i965_disasm tool

Looks great! Reviewed-by: Matt Turner and pushed. Thanks a bunch! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] glsl: skip stringification in preprocessor if in unreachable branch

On 08/28/2018 06:36 PM, Timothy Arceri wrote: > This fixes compilation of some "No Mans Sky" shaders where the stringification > happens in branches intended for DX12. I was going to complain that this would make things like the following compile: #version 110 #ifdef this_is_undefined

[Mesa-dev] [PATCH v3] intel/tools: new i965_disasm tool

Adds a new i965 instruction disassemble tool v2: 1) fix a few nits (Matt Turner) 2) Remove i965_disasm header (Matt Turner) v3: 1) Redirect output to correct file descriptors (Matt Turner) 2) Refactor code (Matt Turner) 3) Use better formatting style (Matt Turner) Signed-off-by:

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #15 from Clément Guérin --- I haven't found the time to test it yet. Is forcing `output_usage_mask` at line 71 intentional? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

Re: [Mesa-dev] [PATCH v2 14/22] intel/compiler: Do image load/store lowering to NIR

On Wednesday, August 29, 2018 10:11:48 AM PDT Jason Ekstrand wrote: > This commit moves our storage image format conversion codegen into NIR > instead of doing it in the back-end. This has the advantage of letting > us run it through NIR's optimizer which is pretty effective at shrinking > things

Re: [Mesa-dev] [PATCH v2 21.5/22 (was 18/22)] intel: Use TXS for image_size when we have a typed surface

On Wednesday, August 29, 2018 10:12:59 AM PDT Jason Ekstrand wrote: > --- > src/intel/compiler/brw_eu_defines.h | 2 ++ > src/intel/compiler/brw_fs_generator.cpp | 23 +--- > src/intel/compiler/brw_fs_nir.cpp | 35 +++ >

[Mesa-dev] [PATCH] anv: Use separate MOCS settings for external BOs on gen8

On all other platforms, it's safe to use the usual PTE settings for both internal and external BOs. On Broadwell, however, we can't get the right caching behavior for scanout without disabling eLLC and we really don't want to do this on everything. In order to do this, we add an anv-specific BO

[Mesa-dev] [PATCH] anv: Re-emit vertex buffers when the pipeline changes

Some of the bits of VERTEX_BUFFER_STATE such as access type, instance data step rate, and pitch come from the pipeline. Cc: mesa-sta...@lists.freedesktop.org --- src/intel/vulkan/genX_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c

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