itching back to the 3D pipeline.
Yep, this is the way it is.
Reviewed-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
> src/mesa/drivers/dri/i965/brw_misc_state.c | 38
> ++
> src/
On 12/10/2015 06:23 AM, Jason Ekstrand wrote:
> While we're at it, we also add support for the possibility that the
> indirect is, in fact, a constant. This shouldn't happen in the common case
> (if it does, that means NIR failed to constant-fold something), but it's
> possible so we should
On 12/07/2015 04:45 PM, Ilia Mirkin wrote:
> On Mon, Dec 7, 2015 at 7:39 AM, Abdiel Janulgue
> <abdiel.janul...@linux.intel.com> wrote:
>> v2 (Francisco Jerez):
>>- Rename HSW_GATHER_CONSTANTS_RESERVED to
>> HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
>
v2 (Francisco Jerez):
- Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
- Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANTS_*.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_defines.
const int output_vertex_size_owords =
> gs_prog_data->output_vertex_size_hwords * 2;
>
> - fs_reg offset;
>if (gs_vertex_count.file == IMM) {
> per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
>
ine function presumably improved icache usage.
>
> Improves performance of Gl32Batch7 by 3.39898% +/- 0.358674% (n=155) on
> Ivybridge.
> ---
> I'll try to get benchmark results on other platforms as well.
Patch is Reviewed-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
&
t; +#define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES(512*64)
> +#define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES(512*64)
> +
> /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
> * (128 bytes) URB rows and the maximum allowed value is
;
> - Application calls the meta function again, and the meta function
>replaces the data. The application's data is lost, and the app
>fails. Have fun debugging that.
>
> Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
> Bugzilla: https://bugs.freedesktop.o
@@ _mesa_attr_zero_aliases_vertex(struct gl_context *ctx)
> && !is_forward_compatible_context));
> }
>
> +extern void
> +_mesa_bind_vertex_buffer(struct gl_context *ctx,
> + struct gl_vertex_array_object *vao,
> +
to be careful.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Patches 1-4 are
Reviewed-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 10/27/2015 03:18 PM, Francisco Jerez wrote:
> Francisco Jerez <curroje...@riseup.net> writes:
>
>> Abdiel Janulgue <abdiel.janul...@linux.intel.com> writes:
>>
>>> Use the gather table generated from the uniform uploads and
>>> ir_binop_ubo_loa
Ping! No thoughts/consensus if this approach is worth considering or
not? The patches are getting stale. Should I re-base or just discard
these optimisations?
On 09/15/2015 08:59 PM, Ben Widawsky wrote:
> On Tue, Sep 15, 2015 at 12:24:00PM +0300, Abdiel Janulgue wrote:
>> Here
Here's a more comprehensive shader-db run:
total instructions in shared programs: 6394485 -> 6374865 (-0.31%)
instructions in affected programs: 261322 -> 241702 (-7.51%)
helped:3210
HURT: 0
GAINED:
On 09/12/2015 01:42 AM, Ben Widawsky wrote:
> On Fri, Sep 11, 2015 at 11:33:14AM +0300, Abdiel Janulgue wrote:
>> Some updated figures first:
>>
>> Ue4 Reflections Subway demo
>> x fs gather constants disabled
>> + fs gather constants enabled
>>
>&
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/glsl/nir/nir_types.cpp | 6 ++
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index a0caf0e..332da8f 100644
--- a/src/gl
Assign the uploaded uniform block with hardware binding table indices.
This is indexed by the resource streamer to fetch the constant buffers
referred to by our gather table entries.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen6_vs_s
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 12
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dr
Reserve space in the gather pool where the gathered uniforms are flushed.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 11 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 ++
2 files changed, 17 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/sr
When the const block and offset are immediate values. Otherwise just
fall-back to the previous method of uploading the UBO constant data to
GRF using pull constants.
Cc: kenn...@whitecape.org
Cc: ja...@jlekstrand.net
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
sr
Now that we consider UBO constants as push constants, we need to include
the sizes of the UBO's constant slots in the visitor's uniform slot sizes.
This information is needed to properly pack vector constants tightly next to
each other.
Signed-off-by: Abdiel Janulgue <abdiel.ja
We now have two sources of constant buffers: UBOs and ordinary uniforms.
After assigning a block of push constant hw-register to normal uniforms,
just pack the UBO push constant registers right after it.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drive
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/glsl/nir/nir_types.cpp | 6 ++
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index 940c676..a0caf0e 100644
--- a/src/gl
support.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 59 ++
src/mesa/drivers/dri/i965/brw_context.c| 39 -
src/mesa/drivers/dri/i965/brw_context.h| 10 +
src/mesa/d
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index a8594af..7b07c50
Some updated figures first:
Ue4 Reflections Subway demo
x fs gather constants disabled
+ fs gather constants enabled
HSW:
N Min MaxMedian AvgStddev
x 10 5.09739 6.48963 6.33357 6.1979850.40742969
+ 10 6.56139
Now that UBOs are uploaded as push constants. We need to obtain and
append the amount of push constant entries generated by the UBO entry
fetches to the 3DSTATE_CONSTANT_* packets.
v2: GEN8 support
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dr
of the dynamic state base address.
v2: Support GEN8 + non-trivial rebase.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +
When the const block and offset are immediate values. Otherwise just
fall-back to the previous method of uploading the UBO constant data to
GRF using pull constants.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_vec4.cpp
This patch generates the gather table entries for ordinary uniforms
if they are present. The uniform constants here will later be packed
together with UBO constants.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.cp
If there are UBO constant entries, append them to stage_state->push_const_size.
The gather pool contains the combined entries of both ordinary uniforms
and UBO constants.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen6_vs_sta
to go around the issue.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen7_disable.c | 4
src/mesa/drivers/dri/i965/gen7_vs_state.c | 7 +++
src/mesa/drivers/dri/i965/gen8_disable.c | 4
3 files changed, 15 insertions(+)
diff
Switches on push constants whenever we have UBO entries.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Since we now consider UBOs as push constants, we need to layout
our push constant register space in such a way that UBO registers
are packed right after uniform registers.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_vec4.cp
On 08/26/2015 08:19 PM, Ian Romanick wrote:
From: Ian Romanick ian.d.roman...@intel.com
All of the other state upload functions are static because the only use
is in the brw_tracked_state structure.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
This patch is
Reviewed-by: Abdiel
On 07/17/2015 01:38 AM, Kenneth Graunke wrote:
On Friday, July 03, 2015 10:00:30 AM Abdiel Janulgue wrote:
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying
On 07/17/2015 05:41 AM, Kenneth Graunke wrote:
+static uint32_t
+reserve_hw_bt_space(struct brw_context *brw, unsigned bytes)
+{
+ if (brw-hw_bt_pool.next_offset + bytes = brw-hw_bt_pool.bo-size -
128) {
Why -128? I don't see why we should have to subtract anything...
This is
On 07/17/2015 05:26 AM, Kenneth Graunke wrote:
On Tuesday, July 07, 2015 11:50:21 AM Abdiel Janulgue wrote:
+void
+gen7_disable_hw_binding_tables(struct brw_context *brw)
+{
+ if (!brw-use_resource_streamer)
+ return;
+
+ int pkt_len = brw-gen = 8 ? 4 : 3;
+
+ BEGIN_BATCH
...@whitecape.org
Cc: matts...@gmail.com
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 64 ++
1 file changed, 55 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c
b/src
overflow when allocating a chunk out of the
hw-binding table pool (Ken).
v3: Remove extra newline and add missing brace around if-statement (Matt).
Cc: kenn...@whitecape.org
Cc: matts...@gmail.com
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965
-generated binding tables and the previous sw-binding
table GPU state (Chris).
Cc: kenn...@whitecape.org
Cc: syrj...@sci.fi
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 96
On 07/06/2015 01:33 PM, Chris Wilson wrote:
+/*
+ * Add a relocation entry for the target buffer into the current batch.
+ *
+ * This is the heart of performing fast relocations, both here and in
+ * the corresponding kernel relocation routines.
+ *
+ * - Instead of passing in handles
On 07/07/2015 01:19 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 01:14:53PM +0300, Abdiel Janulgue wrote:
On 07/06/2015 01:33 PM, Chris Wilson wrote:
@@ -600,7 +593,10 @@ brw_emit_null_surface_state(struct brw_context *brw,
1 BRW_SURFACE_WRITEDISABLE_B_SHIFT
On 07/03/2015 12:20 PM, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 10:00:31AM +0300, Abdiel Janulgue wrote:
+void
+gen7_enable_hw_binding_tables(struct brw_context *brw)
+{
+ if (!brw-use_resource_streamer)
+ return;
+
+ if (!brw-hw_bt_pool.bo) {
+ /* We use a single re
overflow when allocating a chunk out of the
hw-binding table pool (Ken).
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 73 --
1 file changed, 57 insertions(+), 16 deletions
redundant devinfo-has_resource_streamer check in context create
into init screen.
Cc: kenn...@whitecape.org
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 4
src/mesa/drivers/dri/i965
-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 96 ++
src/mesa/drivers/dri/i965/brw_context.c| 4 ++
src/mesa/drivers/dri/i965/brw_context.h| 6 ++
src/mesa/drivers/dri/i965/brw_state.h | 6
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue
On 06/26/2015 11:19 AM, Ville Syrjälä wrote:
On Fri, Jun 26, 2015 at 08:51:59AM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each
On 06/26/2015 10:55 AM, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 08:52:01AM +0300, Abdiel Janulgue wrote:
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding
On 06/26/2015 02:17 PM, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 01:59:17PM +0300, Abdiel Janulgue wrote:
On 06/26/2015 10:55 AM, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 08:52:01AM +0300, Abdiel Janulgue wrote:
When hardware-generated binding tables are enabled, use the hw-generated
On 06/26/2015 10:46 AM, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 08:51:59AM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each
-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 96 ++
src/mesa/drivers/dri/i965/brw_context.c| 4 ++
src/mesa/drivers/dri/i965/brw_context.h| 6 ++
src/mesa/drivers/dri/i965/brw_state.h | 6
-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 30 ++
src/mesa/drivers/dri/i965/intel_reg.h | 3 +++
2 files changed, 33 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965
...@whitecape.org
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 5 +
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_device_info.c | 5 -
src/mesa/drivers
overflow when allocating a chunk out of the
hw-binding table pool (Ken).
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 73 --
1 file changed, 57 insertions(+), 16 deletions
...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 55 ++
src/mesa/drivers/dri/i965/brw_state.h | 9 +
2 files changed, 64 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue
offset above.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 87 ++
src/mesa/drivers/dri/i965/brw_context.c| 4 ++
src/mesa/drivers/dri/i965/brw_context.h| 6
Time for another rebase, yet again. My previous patches were getting stale...
Changes since last posting:
- Always inspect the getparam.value in the I915_PARAM_HAS_RESOURCE_STREAMER
ioctl as suggested by Chris Wilson.
___
mesa-dev mailing list
if kernel
supports RS (Ken).
- Add brw_device_info::has_resource_streamer and toggle it for
Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue
On 06/16/2015 03:20 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 03:08:56PM +0300, Abdiel Janulgue wrote:
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue
-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 87 ++
src/mesa/drivers/dri/i965/brw_context.c| 4 ++
src/mesa/drivers/dri/i965/brw_context.h| 6 ++
src/mesa/drivers/dri/i965/brw_state.h
offset above in disable_stages().
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 87 ++
src/mesa/drivers/dri/i965/brw_context.c| 4 ++
src/mesa/drivers/dri/i965
overflow when allocating a chunk out of the
hw-binding table pool (Ken).
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 73 --
1 file changed, 57 insertions(+), 16 deletions
if kernel
supports RS (Ken).
- Add brw_device_info::has_resource_streamer and toggle it for
Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.c
= INTEL_MIPTREE_TRMODE_NONE;
+ intel_miptree_set_alignment(brw, mt);
intel_miptree_set_total_width_height(brw, mt);
if (!mt-total_width || !mt-total_height) {
Patches 1, 3, and 4 are
Reviewed-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
Thanks a lot Ken! Your help in debugging this pointed me in the right
direction! I had some further observations below:
On 06/09/2015 11:08 AM, Kenneth Graunke wrote:
(To bring the mailing list up to speed: Abdiel mentioned on IRC tonight
that this is actually still necessary---some Piglit
:
On Wed, Jun 03, 2015 at 10:05:25AM +0300, Abdiel Janulgue wrote:
On 06/02/2015 08:28 PM, Kenneth Graunke wrote:
On Tuesday, June 02, 2015 03:23:35 PM Abdiel Janulgue wrote:
On 06/02/2015 09:31 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote
On 06/02/2015 10:54 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:26 PM Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each
On 06/02/2015 08:28 PM, Kenneth Graunke wrote:
On Tuesday, June 02, 2015 03:23:35 PM Abdiel Janulgue wrote:
On 06/02/2015 09:31 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote:
This is needed since kernel doesn't support RS context save and
restore
On 06/02/2015 11:25 AM, Kenneth Graunke wrote:
On Tuesday, June 02, 2015 12:58:29 AM Kenneth Graunke wrote:
As I mentioned in my reply to patch 3, I think you need some sort of
did the buffer fill up? check. Perhaps make a function to reserve
space, advancing next_offset and returning the
On 06/02/2015 11:05 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote:
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc: kenn
On 06/02/2015 09:31 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote:
This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated binding tables
when done using it in the batch. Otherwise the GPU
.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: Clarify start of binding table pool offsets. (Topi)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 101
driver.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 11 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965
state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base
address.
Signed-off-by: Abdiel
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc: kenn...@whitecape.org
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Abdiel Janulgue abdiel.janul
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 +++-
2 files changed, 8
the state for these combined edits which it then automatically
flushes to a binding table pool when the binding table pointer state
command is invoked.
v2: Clarify binding table edit bit aligment. (Topi)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
On 05/20/2015 09:47 AM, Pohjolainen, Topi wrote:
On Wed, May 20, 2015 at 09:32:06AM +0300, Abdiel Janulgue wrote:
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 24
the state for these combined edits which it then automatically
flushes to a binding table pool when the binding table pointer state
command is invoked.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 50
.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 97 ++
src/mesa/drivers/dri/i965/brw_context.c
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 +++-
2 files changed, 8
state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base
address.
Signed-off-by: Abdiel
I've decided to split my gather constants work into even smaller chunks
to make it easier for reviewers which in turn makes it easier to merge.
First in this patch series enables hardware-generated binding tables
which is required for gather constants[*] to work.
Chances since previous posting
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 24
src/mesa/drivers/dri/i965/intel_reg.h | 3 +++
2 files changed, 27 insertions(+)
diff --git a/src
On 05/20/2015 09:54 AM, Pohjolainen, Topi wrote:
On Wed, May 20, 2015 at 09:32:08AM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed
On 05/20/2015 10:21 AM, Pohjolainen, Topi wrote:
On Wed, May 20, 2015 at 10:11:36AM +0300, Abdiel Janulgue wrote:
On 05/20/2015 09:54 AM, Pohjolainen, Topi wrote:
On Wed, May 20, 2015 at 09:32:08AM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which
.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: Clarify start of binding table pool offsets. (Topi)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 95
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 +++-
2 files changed, 8
the state for these combined edits which it then automatically
flushes to a binding table pool when the binding table pointer state
command is invoked.
v2: Clarify binding table edit bit aligment. (Topi)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965
v2: Simply HW binding table bit definitions and magic constants (Topi)
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 28
src/mesa/drivers/dri/i965
state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base
address.
Signed-off-by: Abdiel
On 05/07/2015 05:46 PM, Pohjolainen, Topi wrote:
On Thu, May 07, 2015 at 04:43:21PM +0300, Pohjolainen, Topi wrote:
On Tue, Apr 28, 2015 at 11:08:00PM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool
On 05/07/2015 06:17 PM, Pohjolainen, Topi wrote:
On Tue, Apr 28, 2015 at 11:08:08PM +0300, Abdiel Janulgue wrote:
The resource streamer is able to gather and pack sparsely-located
constant data from any buffer object by a referring to a gather table
This patch adds support for keeping track
On 05/07/2015 05:48 PM, Pohjolainen, Topi wrote:
On Tue, Apr 28, 2015 at 11:08:23PM +0300, Abdiel Janulgue wrote:
Programming null constants with gather constant tables seems to
be unsupported and results in a GPU lockup even with the prescribed
GPU workarounds in the bspec. Found out
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