[Mesa-dev] [PATCH] i965/bxt: Fix conservative wm thread counts.

sta...@lists.freedesktop.org> Cc: Kenneth Graunke <kenn...@whitecape.org> Cc: Neil Roberts <n...@linux.intel.com> Cc: Mark Janes <mark.a.ja...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_device_info.c | 2 +- 1 f

[Mesa-dev] [PATCH] i965/fs: Remove unused count from vs urb setup

.@whitecape.org> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 6 -- 1 file changed, 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 05f335e..cbeab6f 100644 --- a/s

Re: [Mesa-dev] [RFC PATCH] mesa: Add MESA_SHADER_CAPTURE_PATH for writing .shader_test files.

On Mon, Jan 18, 2016 at 07:05:21AM -0800, Kenneth Graunke wrote: > This writes linked shader programs to .shader_test files to > $MESA_SHADER_CAPTURE_PATH in the format used by shader-db > (http://cgit.freedesktop.org/mesa/shader-db). > > It supports both GLSL shaders and ARB programs. All

Re: [Mesa-dev] [PATCH 2/2] i965: Implement compute sampler state atom.

On Mon, Jan 18, 2016 at 12:37:18PM -0800, Francisco Jerez wrote: > Fixes a number of GLES31 CTS failures and hangs on various hardware: > > ES31-CTS.texture_gather.plain-gather-depth-2d > ES31-CTS.texture_gather.plain-gather-depth-2darray > ES31-CTS.texture_gather.plain-gather-depth-cube >

[Mesa-dev] [PATCH] i965: Remove unused hw_must_use_separate_stencil

I spotted this while looking for what needs updating in future platforms. I'm too lazy to go through the git logs, but it was probably missed by Jason when all the brw refactoring happened. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_con

[Mesa-dev] [PATCH 1/2] i965: Make feature macros gen8 based

All the "features" of the hardware are similar starting with GEN8, so remove as much of the GEN9 uniqueness as possible. This makes implementing future gen platforms a bit easier. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_de

[Mesa-dev] [PATCH 2/2] i965: Put the gt and slice count in the features macro

information like we have for BXT. This patch is just a preference of mine, so if people are opposed it doesn't need to get merged. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_device_info.c | 25 ++--- 1 file changed, 10 insertions(

Re: [Mesa-dev] [PATCH] i965: Add tr_mode and mip tail information in surface state dump

On Wed, Dec 23, 2015 at 12:09:44PM -0800, Anuj Phogat wrote: > Cc: Ben Widawsky <b...@bwidawsk.net> > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> > --- > src/mesa/drivers/dri/i965/brw_state_dump.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-)

[Mesa-dev] [PATCH] i965: Only apply CS stall workaround pre-SKL

As per the docs. Cc: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_cont

Re: [Mesa-dev] [PATCH 0/5] i965/gen9: Support fast clear on SRGB buffers

atches are in a branch here: > > https://github.com/bpeel/mesa/commits/skl-fast-clear > -- Ben Widawsky, Intel Open Source Technology Center ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/5] i965/gen8+: Don't upload the MCS buffer for single-sampled textures

;num_samples > 1) { >aux_mt = mt->mcs_mt; >aux_mode = GEN8_SURFACE_AUX_MODE_MCS; > -- Ben Widawsky, Intel Open Source Technology Center ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 5.5/42] i965: Add slice count to the brw_device_info structure.

The most important feedback I have on the patch is that we continue to add stuff like this for compute when there is a libdrm interface which exposes all or most of it - and that interface should either be expanded or removed. FWIW, I wasn't a big fan of the interface when it was introduced, but

Re: [Mesa-dev] [PATCH v2 1/2] mesa: Add KBL PCI IDs and platform information.

On Fri, Nov 20, 2015 at 02:18:56PM +, Emil Velikov wrote: > On 18 November 2015 at 21:59, Ilia Mirkin wrote: > > On Wed, Nov 18, 2015 at 4:54 PM, Sarah Sharp > > wrote: > >>> There's not really a consensus I guess, but most people do leave

Re: [Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

On Fri, Nov 20, 2015 at 11:02:43AM -0800, Chad Versace wrote: > On Wed 18 Nov 2015, Ben Widawsky wrote: > > On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote: > > > On Tue 17 Nov 2015, Ben Widawsky wrote: > > > > Background: Prior to Skylake and since Iv

Re: [Mesa-dev] [PATCH 2/5] i965/gen8: Allow rendering to B8G8R8X8

BTW, I pointed this out to Nanley, but I didn't see a patch, I think we need to add is_braswell (and maybe broxton)) to the gen += 5 at the top of this function. lgtm Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 5/5] i965/gen9: Don't allow the RGBX formats for texturing/rendering

On Thu, Nov 19, 2015 at 04:25:21PM +0100, Neil Roberts wrote: > The RGBX surface formats aren't renderable so we internally remap them > to RGBA when rendering. They are retained as RGBX when used as > textures. However since the previous patch fast clears are disabled > for surfaces that use a

Re: [Mesa-dev] [PATCH 1/5] i965/gen9: Don't disallow fast clear for MSRT formats matching render

orget, did you find failures for this in the non-MSRT case? If not, maybe we could skip this patch and just take the rest of the series? That way we can avoid the "perf regression" of RGBX clears which we do hit on certain workloads. Assuming we have a failure in non-MSRT case, and we can't just bypass this patch, this is: Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/5] i965: Check base format to determine whether to use tiled memcpy

On Thu, Nov 19, 2015 at 04:25:19PM +0100, Neil Roberts wrote: > The tiled memcpy doesn't work for copying from RGBX to RGBA because it > doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added > a check to disable it for RGBX formats by looking at the TexFormat. > However a lot of

Re: [Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

On Wed, Nov 18, 2015 at 03:50:32PM -0800, Ben Widawsky wrote: > On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote: > > On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote: > > > Background: Prior to Skylake and since Ivybridge Inte

Re: [Mesa-dev] [PATCH] [v3] i965/skl: skip fast clears for certain surface formats

On Wed, Nov 18, 2015 at 12:15:40PM +0200, Pohjolainen, Topi wrote: > On Tue, Nov 17, 2015 at 05:31:12PM -0800, Ben Widawsky wrote: > > Some of the information originally in this commit message is now in the > > patch > > before this. > > > > SKL adds compressib

Re: [Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote: > On Tue 17 Nov 2015, Ben Widawsky wrote: > > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > > ability to use a MCS (Multisample Control Surface) as auxiliary data in > > &qu

Re: [Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote: > On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote: > > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > > ability to use a MCS (Multisample Control Surface) as

Re: [Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote: > On Tue 17 Nov 2015, Ben Widawsky wrote: > > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > > ability to use a MCS (Multisample Control Surface) as auxiliary data in > > &qu

Re: [Mesa-dev] [PATCH 05/36] i965: Import tables enumerating the set of validated L3 configurations.

On Sat, Nov 14, 2015 at 01:43:41PM -0800, Jordan Justen wrote: > From: Francisco Jerez > > It should be possible to use additional L3 configurations other than > the ones listed in the tables of validated allocations ("BSpec » > 3D-Media-GPGPU Engine » L3 Cache and URB

[Mesa-dev] [PATCH] [v2] i965: Add lossless compression to surface format table

n Requested-by: Chad - change meaning of brw_losslessly_compressible_format Requested-by: Chad - related changes to the code to reflect this. - remove excess ccs (Chad) Requested-by: Chad Versace <chad.vers...@intel.com> Requested-by: Neil Roberts <n...@linux.intel.com> Signed-off-

[Mesa-dev] [PATCH] [v3] i965/skl: skip fast clears for certain surface formats

ven look at it since Chad said he was fine with that, and presumably Matt is fine with it. Cc: Chad Versace <chad.vers...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_surface_formats.c | 52 - src/mesa/drivers/dri/

[Mesa-dev] [PATCH 7/7] [v2] i965/gen9: Support fast clears for 32b float

they are now handled by Neil's patch to disable MSAA fast clears. Cc: Neil Roberts <n...@linux.intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++-- src/mesa/drivers/dri/i965/gen8_surface_state.c | 8 2 file

Re: [Mesa-dev] [PATCH v2] i965: Implement ARB_pipeline_statistics_query tessellation counters.

On Tue, Nov 17, 2015 at 11:28:25AM -0800, Kristian Høgsberg wrote: > On Tue, Nov 17, 2015 at 11:25 AM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > We basically just need to uncomment Ben's code. > > Reviewed-by: Kristian Høgsberg <k...@bitplanet.net>

Re: [Mesa-dev] [PATCH v2 1/2] mesa: Add KBL PCI IDs and platform information.

at the various fields mean. > > Signed-off-by: Sarah Sharp <sarah.a.sh...@linux.intel.com> > Suggested-by: Ben Widawsky <benjamin.widaw...@intel.com> > Tested-by: Rodrigo Vivi <rodrigo.v...@intel.com> (KBL-GT2) > --- > > v2: > - reorder the PCI IDs > - re

Re: [Mesa-dev] [PATCH 2/2] intel/kbl: Add Kabylake PCI ids

d)) > + The actual correct breakdown IMO (and the encoding going back to bdw) is nibble #1 represents the GT#. ie 590x = gt1 591x = gt2 592x = gt3 593x = gt4 This doesn't match how it's done here (the fuse parts are rounded down instead of up, like gt 1.5),

Re: [Mesa-dev] [PATCH 3/7] [v2] i965/skl: skip fast clears for certain surface formats

On Fri, Nov 13, 2015 at 12:22:47PM -0800, Chad Versace wrote: > On Wed 11 Nov 2015, Ben Widawsky wrote: > > Some of the information originally in this commit message is now in the > > patch > > before this. > > > > SKL adds compressible render tar

Re: [Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

On Fri, Nov 13, 2015 at 12:29:47PM -0800, Chad Versace wrote: > On Wed 11 Nov 2015, Ben Widawsky wrote: > > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > > ability to use a MCS (Multisample Control Surface) as auxiliary data in > > &qu

[Mesa-dev] [PATCH] i965: Add assertion for src_stencil payload size

This helps address a coverity warning and prevents future questions about this code. Reported-by: Coverity (via Ilia) Cc: Matt Turner <matts...@gmail.com> Cc: Ilia Mirkin <imir...@alum.mit.edu> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i

Re: [Mesa-dev] [PATCH 4/7] [v2] i965/meta/gen9: Individually fast clear color attachments

to keep your patch as > it is it's up to you. Thanks a lot, I will squash it in - and sorry again about ignoring your feedback. > > Regards, > - Neil > > Ben Widawsky <benjamin.widaw...@intel.com> writes: [snip] ___ mesa-dev ma

Re: [Mesa-dev] [PATCH v2] i965: Handle lum, intensity and missing components in the fast clear

bably be nice to track down a good spec reference if you manage to find one. I know I've seen such reference in SKL docs (which aren't SKL specific) - but I am having trouble finding it in PRMs. My VPN is broken, so I can't look at SKL docs right now. With the explanation of why the luminance alpha channel isn't 1 (I also claim incompotence on the GL_LUMINANCE_ALPHA format): Reviewed-by: Ben Widawsky <benjamin.widaw...@intel.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Disable fast clears for MSRTs on SKL

if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS) > clear_type = REP_CLEAR; > (Perhaps "Disable fast clears..." is a misleading title because it doesn't really disable them. A note that this patch should have no functional effect other than pe

[Mesa-dev] [PATCH] i965/skl: Disable fast clear for formats without alpha

--- Here is one proposal to fix the issue. I noticed that only formats without alpha were failing. This sucks for RGBX formats (which technically aren't fast clearable based on the surface format). The hunk for moving the format should happen regardless of this patch. Neil has another patch

Re: [Mesa-dev] [PATCH 7/7] [v2] i965/gen9: Support fast clears for 32b float

On Thu, Nov 12, 2015 at 11:39:25AM +0100, Neil Roberts wrote: > Ben Widawsky <benjamin.widaw...@intel.com> writes: > > > Two formats are explicitly disabled because they fail piglit tests, > > LUMINANCE16F and INTENSITY16F. There is some question about the >

Re: [Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

On Wed, Nov 11, 2015 at 02:10:57PM -0800, Ben Widawsky wrote: > This subject used to say Add lossless compression to surface format TO table > > somehow, "to" got dropped. It's fixed locally. > Ignore this, subject looks fine to me an

[Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

nrelated to enabling this on GEN9, it becomes somewhat tricky to implement because of the fact that surface format support diminishes. You'd probably want another column to cleanly implement it. Requested-by: Chad Versace <chad.vers...@intel.com> Requested-by: Neil Roberts <n...@linux.

[Mesa-dev] [PATCH 1/7] [v2] i965/skl: Add fast color clear infrastructure

lt;chad.vers...@linux.intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> Reviewed-by: Neil Roberts <n...@linux.intel.com> --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 55 ++--- src/mesa/drivers/dri/i965/gen8_surface_state.c | 16 ++- src/mesa/drivers/d

[Mesa-dev] [PATCH 4/7] [v2] i965/meta/gen9: Individually fast clear color attachments

the mt (Chad) Cc: Chad Versace <chad.vers...@linux.intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 94 + 1 file changed, 81 insertions(+), 13 deletions(-) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH 0/7] [v2] Gen9 MCS buffers

<chad.vers...@linux.intel.com> Ben Widawsky (7): i965/skl: Add fast color clear infrastructure i965: Add lossless compression to surface format table i965/skl: skip fast clears for certain surface formats i965/meta/gen9: Individually fast clear color attachments Revert "i965/gen

[Mesa-dev] [PATCH 3/7] [v2] i965/skl: skip fast clears for certain surface formats

Cc: Neil Roberts <n...@linux.intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_surface_formats.c | 52 - src/mesa/drivers/dri/i965/gen8_surface_state.c | 7 +++- 2 files changed, 31 insertions(+), 28 d

[Mesa-dev] [PATCH 5/7] Revert "i965/gen9: Disable MCS for 1x color surfaces"

This reverts commit dcd59a9e322edeea74187bcad65a8e56c0bfaaa2. Reviewed-by: Neil Roberts --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 1 file changed, 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 6/7] Revert "i965/gen9: Enable rep clears on gen9"

This reverts commit 8a0c85b25853decb4a110b6d36d79c4f095d437b. It's not a strict revert because I don't want to bring back the gen < 9 check at this point in time. Reviewed-by: Neil Roberts --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 - 1 file changed, 5

[Mesa-dev] [PATCH 7/7] [v2] i965/gen9: Support fast clears for 32b float

t;n...@linux.intel.com Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 12 ++-- src/mesa/drivers/dri/i965/gen8_surface_state.c | 8 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers

Re: [Mesa-dev] [PATCH 2/7] i965: Add lossless compression to surface format table

This subject used to say Add lossless compression to surface format TO table somehow, "to" got dropped. It's fixed locally. On Wed, Nov 11, 2015 at 02:06:16PM -0800, Ben Widawsky wrote: > Background: Prior to Skylake and since Ivybridge Intel hardware has had the > abil

Re: [Mesa-dev] [PATCH] i965: Implement ARB_pipeline_statistics_query tessellation counters.

On Mon, Nov 09, 2015 at 11:59:43PM -0800, Kenneth Graunke wrote: > We basically just need to uncomment Ben's code. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/gen6_queryobj.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > >

Re: [Mesa-dev] [PATCH 04/10] i965/skl: skip fast clears for certain surface formats

There is one thing I need a response on at the very bottom, the rest will be addressed in v2. Thanks. On Mon, Nov 09, 2015 at 11:33:17AM -0800, Chad Versace wrote: > On Tue 03 Nov 2015, Ben Widawsky wrote: > > On Fri, Oct 16, 2015 at 04:05:22PM -0700, Chad Versace wrote: > > >

Re: [Mesa-dev] [PATCH 09/10] i965/meta: Remove fast_clear_color variable

On Wed, Oct 14, 2015 at 08:16:54AM -0700, Ben Widawsky wrote: > On Wed, Oct 14, 2015 at 11:52:03AM +0200, Neil Roberts wrote: > > This patch doesn't look right. See this sentence in “Render Target Fast > > Clear”: > > > > “The pixel shader kernel requires no attri

Re: [Mesa-dev] [PATCH] i965/skl/gt4: Fix URB programming restriction.

On Mon, Nov 09, 2015 at 11:50:25AM -0800, Kenneth Graunke wrote: > On Saturday, November 07, 2015 08:40:51 AM Ben Widawsky wrote: > > On Fri, Nov 06, 2015 at 07:29:18PM -0800, Kenneth Graunke wrote: > > > On Friday, November 06, 2015 06:12:27 PM Ben Widawsky wrote: > > >

Re: [Mesa-dev] [PATCH] i965/skl/gt4: Fix URB programming restriction.

On Fri, Nov 06, 2015 at 07:29:18PM -0800, Kenneth Graunke wrote: > On Friday, November 06, 2015 06:12:27 PM Ben Widawsky wrote: > > The comment in the code details the restriction. Thanks to Ken for having a > > very > > helpful conversation with me, and spotting the blurb i

[Mesa-dev] [PATCH] i965/skl/gt4: Fix URB programming restriction.

The comment in the code details the restriction. Thanks to Ken for having a very helpful conversation with me, and spotting the blurb in the link I sent him :P. There are still stability problems for me on GT4, but this definitely helps with some of the failures. Cc: Kenneth Graunke

Re: [Mesa-dev] [PATCH 1/2] i965: Don't include missing components in the fast clear color

On Wed, Nov 04, 2015 at 06:11:09PM +0100, Neil Roberts wrote: > Neil Roberts writes: > > > Normally this doesn't matter because fast color clears are only > > available on Gen7+ and for that hardware we also always set the > > texture swizzle to force the missing components

Re: [Mesa-dev] [PATCH 03/10] i965/skl: Enable fast color clears on SKL

opt for fewer patches. I've modified this locally to summarize the above. I haven't read your review comments for the patches after this yet. It's likely that you noticed this, and we can continue the discussion there. > On Tue 13 Oct 2015, Ben Widawsky wrote: > > Based on a patch origina

Re: [Mesa-dev] [PATCH 04/10] i965/skl: skip fast clears for certain surface formats

On Fri, Oct 16, 2015 at 04:05:22PM -0700, Chad Versace wrote: > On Tue 13 Oct 2015, Ben Widawsky wrote: > > Initially I had this planned as a patch to be squashed in to the enabling > > patch > > because there is no point enabling fast clears without this. However, Chad >

Re: [Mesa-dev] [PATCH 05/10] i965/meta/gen9: Individually fast clear color attachments

On Tue, Oct 13, 2015 at 09:14:29PM -0700, Matt Turner wrote: > On Tue, Oct 13, 2015 at 9:12 PM, Matt Turner <matts...@gmail.com> wrote: > > On Tue, Oct 13, 2015 at 8:50 PM, Ben Widawsky > > <benjamin.widaw...@intel.com> wrote: > >> The impetus for this patch com

[Mesa-dev] [PATCH] i965: Fix texture views of 2d array surfaces

: Mark Janes <mark.a.ja...@intel.com> (Jenkins) References: https://www.opengl.org/registry/specs/ARB/texture_view.txt Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609 Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/gen8_surface_stat

Re: [Mesa-dev] [PATCH] i965: Fix texture views of 2d array surfaces

On Mon, Nov 02, 2015 at 12:05:32PM -0800, Ben Widawsky wrote: > It is legal to have a texture view of a single layer from a 2D array texture; > you can sample from it, or render to it. Intel hardware needs to be made aware > when it is using a 2d array surface in the surface state. Th

[Mesa-dev] [PATCH] [v2] i965: Fix texture views of 2d array surfaces

org/registry/specs/ARB/texture_view.txt Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609 Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mes

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] [v3] i965/skl: Add GT4 PCI IDs

On Fri, Oct 30, 2015 at 01:38:47PM -0700, Ian Romanick wrote: > On 10/29/2015 05:30 PM, Ben Widawsky wrote: > > Like other gen8+ hardware, the hardware automatically scales up thread > > counts > > and URB sizes, so there is no need to do anything but add the PCI IDs. &g

[Mesa-dev] [PATCH 1/2] [v3] i965/skl: Add GT4 PCI IDs

the wm thread count to support GT4. Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- include/pci_ids/i965_pci_ids.h | 4 src/mesa/drivers/dri/i965/brw_device_info.c | 6 +- 2 files changed, 9 insertions(+), 1 deletion(-)

Re: [Mesa-dev] [PATCH 2/2] i965/vec4: Drop brw_set_default_* before popping insn state.

(p, BRW_ALIGN_16); > } > brw_pop_insn_state(p); > } I'm assuming this is because the correct access mode is always set up before generating the assembly (probably wouldn't hurt to have added that to the commit message for naive people like myself)? If so: Reviewed-by:

[Mesa-dev] [PATCH 1/2] [v2] i965/skl: Add GT4 PCI IDs

...@lists.freedesktop.org Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- include/pci_ids/i965_pci_ids.h | 4 src/mesa/drivers/dri/i965/brw_device_info.c | 4 2 files changed, 8 insertions(+) diff --git a/include/pci_ids/i965_pci_ids.h b/include/p

[Mesa-dev] [PATCH 2/2] [v2] i965/skl: PCI ID cleanup and brand strings

A few new PCI ids are added here, and two are removed (0x190B, 0x192A) because it no longer seems to exist anywhere. v2: Update commit message to reflect the removal of 0x192a as well. Only use ascii characters (Ilia) Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- include/p

[Mesa-dev] [PATCH 2/2] intel: Cleanup SKL PCI ID definitions.

This removes ones which aren't used 0x190b, 192a), and adds some new ones. I kept the original names where possible. Cc: Kristian Høgsberg <k...@bitplanet.net> Cc: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- intel/in

[Mesa-dev] [PATCH 2/2] [v3] i965/skl: PCI ID cleanup and brand strings

for GT4 parts. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- include/pci_ids/i965_pci_ids.h | 33 ++--- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 626064a..2

[Mesa-dev] [PATCH 1/2] intel: Add SKL GT4 PCI IDs

Cc: Kristian Høgsberg <k...@bitplanet.net> Cc: Damien Lespiau <damien.lesp...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- intel/intel_chipset.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/intel/intel

[Mesa-dev] [PATCH 1/2] i965/skl: Add GT4 PCI IDs

Like other gen8+ hardware, the hardware automatically scales up thread counts and URB sizes, so there is no need to do anything but add the PCI IDs. FINISHME: This patch still needs testing before merge. Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Ben Widawsky <benjamin.wi

[Mesa-dev] [PATCH 2/2] i965/skl: PCI ID cleanup and brand strings

A few new PCI ids are added here, and one is removed (0x190B) because it no longer seems to exist anywhere. Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> --- include/pci_ids/i965_pci_ids.h | 40 ++-- 1 file changed, 22 insertions(+), 18 del

Re: [Mesa-dev] [PATCH 1/2] i965/skl: Add GT4 PCI IDs

On Fri, Oct 23, 2015 at 10:37:29AM -0700, Ben Widawsky wrote: > Like other gen8+ hardware, the hardware automatically scales up thread counts > and URB sizes, so there is no need to do anything but add the PCI IDs. > > FINISHME: This patch still needs testing before merge. >

Re: [Mesa-dev] [PATCH 2/2] i965/skl: PCI ID cleanup and brand strings

On Fri, Oct 23, 2015 at 01:44:38PM -0400, Ilia Mirkin wrote: > On Fri, Oct 23, 2015 at 1:37 PM, Ben Widawsky > <benjamin.widaw...@intel.com> wrote: > > A few new PCI ids are added here, and one is removed (0x190B) because it no > > longer seems to exist anywhere. &g

Re: [Mesa-dev] [PATCH 2/2] i965: Set Y-tiling for qualified rotated scanout buffers

On Fri, Oct 23, 2015 at 06:19:02PM -0700, Vivek Kasireddy wrote: > On Thu, 22 Oct 2015 21:12:02 -0700 > Ben Widawsky <b...@bwidawsk.net> wrote: > > > On Thu, Oct 22, 2015 at 06:44:53PM -0700, Vivek Kasireddy wrote: > > > On newer hardware platforms tha

Re: [Mesa-dev] [PATCH] i965: Remove unused devinfo revision

On Fri, Oct 23, 2015 at 02:38:39PM -0700, Ben Widawsky wrote: > I left the function to obtain the revision because it is, and will continue to > be useful in the future. I'd rather not have to dig it up every time we need > it. > Comments left at the implementation to say as muc

[Mesa-dev] [PATCH] i965: Remove unused devinfo revision

I left the function to obtain the revision because it is, and will continue to be useful in the future. I'd rather not have to dig it up every time we need it. Comments left at the implementation to say as much. Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dr

Re: [Mesa-dev] [PATCH 2/2] i965: Set Y-tiling for qualified rotated scanout buffers

On Thu, Oct 22, 2015 at 06:44:53PM -0700, Vivek Kasireddy wrote: > On newer hardware platforms that support rotation, if the gbm > interface requests to create a rotated scanout buffer via the > flag __DRI_IMAGE_USE_SCANOUT_ROTATED_90_270, set Y-tiling > while creating the buffer. > > Cc:

Re: [Mesa-dev] [PATCH] i965/fs: Disable opt_sampler_eot for more message types

On Tue, Oct 20, 2015 at 02:48:41PM -0700, Matt Turner wrote: > On Tue, Oct 20, 2015 at 2:41 PM, Ben Widawsky <b...@bwidawsk.net> wrote: > > On Tue, Oct 20, 2015 at 11:56:15AM +0200, Neil Roberts wrote: > >> In bfdae9149e0 I disabled the opt_sampler_eot optimisation fo

[Mesa-dev] [PATCH 2/6] [v2] i965/fs: Enumerate logical fb writes arguments

to make sure the component numbering is correct (Ben) Cc: Matt Turner <matts...@gmail.com> Cc: Francisco Jerez <curroje...@riseup.net> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_defines.h | 22 +- src/mesa/drivers/d

[Mesa-dev] [PATCH 6/6] i965: Advertise ARB_shader_stencil_export (gen9+)

Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- docs/relnotes/11.1.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html index d3dbe9d..9abc6df 100644 ---

[Mesa-dev] [PATCH 5/6] Implement the proper packing for the stencil payload

This patch is split out for review. It will be squashed before pushing. --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++- src/mesa/drivers/dri/i965/brw_fs.h | 2 ++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 44

[Mesa-dev] [PATCH 0/6] Add ARB_shader_stencil_export for SKL+

working on implementing meta blits for stencil using this extension. I think the patches for that are mostly done, but they need more testing. I'll be posting those separately. Ben Widawsky (6): i965: Correct the comment about fb write payload i965/fs: Enumerate logical fb writes arguments

[Mesa-dev] [PATCH 2/6] i965/fs: Enumerate logical fb writes arguments

to the patch. Cc: Francisco Jerez <curroje...@riseup.net> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_defines.h | 18 ++ src/mesa/drivers/dri/i965/brw_fs.cpp| 21 +++-- 2 files changed, 21 insertions(+), 18 deleti

[Mesa-dev] [PATCH 3/6] i965: (trivial) rename computes stencil to gen9

<kenn...@whitecape.org> Date: Thu Nov 29 21:00:27 2012 -0800 i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA. Cc: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_defines.h | 2 +-

[Mesa-dev] [PATCH 1/6] i965: Correct the comment about fb write payload

Cc: Francisco Jerez <curroje...@riseup.net> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_defines.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_def

[Mesa-dev] [PATCH 4/6] i965: Implement ARB_shader_stencil_export (SKL+)

Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_compiler.h | 1 + src/mesa/drivers/dri/i965/brw_defines.h| 5 +++-- src/mesa/drivers/dri/i965/brw_fs.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_fs.h | 2 +

Re: [Mesa-dev] [PATCH] i965/fs: Disable opt_sampler_eot for more message types

On Tue, Oct 20, 2015 at 11:56:15AM +0200, Neil Roberts wrote: > In bfdae9149e0 I disabled the opt_sampler_eot optimisation for TG4 > message types because I found by experimentation that it doesn't work. > I wrote in the comment that I couldn't find any documentation for this > problem. However

Re: [Mesa-dev] [PATCH 2/6] i965/fs: Enumerate logical fb writes arguments

On Tue, Oct 20, 2015 at 02:57:24PM -0700, Matt Turner wrote: > On Tue, Oct 20, 2015 at 2:54 PM, Ben Widawsky <b...@bwidawsk.net> wrote: > > On Tue, Oct 20, 2015 at 02:52:29PM -0700, Matt Turner wrote: > >> On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky > >> &l

Re: [Mesa-dev] [PATCH 5/6] Implement the proper packing for the stencil payload

On Tue, Oct 20, 2015 at 03:17:38PM -0700, Matt Turner wrote: > On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky > <benjamin.widaw...@intel.com> wrote: > > This patch is split out for review. It will be squashed before pushing. > > --- > > src/mesa/drivers/dri/

Re: [Mesa-dev] [PATCH 2/6] i965/fs: Enumerate logical fb writes arguments

On Tue, Oct 20, 2015 at 02:52:29PM -0700, Matt Turner wrote: > On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky > <benjamin.widaw...@intel.com> wrote: > > Gen9 adds the ability to write out a stencil value, so we need to expand the > > virtual payload by one. Abstracting th

Re: [Mesa-dev] [PATCH 2/6] i965/fs: Enumerate logical fb writes arguments

On Tue, Oct 20, 2015 at 03:19:48PM -0700, Matt Turner wrote: > On Tue, Oct 20, 2015 at 3:11 PM, Ben Widawsky <b...@bwidawsk.net> wrote: > > On Tue, Oct 20, 2015 at 02:57:24PM -0700, Matt Turner wrote: > >> On Tue, Oct 20, 2015 at 2:54 PM, Ben Widawsky <b...@bwidawsk.net

Re: [Mesa-dev] [PATCH 09/10] i965/meta: Remove fast_clear_color variable

baffled now why I'd see no piglit regressions since the clear color will *never* be all F. Either way, I'll drop this patch - but my confusion level has increased. > Ben Widawsky <benjamin.widaw...@intel.com> writes: > > > It doesn't actually serve a purpose AFAICT (in f

Re: [Mesa-dev] [PATCH 05/10] i965/meta/gen9: Individually fast clear color attachments

On Wed, Oct 14, 2015 at 08:04:48PM +0300, Pohjolainen, Topi wrote: > On Wed, Oct 14, 2015 at 09:54:43AM -0700, Ben Widawsky wrote: > > On Wed, Oct 14, 2015 at 02:43:24PM +0300, Pohjolainen, Topi wrote: > > > On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote: &g

Re: [Mesa-dev] [PATCH 05/10] i965/meta/gen9: Individually fast clear color attachments

On Wed, Oct 14, 2015 at 02:43:24PM +0300, Pohjolainen, Topi wrote: > On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote: > > Ben Widawsky <benjamin.widaw...@intel.com> writes: > > > > > The impetus for this patch comes from a seemingly benign statemen

Re: [Mesa-dev] [PATCH 04/10] i965/skl: skip fast clears for certain surface formats

hange, for now we could certainly assume that SKL is the base set and future GENs add things. > Ben Widawsky <benjamin.widaw...@intel.com> writes: > > > Initially I had this planned as a patch to be squashed in to the enabling > > patch > > because there is no poi

Re: [Mesa-dev] [PATCH 00/10] Support Skylake MCS buffers (fast clears)

On Tue, Oct 13, 2015 at 08:50:17PM -0700, Ben Widawsky wrote: > This patch series adds support for fast color clears on SKL as it exists on > previous generations of hardware minus the new hardware restriction on surface > formats. Additionally, it adds support for utilizing clear value

[Mesa-dev] [PATCH 10/10] i965/gen9: Support fast clears for 32b float

Observed: 0.50 Probe at (0,0) Expected: 0.00 Observed: 0.50 Not-Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++-- src/mesa/drivers/dri/i965/gen8_surface_state.c | 8 2 files changed, 6 insertions(

[Mesa-dev] [PATCH 01/10] i965/gen8+: Remove redundant zeroing of surface state

the other instances as well. I can make an argument both ways (open coding it, vs. not). I can rework the next patch if requires. Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 12 1 file changed, 12 deletions(-) diff --git

[Mesa-dev] [PATCH 05/10] i965/meta/gen9: Individually fast clear color attachments

for clearing multiple color buffer attachments and can be observed in the following piglit tests: spec/arb_framebuffer_object/fbo-drawbuffers-none glclear spec/ext_framebuffer_multisample/blit-multiple-render-targets 0 Signed-off-by: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH 00/10] Support Skylake MCS buffers (fast clears)

this to provide large gains in tests which are memory bandwidth limited and doing many clears. Ben Widawsky (10): i965/gen8+: Remove redundant zeroing of surface state i965/gen8+: Extract color clear surface state i965/skl: Enable fast color clears on SKL i965/skl: skip fast clears

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