Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src
Now this is the preferred format for GL_SRGB8_ALPHA8.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965
We need to wire the original texture's mt into the view. All the hard
work of setting up an appropriate tree of gl_texture_image structures
has already been done by core mesa.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri
This is supported by all generations, and is required for memory layout
consistency for texture_view.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965
We're about to need this so we can determine the layer count of the
wrapper.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965
We'll still avoid MinLayer here since the fast path doesn't understand
arrays at all, but it's straightforward to do levels.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
1 file changed
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_fbo.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index d0e1349..98247f2
ARB_texture_view support) fixes
the piglit test: `spec/ARB_texture_view/view compare 48bit formats`
No regressions in gpu.tests on Haswell.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 2 +-
1 file
This is the effective layer count, for clears etc. This differs from the
depth of the miptree level when views are involved.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_fbo.c | 10 ++
src/mesa/drivers
on a 'prefer_no_swizzle' flag which
was set in TexStorage/TextureView paths, but we need the same behavior
for ARB_shader_image_load_store (which also works with images created
via TexImage, so we don't want it to be conditional.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/texformat.c | 22
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_copy.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c
b/src/mesa/drivers/dri/i965/intel_tex_copy.c
index ca0b5b9..c2b6c35 100644
--- a/src
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
docs/GL3.txt| 2 +-
docs/relnotes/10.2.html | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index b7e4c87..657ac7e 100644
--- a/docs/GL3
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 9e80935..300ff5c 100644
V2: - No need for layer_multiplier; multisampled depth surfaces are IMS.
- Remove unused num_layers.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_clear.c | 6 +++---
1 file changed, 3 insertions(+), 3
On Sun, Mar 30, 2014 at 12:36 AM, Brian Paul bri...@vmware.com wrote:
Let's put that closing */ on the next line to match the format of other
comments.
I keep doing that -- I guess I should fix my editor. :(
For both, Reviewed-by: Brian Paul bri...@vmware.com However, have you
retested
On Sun, Mar 30, 2014 at 12:50 AM, Marek Olšák mar...@gmail.com wrote:
Why is this needed?
The second patch fixes format/type to mesa_format matching for
intensity formats, so that texture uploads / buffer object clears /
etc can get the memcpy paths. (Previously, we were testing on pixel
format
clients such
as TexImage, GetTexImage, and ReadPixels, so this should really be
fixed in the problematic caller of st_choose_matching_format, that is
DrawPixels.
Marek
On Sat, Mar 29, 2014 at 7:48 PM, Chris Forbes chr...@ijw.co.nz wrote:
On Sun, Mar 30, 2014 at 12:50 AM, Marek Olšák mar
it will stick this time.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Brian Paul bri...@vmware.com
---
src/mesa/main/formats.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 4fb1f11..fb2501c
_mesa_format_matches_format_and_type() returns true for
GL_RED/GL_RED_INTEGER (with an appropriate type) into an intensity
mesa_format.
We want the `red`-based format instead, regardless of the order we find
them in our walk of the mesa formats list.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
The case for this was in the wrong function, and this format's store
func was not set in the table at all.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/texstore.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/texstore.c b/src/mesa
On Thu, Mar 27, 2014 at 2:20 AM, Juha-Pekka Heikkila
juhapekka.heikk...@gmail.com wrote:
Type mismatch caused random memory to be copied when casted
memory area was smaller than expected type.
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
---
GL_INTENSITY has never been valid as a pixel format -- to get the memcpy
pack/unpack paths, the app needs to specify GL_RED as the pixel format
(or GL_RED_INTEGER for the integer formats).
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/formats.c | 20
1 file
the FRAMEBUFFER_INCOMPLETE_DRAW_BUFFER /
FRAMEBUFFER_INCOMPLETE_READ_BUFFER cases are removed by that extension)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/fbobject.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
Tested on ILK and CTG (with the GL3isms taken out of the piglits).
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers
Now this is the preferred format for GL_SRGB8_ALPHA8 with
prefer_no_swizzle.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers
in piglit's
arb_texture_view-format-consistency-get test on i965. The similar 1-, 2-
and 4-component cases already worked because they took the memcpy path
rather than repacking.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/pack.c | 116
This is supported by all generations, and is required for memory layout
consistency for texture_view.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_copy.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c
b/src/mesa/drivers/dri/i965/intel_tex_copy.c
index ca0b5b9..c2b6c35 100644
--- a/src
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 22a4a07..9194c06 100644
This series follows on from the ARB_texture_view support +
`prefer_no_swizzle` patches I sent out a while ago and fixes a few
things which I had previously overlooked:
- CopyTexSubImage didn't account for MinLayer or MinLevel when copying into a
view.
- GetTexImage handling of SNORM formats
The comments for the actual formats were fixed a while ago,
but the examples at the top were not, which was confusing.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/formats.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/formats.h b/src
and this series
gets a fair bit simpler -- the only big question that remains is
whether to do this in mesa core, or give i965 its own
ChooseTextureFormat hook to avoid disturbing anyone else.
-- Chris
Chris Forbes chr...@ijw.co.nz writes:
Actually, after poking around a bit more, I think
This patch is:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Mar 12, 2014 at 9:28 PM, Kenneth Graunke kenn...@whitecape.org wrote:
Ideally, we'd like to never even attempt the SIMD16 compile if we could
know ahead of time that it won't succeed---it's purely a waste of time
.
Unfortunately the example higher up of how a type-P format is laid out
is still backwards, which adds to the confusion.
-- Chris
On Wed, Mar 12, 2014 at 12:36 PM, Chris Forbes chr...@ijw.co.nz wrote:
Yeah, you're right -- that looks bogus. There's been piles of
confusion recently in formats.h about
==GL_NONE in mesa, and possibly avoid the parameter -- but
that doesn't help for ARB_shader_image_load_store.
-- Chris
On Wed, Mar 12, 2014 at 8:47 AM, Francisco Jerez curroje...@riseup.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
Hi Michel, and thanks for the quick feedback.
This is why it's
...@riseup.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
If prefer_no_swizzle is set, try:
- The exact matching format
- Formats with the required components in the correct order, plus a junk
component
- finally, swizzled formats (BGRA etc)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src
Future patches will pass this to where it is needed. For now, just
drop it on the floor.
TexStorage* and TextureView pass GL_TRUE; all other callers pass
GL_FALSE.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/teximage.c | 11 +++
src/mesa/main/teximage.h
Now this is the preferred format for GL_SRGB8_ALPHA8 with
prefer_no_swizzle.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers
, or for interaction with scanout hardware.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i915/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/nouveau/nouveau_texture.c | 3 ++-
src/mesa/drivers/dri/radeon/radeon_texture.c
There are good reasons for wanting alternative component orderings for some
surfaces, but this complicates views, which need the components to be in a
consistent order across whole view classes.
This series alters texture format selection to prefer unswizzled formats in
TexStorage* and
If prefer_no_swizzle is set, try:
- The exact matching format
- Formats with the required components in the correct order, plus a junk
component
- finally, swizzled formats (BGRA etc)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/texformat.c | 35
-03-10 at 22:20 +1300, Chris Forbes wrote:
If prefer_no_swizzle is set, try:
- The exact matching format
- Formats with the required components in the correct order, plus a junk
component
How are 'exact matching' and 'correct order' defined? My understanding
of GL internal formats
Will land this + the sampler key width change since they fix real
bugs, and then follow up with a new series to improve performance.
On Sun, Feb 23, 2014 at 9:25 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On 02/21/2014 09:09 PM, Chris Forbes wrote:
BRW_MAX_TEX_UNIT is the static limit
Previously the `high` 16 samplers on Haswell+ would not get sampler
workarounds applied.
Don't bother widening YUV fields, since they're ignored and going away
soon anyway.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 10.1 mesa-sta...@lists.freedesktop.org
Cc: Kenneth Graunke kenn
Ken,
Just noticed -- all those fields that we're keeping need to be widened
to uint32_t for 32 samplers. None of our sampler quirks get flagged
correctly for `high` samplers on Haswell at present. I'll send some
patches for that this evening if no one beats me to it.
-- Chris
On Tue, Feb 25,
I'd call the new structure just brw_surface. This stuff hasn't been
specific to the WM for as long as we've supported vertex textures.
-- Chris
On Sat, Feb 22, 2014 at 10:05 PM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
. [The interaction with
ARB_stencil_texturing is a good example of why you might want to]
On Sat, Feb 22, 2014 at 4:06 PM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
We will need this for munging the view's format.
But texture views don't allow internalformats
be actually
used.
Fixes invisible bad behavior in piglit's max-samplers test (although
this escalated to an assertion failure on HSW with texture_view, since
non-immutable textures only have _Format set by validation.)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 9.2 10.0 10.1 mesa-sta
This series adds support for texture views on i965. I think it's fairly
complete, but have probably still missed some things. It would be great if
someone at Intel can run the relevant parts of oglconform against this.
Big changes from V1:
* Level/layer clamping behavior is fixed. [there were
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index eca876b..e43c1ff 100644
ARB_texture_view support) fixes
the piglit test: `spec/ARB_texture_view/view compare 48bit formats`
No regressions in gpu.tests on Haswell.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/texobj.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 6adc0ae..67c362d 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -557,6 +557,13
We will need to call this to munge view formats.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++
2 files changed, 45 insertions(+), 34 deletions(-)
diff --git
-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_validate.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index d8497a6..c8e1afb 100644
--- a/src/mesa/drivers
We will need this for munging the view's format.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git
We need to wire the original texture's mt into the view. All the hard
work of setting up an appropriate tree of gl_texture_image structures
has already been done by core mesa.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex.c | 41
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index
This is the actual mesa_format to use. In non-view cases this is always
the same as the mt's format.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex.c | 8
src/mesa/drivers/dri/i965/intel_tex_obj.h | 5 +
src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 9159df5..039bc03 100644
This allows core mesa's TexSubImage paths etc to work correctly
with views which have nonzero MinLevel or MinLayer.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 489b6ad..c2875dd 100644
This will eventually be relaxed, but we'll get the fallback path
working first.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa
V2: - No need for layer_multiplier; multisampled depth surfaces are IMS.
- Remove unused num_layers.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_clear.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/GL3.txt| 2 +-
docs/relnotes/10.2.html | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 542ee28..f53e92a 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -162,7 +162,7 @@ GL 4.3
We're about to need this so we can determine the layer count of the
wrapper.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 039bc03..9e7252f 100644
--- a/src
This is the effective layer count, for clears etc. This differs from the
depth of the miptree level when views are involved.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_fbo.c | 10 ++
src/mesa/drivers/dri/i965/intel_fbo.h | 3 +++
2 files changed, 13
We'll still avoid MinLayer here since the fast path doesn't understand
arrays at all, but it's straightforward to do levels.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_fbo.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index d11cdb6..a2ed5d2 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
We're about to need this in another place.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index ef9aa55..0bd1115 100644
--- a/src/mesa/drivers/dri
This is a nice improvement.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Sat, Feb 15, 2014 at 12:00 PM, Eric Anholt e...@anholt.net wrote:
It often confused people because it was unclear on whether it was the
physical or logical, and people needed the other one as well. We can
recompute
FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
+ break;
+ case PIPE_FORMAT_Z32_FLOAT:
+ case
[Possibly ignore that, I guess it's the negated number of mantissa bits]
On Tue, Feb 11, 2014 at 3:39 PM, Chris Forbes chr...@ijw.co.nz wrote:
FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ pa_su_poly_offset_db_fmt_cntl
Since we don't have to do nonzero miplevels for multisampling, can't
you just use mt-logical_width0 and mt-logical_height0 if
multisampling?
On Tue, Feb 11, 2014 at 6:48 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On 02/07/2014 10:43 PM, Kenneth Graunke wrote:
Broadwell's 3DSTATE_WM_HZ_OP
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Mon, Feb 10, 2014 at 1:56 PM, Kenneth Graunke kenn...@whitecape.org wrote:
The 4x and 8x cases contained identical code for extracting the X and
Y sample offset values and converting them from U0.4 back to float.
Without
not the right thing.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 41 +++-
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index
Forgot to cc the list.
-- Forwarded message --
From: Chris Forbes chr...@ijw.co.nz
Date: Fri, Feb 7, 2014 at 1:24 PM
Subject: Re: [Mesa-dev] [PATCH 2/2] i965: Use the new
brw_load_register_mem helper for draw indirect.
To: Kenneth Graunke kenn...@whitecape.org
+ } else
`centroid` has never been an interpolation qualifier, though.
In GLSL 1.20, `centroid varying` is a storage qualifier.
In GLSL 1.30, `centroid in`, `centroid out` are added as storage qualifiers.
In GLSL 4.20 (or ARB_shading_language_420pack), `centroid`, `sample`,
and `patch` are split from `in`
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 22 ++
2 files changed, 23 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_program.h | 11 +++
src/mesa/drivers/dri/i965/brw_wm.c | 20
2 files changed, 31 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_program.h
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c | 2 ++
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
This series adds a bunch of workarounds to enable ARB_texture_gather
(in its more restrictive form) on Gen6 hardware.
These are necessary because Gen6's gather4 instruction doesn't work
correctly with integer or unsigned integer formats.
The approach is:
* For 32-bit wide formats, pretend the
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 26 ++
2 files changed, 27 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965
, Feb 3, 2014 at 10:29 PM, Chris Forbes chr...@ijw.co.nz wrote:
This series adds a bunch of workarounds to enable ARB_texture_gather
(in its more restrictive form) on Gen6 hardware.
These are necessary because Gen6's gather4 instruction doesn't work
correctly with integer or unsigned integer
I wonder if we could lose mt-first_level entirely? It looks like it's
always going to be zero in i965 now.
On Sat, Feb 1, 2014 at 10:10 PM, Kenneth Graunke kenn...@whitecape.org wrote:
In commit 16060c5adcd4d809f97e874fcde763260c17ac18, Eric changed the
code to not relayout just for baselevel
Marek,
I think there's an interaction with software primitive restart here.
The primitive restart path maps the index buffer (and the indirect
buffer, for indirect draws), and relies on these checks to guarantee
that's possible.
That may not be an issue for your driver, though -- I don't know.
Hi Ian,
Replying to IRC:
idr chrisf: You know if SNB can do the enhanced textureGatherOffset
modes from ARB_gpu_shader5?
Sandybridge has per-slot offset support (gather4_po) but lacks:
* Channel select bits in the message header
* Any ability to sample from a multi-component
this language in the spec?
In any case, happy to park this for now -- it just looked like an easy
win, and it turns out it's not quite.
-- Chris
On Mon, Jan 27, 2014 at 5:59 AM, Ian Romanick i...@freedesktop.org wrote:
On 01/24/2014 10:51 PM, Chris Forbes wrote:
Same idea as gl_Layer -- this is delivered
If multiple color outputs are written, this shader is unlikely to be
useful with a winsys framebuffer.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1e6c3e0..d6ebe50 100644
--- a/src/mesa/drivers/dri/i965
at 3:34 AM, Chris Forbes chr...@ijw.co.nz wrote:
We're about to need this in another place.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/texobj.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 3c64c437..9cb46cd 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -557,6 +557,13
These two patches correct issues with level and layer clamping with texture
views.
With the main series + this, Jon's rendering-levels and rendering-layers tests
behave
correctly.
I'll fit these into the appropriate points in the main series, but didn't feel
it
was necessary to send out the
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