Re: [Mesa-dev] [PATCH 1/9] compiler: Add new system value SYSTEM_VALUE_BASE_VERTEX_ID

On Friday, November 10, 2017 9:53:29 AM PST Antia Puentes wrote: > This VS system value will contain the value passed as > for indexed draw calls or the value passed as for non-indexed > draw calls. It will be used to calculate the gl_VertexID as > SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus

[Mesa-dev] [PATCH] meta: Fix ClearTexture with GL_DEPTH_COMPONENT.

We only handled unpacking for GL_DEPTH_STENCIL formats. Cemu was hitting _mesa_problem() for an unsupported format in _mesa_unpack_float_32_uint_24_8_depth_stencil_row(), because the format was depth-only, rather than depth-stencil. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94739

Re: [Mesa-dev] [PATCH] intel/isl: Declare private array as static const

static const struct isl_drm_modifier_info modifier_info[] = { > { >.modifier = DRM_FORMAT_MOD_NONE, > .name = "DRM_FORMAT_MOD_NONE", > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message p

Re: [Mesa-dev] [PATCH v2] mesa: add AllowGLSLCrossStageInterpolationMismatch workaround

apani.pa...@intel.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801 > Acked-by: Andres Gomez <ago...@igalia.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Descrip

[Mesa-dev] [PATCH] i965: Program the dynamic state heap size to MAX_STATE_SIZE.

STATE_BASE_ADDRESS specifies a maximum size of the dynamic state section, beyond which data supposedly reads back as 0. On Gen8+, we were programming it to the size of the buffer. This worked fine until we started growing the state buffer in commit 2dfc119f22f25708. When the state buffer grows,

Re: [Mesa-dev] [PATCH 6/6] i965: Add some batchbuffer debugging code.

On Tuesday, November 28, 2017 4:13:21 PM PST Kenneth Graunke wrote: > Uncommenting these blocks stress tests the batch/state growth code by > trying to "grow" a buffer to the same size at least once per batch. > > When anything goes wrong with this code, dumping the validat

Re: [Mesa-dev] [PATCH 5/6] i965: Avoid problems from referencing orphaned BOs after growing.

On Tuesday, November 28, 2017 4:13:20 PM PST Kenneth Graunke wrote: > Growing the batch/state buffer is a lot more dangerous than I thought. > > A number of places emit multiple state buffer sections, and then write > data to the returned pointer, or save a pointer to brw->

Re: [Mesa-dev] [PATCH 5/6] i965: Avoid problems from referencing orphaned BOs after growing.

On Tuesday, November 28, 2017 6:34:20 PM PST Ian Romanick wrote: > On 11/28/2017 04:13 PM, Kenneth Graunke wrote: > > diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > b/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > index b30ffe5d7f6..12d165d7236 100644 >

Re: [Mesa-dev] [PATCH 1/6] i965: Don't grow batch/state buffer on every emit after an overflow.

On Tuesday, November 28, 2017 6:15:59 PM PST Ian Romanick wrote: > On 11/28/2017 04:13 PM, Kenneth Graunke wrote: > > Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we > > try and flush. If we're not allowed to flush, we resort to growing the > > b

[Mesa-dev] [PATCH 6/6] i965: Add some batchbuffer debugging code.

Uncommenting these blocks stress tests the batch/state growth code by trying to "grow" a buffer to the same size at least once per batch. When anything goes wrong with this code, dumping the validation list is a useful way to figure out what's happening. ---

[Mesa-dev] [PATCH 3/6] i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.

The original state buffer was marked with EXEC_OBJECT_CAPTURE. When growing it, we want to preserve that flag so we continue to capture it in GPU hang reports. Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Bugzilla:

[Mesa-dev] [PATCH 2/6] i965: Use old_bo->align when growing batch/state buffer instead of 4096.

The intention here is make the new BO use the same alignment as the old BO. This isn't strictly necessary, but we would have to update the 'alignment' field in the validation list when swapping it out, and we don't bother today. The batch and state buffers use an alignment of 4096, so this

[Mesa-dev] [PATCH 5/6] i965: Avoid problems from referencing orphaned BOs after growing.

Growing the batch/state buffer is a lot more dangerous than I thought. A number of places emit multiple state buffer sections, and then write data to the returned pointer, or save a pointer to brw->batch.state.bo and then use it in relocations. If each call can grow, this can result in stale map

[Mesa-dev] [PATCH 4/6] i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.

We're about to add more of them, and need to pass the whole lot of them around together when growing them. Putting them in a struct makes this much easier. brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things labeled 'batch' and 'state' now that we have multiple buffers.

[Mesa-dev] [PATCH 1/6] i965: Don't grow batch/state buffer on every emit after an overflow.

Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we try and flush. If we're not allowed to flush, we resort to growing the buffer so that there's space for the data we need to emit. We accidentally got the threshold wrong. The first non-wrappable call beyond (e.g.) STATE_SZ

[Mesa-dev] [PATCH] i965: Move perf_debug and WARN_ONCE back to brw_context.h.

These were moved to src/intel/common/gen_debug.h, but they are not common code. They assume that brw_context or gl_context variables exist, named brw or ctx. That isn't remotely true outside of i965. --- src/intel/common/gen_debug.h| 29 -

[Mesa-dev] [PATCH] i965: Use C99 struct initializers in brw_bufmgr.c.

This is cleaner than using a non-standard memclear macro (which does a memset to 0) and then initializing fields after the fact. We move the declarations to where we initialized the fields. While we're at it, we move the declaration of 'ret' that goes with the ioctl, eliminating the declaration

[Mesa-dev] [PATCH] i965: Fix Smooth Point Enables.

We want to program the 3DSTATE_RASTER field to the gl_context value, not the other way around. Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.) --- src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH mesa] genxml: fix assert guards

le changed, 5 insertions(+), 5 deletions(-) #ifndef NDEBUG is the right thing to use for guarding asserts. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___

Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

: Convert the supported_extensions struct to spirv_options > spirv: Refactor a couple of pointer query helpers Patches 1-7 (the above) and patch 10 (rename) are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> I'm planning to review the rest as well, but that's going to take a littl

Re: [Mesa-dev] [PATCH 2/2] i965: Implement ARB_texture_filter_minmax

On Thursday, November 16, 2017 11:50:48 AM PST Ian Romanick wrote: > On 11/14/2017 02:54 PM, Scott D Phillips wrote: > > On gen >= 9, minmax reduction modes are available as a flag in > > SAMPLER_STATE. > > --- > > docs/features.txt | 2 +- > >

Re: [Mesa-dev] [PATCH 1/2] i965/bufmgr: Add a helper to mark a BO as external

On Friday, November 17, 2017 5:02:04 PM PST Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_bufmgr.c | 17 +++-- > 1 file changed, 11 insertions(+), 6 deletions(-) Both patches are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org&g

Re: [Mesa-dev] [PATCH 3/4] i965: Rewrite disassembly annotation code

e_tail = false; Err...it's already false in this case. You just checked it two lines earlier, and disasm_new_inst_group doesn't change. > + } else { > + group = exec_node_data(struct inst_group, > + exec_list_get_tail_raw(disasm->group_list), >

Re: [Mesa-dev] [PATCH 1/2] anv: setup BO flags at state_pool/block_pool creation

nit(>bo_cache); > if (result != VK_SUCCESS) >goto fail_batch_bo_pool; > > - result = anv_state_pool_init(>dynamic_state_pool, device, 16384); > + /* For the state pools we explicitly disable 48bit. */ > + bo_flags = physical_device->has_exec_async ? EXEC_

[Mesa-dev] [PATCH] genxml: Fix PIPELINE_SELECT on G45/Ironlake.

Original 965 sets bits 28:27 to 0, while G45 and later set it to 1. Also, there's no GPGPU pipeline on Gen5, and the pipeline to select is a single bit - bit 1 is reserved. --- src/intel/genxml/gen45.xml | 4 ++-- src/intel/genxml/gen5.xml | 5 ++--- 2 files changed, 4 insertions(+), 5

[Mesa-dev] [PATCH] i965: Upload invariant state once at the start of the batch on Gen4-5.

We want to emit invariant state at the start of a render batch. In the past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT (because we don't have hardware contexts), which triggered the brw_invariant_state atom. So, it would be emitted before any 3D drawing. (Technically,

[Mesa-dev] [PATCH] i965: Listen to BRW_NEW_*_PROGRAM in L3 state atom.

This looks at prog->*. You don't get to do that unless you listen to BRW_NEW_*_PROGRAM, which is a superset of the cases where BRW_NEW_*_PROG_DATA is flagged. --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Mesa-dev] [PATCH] i965: Implement another VF cache invalidate workaround on Gen8+.

...and provide a better citation for the existing one. v2: - Apply the workaround to Gen8 too, as intended (caught by Topi). - Restructure to add bits instead of an extra flush (based on a similar patch by Rafael Antognolli). --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 41

Re: [Mesa-dev] [PATCH] i965: Remove DWord length from MI_FLUSH_DW definition

On Tuesday, November 14, 2017 2:52:35 PM PST Anuj Phogat wrote: > This fixes the changes introduced in commit 6165fda59b. > > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> > Cc: <mesa-sta...@lists.freedesktop.com> > Cc: Nanley Chery <nanley.g.ch...@intel.co

Re: [Mesa-dev] [PATCH 04/11] intel/tools/error: Only decode a few sections of error states.

On Sunday, November 12, 2017 1:41:29 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2017-11-12 08:35:05) > > These three are the only we can reasonably decode with genxml. > > Makes sense, I would recommend putting those into an array for ease of > future expansion. May

Re: [Mesa-dev] [PATCH 4/4] i965: Use prepare_external instead of make_shareable in setTexBuffer2

uot; <mesa-sta...@lists.freedesktop.org> > Cc: Chad Versace <chadvers...@chromium.org> > Cc: Daniel Stone <dani...@collabora.com> > Cc: Louis-Francis Ratté-Boulianne <l...@collabora.com> > Cc: Adam Jackson <a...@redhat.com> > Cc: Chris Wilson &

Re: [Mesa-dev] [PATCH 2/4] i965: Add more precise cache tracking helpers

t;src.addr.buffer); > - brw_render_cache_set_check_flush(brw, params->dst.addr.buffer); > + brw_cache_flush_for_read(brw, params->src.addr.buffer); > + brw_cache_flush_for_render(brw, params->dst.addr.buffer); This drops the cache flush, because brw_cache_flush_for_render is

Re: [Mesa-dev] [PATCH 4/4] i965: Use PTE MOCS for all external buffers

> buffer even though we don't know the caching mode. This can happen, for > instance, on buffers imported from another GPU via prime. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691 > Cc: Kenneth Graunke <kenn...@whitecape.org> > Cc: Chris Wilson <ch

Re: [Mesa-dev] [PATCH 3/4] intel/blorp: Make the MOCS setting part of blorp_address

rp_batch *batch, > vb[1].VertexBufferIndex = 1; > vb[1].BufferPitch = 0; > #if GEN_GEN >= 6 > - vb[1].VertexBufferMOCS = batch->blorp->mocs.vb; > + vb[0].VertexBufferMOCS = vb[1].BufferStartingAddress.mocs; I think you mean vb[1] here! With that fixes, patches 1-3 ar

Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

On Monday, November 13, 2017 1:30:10 PM PST Alejandro Piñeiro wrote: > > On 13/11/17 20:04, Kenneth Graunke wrote: > > On Monday, November 13, 2017 2:16:59 AM PST Alejandro Piñeiro wrote: > >> --- > >> src/compiler/spirv/spirv_info_c.py | 5 - > >> 1 fi

Re: [Mesa-dev] [PATCH 09/11] intel/tools/error: Decode shaders while decoding batch commands.

On Sunday, November 12, 2017 3:57:56 AM PST Lionel Landwerlin wrote: > On 12/11/17 08:35, Kenneth Graunke wrote: > > This makes aubinator_error_decode's shader dumping work like aubinator. > > Instead of printing them after the fact, it prints them right inside the > > 3

Re: [Mesa-dev] [PATCH 11/11] intel/tools/error: Decode compute shaders.

On Sunday, November 12, 2017 4:06:06 AM PST Lionel Landwerlin wrote: > On 12/11/17 08:35, Kenneth Graunke wrote: > > This is a bit more annoying than your average shader - we need to look > > at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over > > to the

Re: [Mesa-dev] [PATCH 2/2] i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen9+

+), 2 deletions(-) Subject is wrong, should be Gen8+ not gen9+. Both patches are Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.

Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

;"\ > +TEMPLATE = Template("""\ > +/* DO NOT EDIT - This file generated automatically by spirv_info_c.py script > */ "is generated automatically" Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> > + > +""" + COPYRIGHT + "&quo

Re: [Mesa-dev] [PATCH 0/8] i965: add performance query support for Coffeelake

T2 > i965: perf: add support for CoffeeLake GT3 Patches 2-3 are Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> and the rest are Acked-by: Kenneth Graunke <kenn...@whitecape.org> because I have no idea where you get this information from, so I can't really re

Re: [Mesa-dev] [PATCH] intel/genxml: Delete empty groups

> headers in any way. > > Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com> > --- > src/intel/genxml/gen6.xml | 2 -- > src/intel/genxml/gen7.xml | 2 -- > src/intel/genxml/gen75.xml | 2 -- > src/intel/genxml/gen8.xml | 2 -- > 4 files changed, 8 deleti

Re: [Mesa-dev] [PATCH 2/2] intel/tools: Fix program disassembly in aubinator_error_decode.

On Saturday, November 11, 2017 3:35:21 PM PST Lionel Landwerlin wrote: > :( > > The intention was to deal with cases where we've encountered more than > MAX_NUM_PROGRAMS (actually happened to me). > So we start by the index + 1 assuming this is the oldest program because > we're in a rolling

[Mesa-dev] [PATCH 10/11] intel/tools/error: Use do-while for field iterator loops.

while loops skip the first field of the instruction/structure, which is not what the code intended. It works out because the field we're looking for doesn't happen to be first, but we ought to do it right regardless. Found while writing the next patch, where Kernel Start Pointer is the first

[Mesa-dev] [PATCH 11/11] intel/tools/error: Decode compute shaders.

This is a bit more annoying than your average shader - we need to look at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over to the dynamic state buffer to read the INTERFACE_DESCRIPTOR_DATA, then hop over to the instruction buffer to decode the program. Now that we store all the

[Mesa-dev] [PATCH 09/11] intel/tools/error: Decode shaders while decoding batch commands.

This makes aubinator_error_decode's shader dumping work like aubinator. Instead of printing them after the fact, it prints them right inside the 3DSTATE_VS/HS/DS/GS/PS packet that references them. This saves you the effort of cross-referencing things and jumping back and forth. It also reduces a

[Mesa-dev] [PATCH 08/11] intel/tools/error: Save error state sections and decode them later.

This lets us complete parsing and storing of each buffer's data before we begin decoding the batchbuffer. This makes it possible to inspect the state buffer and program buffer, so we can properly decode any indirect state or shader programs. --- src/intel/tools/aubinator_error_decode.c | 95

[Mesa-dev] [PATCH 01/11] intel/tools/error: Do ascii85 decode first.

The dashes "---" may occur within an ascii85 block, but only an ascii85 block starts with ':' or '~'. Ported from Chris Wilson's intel-gpu-tools commit: bceec7e1d8a160226b783c6344eae8cbf4ece144 --- src/intel/tools/aubinator_error_decode.c | 60 +++- 1 file changed, 29

[Mesa-dev] [PATCH 07/11] intel/tools/error: Fix null termination of ring name string.

Ported from intel_error_decode. We don't want to run off the end. --- src/intel/tools/aubinator_error_decode.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 9cd0fa761dd..f9d14cc20d5 100644 ---

[Mesa-dev] [PATCH 05/11] intel/tools/error: Refactor buffer matching, add more buffers.

Based on a similar patch to intel_error_decode by Chris Wilson. While we're de-duplicating the gtt_offset calculation, we can simplify it to assume two hex digits are there - the kernel has done this since v4.6, and we already require error states from v4.10. ---

[Mesa-dev] [PATCH 03/11] intel/tools/error: Drop unused parameters from decode() helper.

Also change count from a pointer into a value. We were supposed to be resetting it to 0 (and failed to), but that's gone since we dropped the pre-ascii85 handling. --- src/intel/tools/aubinator_error_decode.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 06/11] intel/tools/error: Drop unused MAX_RINGS #define.

Dead code. --- src/intel/tools/aubinator_error_decode.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 0b0a308a317..9cd0fa761dd 100644 --- a/src/intel/tools/aubinator_error_decode.c +++

[Mesa-dev] [PATCH 00/11] Make aubinator_error_decode support extra buffers

Hello, This series does a pretty substantial rework of aubinator_error_decode (the new error state decoder). The first few patches fix a whole bunch of bugs in the decoding, where we parsed the file wrong, decoded the wrong data in the wrong places, or decoded non-batch data as commands

[Mesa-dev] [PATCH 02/11] intel/tools/error: Drop support for non-ascii85 encoded error states.

Error state files used to look like: render ring --- gtt_offset = 0x0e8f6000 : 6904 0004 : 7909 ... 7ffc : --- ringbuffer = 0x1000 There were thousands of lines between sections. The file format changed with Kernel 4.10, and now has a

[Mesa-dev] [PATCH 04/11] intel/tools/error: Only decode a few sections of error states.

These three are the only we can reasonably decode with genxml. --- src/intel/tools/aubinator_error_decode.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 94436e957d4..ae9f08f1d2b

[Mesa-dev] [PATCH 2/2] intel/tools: Fix program disassembly in aubinator_error_decode.

This indexing is bogus. idx_program is the offset of the next program. At this point, we've walked through the entire batch, and accumulated all the programs. So adding it again simply skips over 100% of the programs. --- src/intel/tools/aubinator_error_decode.c | 13 ++--- 1 file

[Mesa-dev] [PATCH 1/2] intel/tools: Fix detection of enabled shader stages.

We renamed "Function Enable" to "Enable", which broke our detection of whether shaders are enabled or not. So, we'd see a bunch of HS/DS packets with program offsets of 0, and think that was a valid TCS/TES. Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".) ---

[Mesa-dev] [PATCH] i965: Make L3 configuration atom listen for TCS/TES program updates.

The L3 configuration code already considers the TCS and TES programs, but failed to listen for TCS/TES program changes. This was somehow missing. Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

Re: [Mesa-dev] [PATCH 1/3] i965: Make a better helper function for UBO/SSBO/ABO surface handling.

On Thursday, November 9, 2017 12:31:18 PM PST Jason Ekstrand wrote: > On Thu, Nov 9, 2017 at 12:45 AM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > > This fixes the missing AutomaticSize handling in the ABO code, removes > > a bunch of duplicated code, and drops

Re: [Mesa-dev] [PATCH] i965: Pretend there are 4 subslices for compute shader threads on Gen9+.

On Thursday, November 9, 2017 11:22:34 AM PST Rafael Antognolli wrote: > On Thu, Nov 09, 2017 at 12:59:12AM -0800, Jordan Justen wrote: > > Reviewed-by: Jordan Justen > > It's also > > Tested-by: Rafael Antognolli Sorry, I forgot to sync

[Mesa-dev] [PATCH 1/3] i965: Make a better helper function for UBO/SSBO/ABO surface handling.

This fixes the missing AutomaticSize handling in the ABO code, removes a bunch of duplicated code, and drops an extra layer of wrapping around brw_emit_buffer_surface_state(). --- src/mesa/drivers/dri/i965/brw_context.h | 10 -- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 113

[Mesa-dev] [PATCH 3/3] i965: Fold ABO state upload code into the SSBO/UBO state upload code.

Having this separate could potentially make programs that rebind atomics but no other surfaces ever so slightly faster. But it's a tiny amount of code to add to the existing UBO/SSBO atom, and very related. The extra atoms have a cost on every draw call, and so dropping some of them would be

[Mesa-dev] [PATCH 2/3] i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.

We use the same hardware mechanism for both atomic counters and SSBO atomics, so there's really no benefit to maintaining separate code to handle each case. Instead, we can just use Rob's shiny new NIR pass to convert atomic_uints to SSBOs, and delete piles of code. The ssbo_start section of the

[Mesa-dev] [PATCH] i965: Pretend there are 4 subslices for compute shader threads on Gen9+.

Similar to what we did for pixel shader threads - see gen_device_info.c. We don't want to bump the actual Maximum Number of Threads though, so we adjust it here. For pixel shaders, we don't use max_wm_threads, so we could just bump it globally. Fixes Piglit tests:

Re: [Mesa-dev] [PATCH 2/3] glsl: use the correct parent when allocating program data members

| 6 +++--- > src/compiler/glsl/shader_cache.cpp | 4 ++-- > 4 files changed, 8 insertions(+), 8 deletions(-) Patches 1-2 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Jordan might want to take a look at patch 1 as well... signature.asc Descripti

Re: [Mesa-dev] [PATCH 3/3] mesa: rework how we free gl_shader_program_data

On Tuesday, November 7, 2017 5:41:59 PM PST Timothy Arceri wrote: > When I introduced gl_shader_program_data one of the intentions was to > fix a bug where a failed linking attempt freed data required by a > currently active program. However I seem to have failed to finish > hooking up the final

Re: [Mesa-dev] [PATCH v3] i965: expose SRGB visuals and turn on EGL_KHR_gl_colorspace

MESA_FORMAT_B8G8R8X8_UNORM, > > + MESA_FORMAT_B8G8R8A8_SRGB, > + MESA_FORMAT_B8G8R8X8_SRGB, > + I'm worried that exposing B8G8R8X8_SRGB is not going to work. See the explanation in commit 61cdb7665f7bd147533cdc5977750d990c2eafd5. Unless I'm mistaken, I don't think anything

[Mesa-dev] [PATCH v2] glsl: Make #pragma STDGL invariant(all) only modify outputs.

According to the GLSL ES 3.20, GLSL 4.50, and GLSL 1.20 specs: "To force all output variables to be invariant, use the pragma #pragma STDGL invariant(all) before all declarations in a shader." Notably, this is only supposed to affect output variables. Furthermore, "Only

[Mesa-dev] [PATCH] glsl: Make #pragma STDGL invariant(all) only modify outputs.

According to the GLSL ES 3.20, GLSL 4.50, and GLSL 1.20 specs: "To force all output variables to be invariant, use the pragma #pragma STDGL invariant(all) before all declarations in a shader." Notably, this is only supposed to affect output variables. Furthermore, "Only

Re: [Mesa-dev] [PATCH 2/2] intel/compiler: Move the destructor from vec4_visitor to backend_shader

4 files changed, 5 insertions(+), 5 deletions(-) Both are Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists

Re: [Mesa-dev] [PATCH] glsl: Allow precision mismatch on dead uniform with GLSL ES 1.00 (v3)

On Thursday, October 19, 2017 9:02:20 PM PST Tomasz Figa wrote: > Hi Ian, Kenneth, > > On Wed, Sep 27, 2017 at 2:57 AM, Tomasz Figa wrote: > > Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for > > mismatching uniform precision, as required by GLES 3.0

Re: [Mesa-dev] [PATCH] nir: handle get_buffer_size in nir_lower_atomics_to_ssbo

keep same opcode and just remap SSBO buffer index: */ >op = instr->intrinsic; > idx_src = (op == nir_intrinsic_store_ssbo) ? 1 : 0; > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message

Re: [Mesa-dev] [PATCH 9/9] i965: Enable flush control

On Thursday, November 2, 2017 12:01:48 PM PDT Adam Jackson wrote: > From: Neil Roberts <n...@linux.intel.com> > > Reviewed-by: Adam Jackson <a...@redhat.com> > Signed-off-by: Neil Roberts <n...@linux.intel.com> Patches 2 and 9 are: Reviewed-by: Kenneth

[Mesa-dev] [PATCH] i965: Don't emit 3DSTATE_SAMPLER_STATE_POINTERS_VS for compute shaders.

For the render pipeline, the upload_sampler_state_table atom emits 3DSTATE_BINDING_TABLE_POINTERS_XS. It tries to avoid this for compute: if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) { /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */

Re: [Mesa-dev] [PATCH] i965: Fix ARB_indirect_parameters logic.

bug.cgi?id=103085 > > Signed-off-by: Plamena Manolova <plamena.manol...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> and pushed. Thanks Pam! signature.asc Description: This is a digitally signed message part. __

Re: [Mesa-dev] [PATCH v3 28/34] i965: add cache fallback support using serialized nir

On Sunday, October 29, 2017 5:21:47 PM PDT Jordan Justen wrote: > On 2017-10-29 01:11:32, Kenneth Graunke wrote: > > On Sunday, October 22, 2017 1:01:36 PM PDT Jordan Justen wrote: > > > If the i965 gen program cannot be loaded from the cache, then we > > > fallbac

Re: [Mesa-dev] [PATCH v3 34/34] i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false

hdr_for_addr(brw_disk_cache_init); > + int id_size = build_id_length(note); > + assert(note && id_size == 20 /* sha1 */); > + > + const uint8_t *id_sha1 = build_id_data(note); > + assert(id_sha1); > + > + char timestamp[41]; > + _mesa_sha1_format(timestamp, id_sha1

Re: [Mesa-dev] [PATCH v3 33/34] dri drivers: Always add the sha1 build-id

inux, dep_libdrm, dep_expat, dep_m, dep_thread, > dep_dl], > -link_args : [ld_args_bsymbolic, ld_args_gc_sections], > +link_args : ['-Wl,--build-id=sha1', ld_args_bsymbolic, > ld_args_gc_sections], >) > >pkg.generate( > The autotools bits look f

Re: [Mesa-dev] [PATCH v3 32/34] disk_cache: Fix issue reading GLSL metadata

> * validation. > */ > - cache_item_md_size += sizeof(cache_key); > + cache_item_md_size += num_keys * sizeof(cache_key); >ret = lseek(fd, num_keys * sizeof(cache_key), SEEK_CUR); >if (ret == -1) > goto fail; > Reviewed-

Re: [Mesa-dev] [PATCH v3 30/34] i965: Initialize sha1 hash of dri config options

brwCreateContext? I'm always a bit confused about the driver/screen split here, but I think this looks right. With those changes, Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 29/34] i965: Don't link when the program was found in the disk cache

og->_LinkedShaders); stage++) { >struct gl_linked_shader *shader = shProg->_LinkedShaders[stage]; >if (!shader) > I was concerned that we might be skipping some steps here, but I think everything's OK... Reviewed-by: Kenneth Grau

Re: [Mesa-dev] [PATCH mesa] i965: remove unused variable

On Monday, October 30, 2017 3:37:40 AM PDT Eric Engestrom wrote: > Fixes: 2c873060d3578c7004c0 "i965: Delete unused >brw_vs_prog_data::nr_attributes field." > Cc: Kenneth Graunke <kenn...@whitecape.org> > Signed-off-by: Eric Engestrom <eric.engest...@imgtec.c

[Mesa-dev] [PATCH] i965: Don't flag BRW_NEW_SURFACES unless some push constants are dirty.

Due to a gaffe on my part, we were re-emitting all binding table entries on every single draw call. The push_constant_packets atom listens to BRW_NEW_DRAW_CALL, but skips emitting 3DSTATE_CONSTANT_XS for each stage unless stage_state->push_constants_dirty is true. However, it flagged

Re: [Mesa-dev] [PATCH v3 13/34] glsl/shader_cache: Save and restore serialized nir in gl_program

On Sunday, October 22, 2017 1:01:21 PM PDT Jordan Justen wrote: > v3: > * Rename serialized_nir* to driver_cache_blob*. (Tim) > > Signed-off-by: Jordan Justen > Reviewed-by: Timothy Arceri > --- > src/compiler/glsl/shader_cache.cpp | 16

Re: [Mesa-dev] [PATCH v3 28/34] i965: add cache fallback support using serialized nir

On Sunday, October 22, 2017 1:01:36 PM PDT Jordan Justen wrote: > If the i965 gen program cannot be loaded from the cache, then we > fallback to using a serialized nir program. > > This is based on "i965: add cache fallback support" by Timothy Arceri > . Tim's

Re: [Mesa-dev] [PATCH v3 22/34] i965: Add shader cache support for vertex and fragment stages

eword subject] > [jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program] > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Patches 22-27 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc D

Re: [Mesa-dev] [PATCH v3 21/34] i965: add initial implementation of on disk shader cache

On Sunday, October 22, 2017 1:01:29 PM PDT Jordan Justen wrote: > From: Timothy Arceri > > This uses the recently-added disk_cache.c to write out the final > linked binary for vertex and fragment shader programs. > > This is based off the initial implementation

Re: [Mesa-dev] [PATCH 4/4] i965: Only set key->high_quality_derivatives when it matters.

On Saturday, October 28, 2017 11:08:29 AM PDT Jason Ekstrand wrote: > Have you seen this matter somewhere? It seems like a reasonable thing to > do none the less. 3 and 4 are > > Reviewed-by: Jason Ekstrand Yeah, the Aztec Ruins GL version hits this on almost all of its

Re: [Mesa-dev] [PATCH v2 0/3] Fix for PerVertexValidation CTS test

ck from the symbol table rather waiting for an instruction which > references it. > > I’ve tested it with Piglit and the public CTS repo and it doesn’t > cause any regressions, and of course it fixes the CTS test. > > It might be nice to add a Piglit or CTS test to check this mis

[Mesa-dev] [PATCH 3/4] nir: Make nir_gather_info collect a uses_fddx_fddy flag.

i965 turns fddx/fddy into their coarse/fine variants based on the ctx->Hint.FragmentShaderDerivative setting. It needs to know whether this can impact a shader in order to better guess NOS settings. --- src/compiler/nir/nir_gather_info.c | 16 src/compiler/shader_info.h

[Mesa-dev] [PATCH 4/4] i965: Only set key->high_quality_derivatives when it matters.

This avoids recompiles for shaders that don't use explicit derivatives when ctx->Hint.FragmentShaderDerivative == GL_NICEST. --- src/mesa/drivers/dri/i965/brw_wm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index

[Mesa-dev] [PATCH 1/4] i965: Delete brw_wm_prog_key::drawable_height.

This has been unused since we switched to nir_lower_wpos_ytransform. --- src/intel/compiler/brw_compiler.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 6a330537a5b..17615c6dd9f 100644 ---

[Mesa-dev] [PATCH 2/4] i965: Update brw_wm_debug_recompile() for newer key entries.

Also, reorder them to match the structure's field order, to make it easier to check that they're all present. --- src/mesa/drivers/dri/i965/brw_wm.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c

Re: [Mesa-dev] [PATCH V2 1/2] i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1

On Friday, October 27, 2017 3:17:20 PM PDT Anuj Phogat wrote: > V2: Use _NEW_BUFFERS in place of _NEW_MULTISAMPLE > > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> > Cc: Kenneth Graunke <kenn...@whitecape.org> > --- > src/mesa/drivers/dri/i965/genX_state_up

Re: [Mesa-dev] [PATCH 1/2] i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1

On Friday, October 27, 2017 10:50:23 AM PDT Anuj Phogat wrote: > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c >

Re: [Mesa-dev] [PATCH v5 00/10] new series of Mesa for Tizen

On Thursday, October 26, 2017 11:16:06 AM PDT Eric Anholt wrote: > Gwan-gyeong Mun writes: > > > Hi, > > > > These Patch v5 series modified with new helper function series [1]. > > > > These series only have mesa for tizen feature. > > > > [1]

Re: [Mesa-dev] [PATCH] util: hashtable: make hashing prototypes match

ze); > -uint32_t _mesa_hash_string(const char *key); > +uint32_t _mesa_hash_string(const void *key); > bool _mesa_key_string_equal(const void *a, const void *b); > bool _mesa_key_pointer_equal(const void *a, const void *b); > > Reviewed-by: Kenneth Graunke <kenn...@whitecape.or

Re: [Mesa-dev] [PATCH] intel/compiler/gen9: Pixel shader header only workaround

On Friday, October 27, 2017 4:26:32 AM PDT Pohjolainen, Topi wrote: > On Fri, Oct 27, 2017 at 03:02:59AM -0700, Kenneth Graunke wrote: > > On Wednesday, October 25, 2017 10:37:37 AM PDT Topi Pohjolainen wrote: > > > Fixes intermittent GPU hangs on Broxton with an Intel intern

Re: [Mesa-dev] [PATCH 1/2] i965: remove if conditions from scratch_bo unref

_bo) > - brw_bo_unreference(brw->wm.base.scratch_bo); > + > + brw_bo_unreference(brw->vs.base.scratch_bo); > + brw_bo_unreference(brw->tcs.base.scratch_bo); > + brw_bo_unreference(brw->tes.base.scratch_bo); > + brw_bo_unreference(brw->gs.base.scratch_bo); > + brw_b

Re: [Mesa-dev] [PATCH] intel/compiler/gen9: Pixel shader header only workaround

from > this - most tests kick off one render cycle and any corruption > is left unseen. > > v2 (Ken): Instead of enabling push constants, enable one of the > inputs (PSIZ). > v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe() > h

Re: [Mesa-dev] [PATCH] i965: unref push_const_bo in intelDestroyContext

t * driContextPriv) > > if (brw->wm.base.scratch_bo) > >brw_bo_unreference(brw->wm.base.scratch_bo); > > > > + if (brw->vs.base.push_const_bo) > I'd drop the if checks - brw_bo_unreference works fine when the bo > pointer is NULL. > >

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