On 11/04/2024 06:05, Tapani Pälli wrote:
On 11.4.2024 1.15, Brian Paul wrote:
On 4/10/24 13:53, Timo Aaltonen wrote:
Brian Paul kirjoitti 6.4.2024 klo 1.05:
I'm trying to build the Intel Vulkan driver. First time in a few
months. I'm having build problems related to clc. I'm on Ubuntu
line
discussion.
v4:
- Various improvements all over. (Tvrtko)
v5:
- Include newer integrated platforms when applying the non-recoverable
context and error capture restriction. (Thomas)
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc:
On 17/05/2022 12:23, Tvrtko Ursulin wrote:
On 17/05/2022 09:55, Lionel Landwerlin wrote:
On 17/05/2022 11:29, Tvrtko Ursulin wrote:
On 16/05/2022 19:11, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks
nels, since this came up in some offline
discussion.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jon Bloomfield
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Akeem G Abodunrin
Cc: mesa
On 14/05/2022 00:06, Jordan Justen wrote:
On 2022-05-13 05:31:00, Lionel Landwerlin wrote:
On 02/05/2022 17:15, Ramalingam C wrote:
Capture the impact of memory region preference list of the objects, on
their memory residency and Flat-CCS capability.
v2:
Fix the Flat-CCS capability
-by: Ramalingam C
cc: Matthew Auld
cc: Thomas Hellstrom
cc: Daniel Vetter
cc: Jon Bloomfield
cc: Lionel Landwerlin
cc: Kenneth Graunke
cc: mesa-dev@lists.freedesktop.org
cc: Jordan Justen
cc: Tony Ye
Reviewed-by: Matthew Auld
---
include/uapi/drm/i915_drm.h | 16
1 file
On 03/05/2022 17:27, Matthew Auld wrote:
On 03/05/2022 11:39, Lionel Landwerlin wrote:
On 03/05/2022 13:22, Matthew Auld wrote:
On 02/05/2022 09:53, Lionel Landwerlin wrote:
On 02/05/2022 10:54, Lionel Landwerlin wrote:
On 20/04/2022 20:13, Matthew Auld wrote:
Add an entry for the new uapi
On 03/05/2022 13:22, Matthew Auld wrote:
On 02/05/2022 09:53, Lionel Landwerlin wrote:
On 02/05/2022 10:54, Lionel Landwerlin wrote:
On 20/04/2022 20:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks
On 03/05/2022 12:07, Matthew Auld wrote:
On 02/05/2022 19:03, Lionel Landwerlin wrote:
On 02/05/2022 20:58, Abodunrin, Akeem G wrote:
-Original Message-
From: Landwerlin, Lionel G
Sent: Monday, May 2, 2022 12:55 AM
To: Auld, Matthew ;
intel-...@lists.freedesktop.org
Cc: dri-de
. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (Thomas)
- Add probed_cpu_visible_size. (Lionel)
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Jon Bloomfield
Cc: Da
On 02/05/2022 10:54, Lionel Landwerlin wrote:
On 20/04/2022 20:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer nee
ture. (Thomas)
- Add probed_cpu_visible_size. (Lionel)
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Akeem G Abodunrin
Cc: mesa-dev@lists.freedesktop.org
---
Documentation/gpu
On 22/04/2022 07:56, Dylan Baker wrote:
Hi all,
I've spent a good deal of time this week crushing the backlog of
patches on the mesa 20.0 series before making the release today. As such
there are not only a dozen outstanding patches, mostly for zink, which I
couldn't figure out how to correctly
On 27/04/2022 18:18, Matthew Auld wrote:
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given
kernel?
I assume older kernels are going to reject object creation if we use
this flag
the placement on the GEM object and then query
whether it's mappable by address?
You made a comment stating this is racy, wouldn't querying on the GEM
object prevent this?
Thanks,
-Lionel
On 27/04/2022 09:35, Lionel Landwerlin wrote:
Hi Matt,
The proposal looks good to me.
Looking forward
ture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (Thomas)
- Add probed_cpu_visible_size. (Lionel)
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Lionel Landwerlin
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Hey Matthew, all,
This sounds like a good thing to have.
There are a number of DG2 machines where we have a small BAR and this is
causing more apps to fail.
Anv currently reports 3 memory heaps to the app :
- local device only (not host visible) -> mapped to lmem
- device/cpu ->
On 10/03/2021 22:39, Dylan Baker wrote:
Hi list,
I think we're just about ready for the mesa 21.0 release. Sorry I've
been really about this. Here's a lis tof all outstanding patches that
either don't apply, or don't compile. If you see something here you'd
like to backport for 21.0.0 please
Hi all,
I'm currently looking at implementing some new features in Vulkan WSI.
One particular feature I would like to add would need to do some processing
on events coming from the compositor/display without waiting for the
application to give us the opportunity to do so (by entering the WSI
On 14/02/2021 00:47, Rob Clark wrote:
On Sat, Feb 13, 2021 at 12:52 PM Lionel Landwerlin
wrote:
On 13/02/2021 18:52, Rob Clark wrote:
On Sat, Feb 13, 2021 at 12:04 AM Lionel Landwerlin
wrote:
On 13/02/2021 04:20, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:56 PM Lionel Landwerlin
wrote
On 13/02/2021 18:52, Rob Clark wrote:
On Sat, Feb 13, 2021 at 12:04 AM Lionel Landwerlin
wrote:
On 13/02/2021 04:20, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:56 PM Lionel Landwerlin
wrote:
On 13/02/2021 03:38, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:08 PM Lionel Landwerlin
wrote
On 13/02/2021 04:20, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:56 PM Lionel Landwerlin
wrote:
On 13/02/2021 03:38, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:08 PM Lionel Landwerlin
wrote:
We're kind of in the same boat for Intel.
Access to GPU perf counters is exclusive to a single
On 13/02/2021 03:38, Rob Clark wrote:
On Fri, Feb 12, 2021 at 5:08 PM Lionel Landwerlin
wrote:
We're kind of in the same boat for Intel.
Access to GPU perf counters is exclusive to a single process if you want
to build a timeline of the work (because preemption etc...).
ugg, does that mean
We're kind of in the same boat for Intel.
Access to GPU perf counters is exclusive to a single process if you want
to build a timeline of the work (because preemption etc...).
The best information we could add from mesa would a timestamp of when a
particular drawcall started.
But that's
I'm using these meson options :
-Dgles2=true -Ddri-drivers= -Dglx=dri -Dplatforms=x11,wayland
-Dgallium-drivers=zink -Dvulkan-drivers=intel -Dgallium-vdpau=false
-Dglvnd=true
-Lionel
On 04/02/2021 19:10, Mark Segal wrote:
I'm interested in using Zink to run an OpenGL app on Vulkan. I'm
Hi Andrii,
Just assigned it to Marge. Sorry for the delay.
-Lionel
On 02/02/2021 13:57, asimiklit wrote:
Hello,
Are there some issues/blockers which prevent MR8409 from being merged?
This MR already has r-b and I suspect that it was simply forgotten or
there are some issues with it I am
Hi Filip,
Did you file an issue about this?
If not, could you open one with the details of the platform you're
experiencing the crash on and the steps to reproduce?
Thanks,
-Lionel
On 04/09/2020 11:37, Filip Strömbäck wrote:
Dear mesa-dev,
I recently updated my system, and it seems like
On 28/02/2020 13:46, Michel Dänzer wrote:
On 2020-02-28 12:02 p.m., Erik Faye-Lund wrote:
On Fri, 2020-02-28 at 10:43 +, Daniel Stone wrote:
On Fri, 28 Feb 2020 at 10:06, Erik Faye-Lund
wrote:
On Fri, 2020-02-28 at 11:40 +0200, Lionel Landwerlin wrote:
Yeah, changes on vulkan drivers
On 28/02/2020 11:28, Erik Faye-Lund wrote:
On Fri, 2020-02-28 at 13:37 +1000, Dave Airlie wrote:
On Fri, 28 Feb 2020 at 07:27, Daniel Vetter
wrote:
Hi all,
You might have read the short take in the X.org board meeting
minutes
already, here's the long version.
The good news: gitlab.fd.o has
On 11/12/2019 09:28, Jean Hertel wrote:
From: Lionel Landwerlin
- In case the options are different (which is quite likely), how do we query
the available options?
For OpenGL we have glXGetScreenDriver/glXGetDriverConfig
For EGL we have eglGetDisplayDriverName/eglGetDisplayDriverConfig [2
On 08/12/2019 16:04, Jean Hertel wrote:
Dear Mesa developers,
I'm looking into further improving adriconf[1] as a tool to configure mesa
driver options.
Vulkan mesa drivers can now read their configuration options from the .drirc
configuration file.
With this in mind I have the following
Hmm... I don't see it.
Are you not confused by brw_batch_reloc/brw_state_reloc?
-Lionel
On 05/12/2019 06:56, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 5 -
1 file changed, 5 deletions(-)
diff --git
Meant to Cc Mark too :)
On 03/12/2019 21:24, Lionel Landwerlin wrote:
Hi all,
Our Windows drivers ships with a particular query in
GL_INTEL_performance_query called Intel_Null_Hardware_Query.
The query doesn't report any counter. The query isn't even listed if
you go through the list using
Hi all,
Our Windows drivers ships with a particular query in
GL_INTEL_performance_query called Intel_Null_Hardware_Query.
The query doesn't report any counter. The query isn't even listed if you
go through the list using glGetNextPerfQueryIdINTEL().
It's only returned using
W \o/
Nice work!
-Lionel
On 20/11/2019 20:31, Kenneth Graunke wrote:
Hi all,
iris is now officially a conformant OpenGL 4.6 implementation!
https://www.khronos.org/conformance/adopters/conformant-products/opengl#submission_253
This is on Gen9. I've also submitted for Gen8, but that's
On 19/08/2019 21:28, Rafael Antognolli wrote:
This param is only available starting on kernel 4.16. Use a default
value of 0 if it is not found instead.
I trace the param to :
commit 27cd44618b92fc8c6889e4628407791e45422bac
Author: Neil Roberts
Date: Wed Mar 4 14:41:16 2015 +
Hey Mauro,
I was kind of surprised that u_math.h would pull a gallium header file.
So I pulled the thread a bit and came up with this MR :
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1625
Sorry it's all over the place :(
-Lionel
On 09/08/2019 15:06, Mauro Rossi wrote:
Fixes the
Thanks this looks good to me : Reviewed-by: Lionel Landwerlin
On 05/07/2019 11:52, Chih-Wei Huang wrote:
The gen_enum_to_str.py generates vk_enum_to_str.c and its header at once.
However, the makefiles incorrectly list both files parallel with the same
recipes. That means both two files may
Reviewed-by: Lionel Landwerlin
And reported upstream : https://github.com/ocornut/imgui/pull/2561
On 17/05/2019 03:22, Dave Airlie wrote:
From: Dave Airlie
imgui_draw.cpp:1781: error[shiftTooManyBitsSigned]: Shifting signed 32-bit
value by 31 bits is undefined behaviour
Reported
I've uploaded this MR :
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/776
Which actually highlights a bigger issue with our queries.
-Lionel
On 01/05/2019 11:58, Lionel Landwerlin wrote:
Experimenting a bit with the visibility of PIPE_CONTROL writes & MI_*
commands I realized t
ject to
complicated synchronization rules.
Essentially just make emit_query_availability() take an additional
boolean and then use it in CmdResetQueryPool().
-Lionel
On 30/04/2019 18:18, Lionel Landwerlin wrote:
Let me check the new tests and see if where the problem is.
Thanks for letting us
Let me check the new tests and see if where the problem is.
Thanks for letting us know!
-Lionel
On 30/04/2019 13:43, Iago Toral Quiroga wrote:
Specifically, vkCmdCopyQueryPoolResults is required to see the effect
of a previous vkCmdResetQueryPool. This may not work currently when
query
I started this MR :
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/637
On 11/04/2019 13:06, Lionel Landwerlin wrote:
Sorry, upon rereading the code of the various drivers, it seems
i965/iris handle this properly already.
I have some comments below.
On 11/04/2019 11:36, Lionel
To be honest we're not initializing nir_locals either :/
Reviewed-by: Lionel Landwerlin
On 11/04/2019 11:32, Dave Airlie wrote:
From: Dave Airlie
Pointed out by coverity.
---
src/intel/compiler/brw_vec4_visitor.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler
Sorry, upon rereading the code of the various drivers, it seems
i965/iris handle this properly already.
I have some comments below.
On 11/04/2019 11:36, Lionel Landwerlin wrote:
Hi James,
Thanks a lot for reporting this.
I think this is something we should store in the gen_device_info
Hi James,
Thanks a lot for reporting this.
I think this is something we should store in the gen_device_info and
update with kernel ioctl when supported.
This affects other drivers, not just anv.
-Lionel
On 10/04/2019 23:55, James Xiong wrote:
From: "Xiong, James"
The vma high heap's
There is a small nit below which you don't have to apply.
With the correct bug reference :
Reviewed-by: Lionel Landwerlin
On 09/04/2019 15:18, Samuel Pitoiset wrote:
This is common to all Vulkan drivers and all WSI.
v3: - move the invalid check in wsi_device_init()
- use
On 09/04/2019 14:31, Samuel Pitoiset wrote:
This is common to all Vulkan drivers and all WSI.
v2: - store the override in wsi_device_init()
- do not abort when an invalid value is detected
- check supported present modes
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107391
On 09/04/2019 13:29, Samuel Pitoiset wrote:
On 4/9/19 1:10 PM, Lionel Landwerlin wrote:
On 09/04/2019 08:08, Samuel Pitoiset wrote:
This is common to all Vulkan drivers and all WSI.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107391
Signed-off-by: Samuel Pitoiset
---
src/vulkan
On 09/04/2019 08:08, Samuel Pitoiset wrote:
This is common to all Vulkan drivers and all WSI.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107391
Signed-off-by: Samuel Pitoiset
---
src/vulkan/wsi/wsi_common.c | 19 +++
src/vulkan/wsi/wsi_common_display.c |
On 21/03/2019 19:04, Eric Anholt wrote:
I've just put up a new repo that I'm hoping to use to enable automatic
shader-db results for various drivers on Gitlab CI merge requests (and
maybe with some more work, delete the simulator backends of vc4 and v3d).
Reviewed-by: Lionel Landwerlin
On 19/03/2019 19:15, Jason Ekstrand wrote:
---
src/compiler/nir/nir.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 67304af1d64..e4f012809e5 100644
--- a/src/compiler/nir/nir.h
+++ b
Reviewed-by: Lionel Landwerlin
On 19/03/2019 17:08, Jason Ekstrand wrote:
We initially set this lower because we didn't have SIMD32 support yet
but we've supported SIMD32 for quite some time now. We should bump it
up to the real limit.
---
src/intel/vulkan/anv_device.c | 2 +-
1 file
There is merge request opened about this issue :
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/429
I think the deps need to be moved from src/vulkan/wsi/meson.build into
src/vulkan/meson.build as they apply to the overlay, utils & wsi.
Thanks,
-Lionel
On 16/03/2019 18:56, Tobias
Reviewed-by: Lionel Landwerlin
On 12/03/2019 20:24, Jason Ekstrand wrote:
We've been fairly inconsistent about this so we should really choose
whether we're going to use VK_TRUE/FALSE or the C boolean values. The
Vulkan #defines are set to 1 and 0 respectively so it's the same value
as C
On 11/03/2019 15:04, Eleni Maria Stea wrote:
Enabled the VK_EXT_sample_locations for Intel Gen >= 7.
---
src/intel/vulkan/anv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index
Reviewed-by: Lionel Landwerlin
Thanks!
On 08/03/2019 15:52, Brian Paul wrote:
---
src/intel/compiler/brw_vec4.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index fe36851..2e9de29 100644
--- a/src
Reviewed-by: Lionel Landwerlin
On 08/03/2019 15:52, Brian Paul wrote:
---
src/intel/common/gen_batch_decoder.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index ff898d8..5cac983 100644
On 27/02/2019 06:55, Kenneth Graunke wrote:
On Tuesday, February 26, 2019 9:41:07 AM PST Christian Gmeiner wrote:
Push this format to the pipe driver unchanged.
Signed-off-by: Christian Gmeiner
---
include/GL/internal/dri_interface.h | 1 +
src/gallium/state_trackers/dri/dri2.c | 2 ++
;
+#if GEN_GEN >= 8
+ clip.VertexSubPixelPrecisionSelect = _8Bit;
+#endif
+
clip.ClipMode = CLIPMODE_NORMAL;
clip.TriangleStripListProvokingVertexSelect = 0;
Well spotted.
Reviewed-by: Lionel Landwerlin
___
mesa-dev mailing list
m
.
v2: explicitly set 3DSTATE_SF::VertexSubPixelPrecisionSelect (Jason)
v3: use _8Bit definition as value (Jason)
CC: Jason Ekstrand
CC: Kenneth Graunke
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Lionel Landwerlin
Cc: stable?
---
src/intel/vulkan/anv_device.c| 2 +-
src
On 22/02/2019 15:51, Juan A. Suarez Romero wrote:
Fill out "Vertex Sub Pixel Precision Select" possible values.
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 5 -
src/intel/genxml/gen11.xml | 5 -
src/intel/g
Pushed with the PRM quote, thanks!
On 22/02/2019 06:16, Samuel Iglesias Gonsálvez wrote:
Lionel, are you going to push it with this quote? I can add it
otherwise.
Sam
On Thu, 2019-02-21 at 13:41 +, Lionel Landwerlin wrote:
On 21/02/2019 13:30, Chris Wilson wrote:
Quoting Lionel
ly thought it was harder than that :)
Thanks!
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_lower_clip_cull_distance_arrays.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c
b/src/co
On 21/02/2019 13:30, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-21 12:57:09)
I did not find the PRM bit that says it must be 64b aligned, but I can
see that's what i915 checks.
Chris: If you have a pointer to it, I could add the quote.
In amongst the register specs,
PLANE_STRIDE
I did not find the PRM bit that says it must be 64b aligned, but I can
see that's what i915 checks.
Chris: If you have a pointer to it, I could add the quote.
Thanks!
Reviewed-by: Lionel Landwerlin
On 19/02/2019 12:06, Samuel Iglesias Gonsálvez wrote:
Signed-off-by: Samuel Iglesias
On 18/02/2019 15:08, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-18 15:06:15)
On 15/02/2019 14:43, Samuel Iglesias Gonsálvez wrote:
There are formats which bpp are not aligned to a power-of-two and
that can cause problems in the checks we do.
The cacheline size was a requirement
drop it.
Fixes CTS's CL#3500 test:
dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez
That looks good to me :
Reviewed-by: Lionel Landwerlin
I'm doing a CI run just to convince myself, so if you can wait
On 15/02/2019 14:43, Samuel Iglesias Gonsálvez wrote:
Signed-off-by: Samuel Iglesias Gonsálvez
Hey Samuel,
Thanks for this change. Would you mind changing the align_u32 in the
if() branch too?
It won't fix anything but that's just to be consistent.
With that :
Reviewed-by: Lionel
Fixes: 1f862e923cb "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Cc: Matt Turner
Tested-by: Lionel Landwerlin
With a new piglit test : https://patchwork.freedesktop.org/patch/286177/
---
src/intel/compiler/br
different shader contents. This was causing the simulator to believe
that the ver
Thanks for finding this.
Reviewed-by: Lionel Landwerlin
tex pipeline was executing a fragment shader, which didn't
end up well.
---
src/intel/tools/intel_dump_gpu.c | 41 ++--
1 file
ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")
Cc: José Roberto de Souza
Signed-off-by: Rodrigo Vivi
Acked-by: Lionel Landwe
Reviewed-by: Lionel Landwerlin
On 02/02/2019 08:07, Rodrigo Vivi wrote:
Align with kernel commits:
5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
Cc: José Roberto de Souza
Cc: Kenne
On 03/02/2019 16:04, Jason Ekstrand wrote:
They are effectively ()[0] or * which does nothing.
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_deref.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/TODO | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index b4da05de2b1..5b27cb2bd63 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -7,7 +7,4 @@ Missing Features
Thanks Caio, pushed to master.
On 22/01/2019 18:13, Caio Marcelo de Oliveira Filho wrote:
Reviewed-by: Caio Marcelo de Oliveira Filho
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mesa-dev@lists.freedesktop.org
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https://gitlab.freedesktop.org/mesa/mesa/merge_requests/139
The start of a Vulkan layer to display some basic swapchain/draws/submit
information.
Looks like this : https://i.imgur.com/4zyIiVb.png
There is probably plenty of improvements that can be made to get closer
to the gallium HUD.
Signed-off-by: Lionel Landwerlin
---
src/vulkan/util/gen_enum_to_str.py | 8
1 file changed, 8 insertions(+)
diff --git a/src/vulkan/util/gen_enum_to_str.py
b/src/vulkan/util/gen_enum_to_str.py
index fb9ecd65c6d..06f74eb487c 100644
--- a/src/vulkan/util/gen_enum_to_str.py
+++ b/src
Reviewed-by: Lionel Landwerlin
On 19/01/2019 19:04, Jason Ekstrand wrote:
---
src/intel/vulkan/anv_descriptor_set.c | 43 +++
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan
Thanks, pushed to master.
On 18/01/2019 18:09, Rafael Antognolli wrote:
Reviewed-by: Rafael Antognolli
On Fri, Jan 18, 2019 at 05:01:58PM +, Lionel Landwerlin wrote:
Doesn't save us a great deal of lines but at least they get decoded in
aubinators.
Signed-off-by: Lionel Landwerlin
Doesn't save us a great deal of lines but at least they get decoded in
aubinators.
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 2 ++
src/intel/genxml/gen11.xml | 2 ++
src/intel/genxml/gen7.xml | 2 ++
src/intel/genxml/gen75.xml | 2 ++
src
Reviewed-by: Lionel Landwerlin
On 18/01/2019 16:24, Jason Ekstrand wrote:
I like to keep things in good order so that you can find them.
---
src/intel/vulkan/anv_extensions.py | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_extensions.py
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/132
2 change in this MR :
* add some documentation to clarify how we choose pipeline flushes
invalidations
* narrow the CS stall & RT flushes for the query copies to track
only operations that write a destination buffer
For the
Looking at the change the binding table emission, I think the image++
has been moved such that it doesn't produce the same tables anymore.
Trying this change on CI :
https://github.com/djdeath/mesa/commit/a6b8eaf1325389d94d1d8a5b3bb952a362125eb2
On 17/01/2019 18:19, Clayton Craft wrote:
Put a few nits below, but otherwise looks good.
-
Lionel
On 13/11/2018 00:05, Jordan Justen wrote:
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_compute.c | 131 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 +
Sorry, for replying so late, going through my unread emails :(
We already have functions for doing this :
brw_load_register_reg
brw_load_register_imm32/64
brw_load_register_mem
Why not use those?
-
Lionel
On 13/11/2018 00:05, Jordan Justen wrote:
Signed-off-by: Jordan Justen
---
On 16/01/2019 14:01, Daniel Stone wrote:
Hi,
On Wed, 16 Jan 2019 at 13:01, Lionel Landwerlin
wrote:
- It seems we only get notifications when adding to an MR, I could like to
subscribe to particular tags
If you go to https://gitlab.freedesktop.org/mesa/mesa/labels/ then you
can subscribe
- I'm pretty happy with the discussion on a particular point/location of
a change.
A lot more readable than a long chain of email.
- Having issues with the comments not always showing up on a particular
commit of an MR (but it looks like gitlab is aware of that issue)
- The Rb/Ab tags were
On 16/01/2019 01:31, Matt Turner wrote:
On Mon, Oct 29, 2018 at 11:16 AM Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_sanitize_gpu.in | 55 ++-
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools
uffers
display as expected.
CC: Lionel Landwerlin
CC: Tapani Palli
Signed-off-by: Vivek Kasireddy
---
src/compiler/nir/nir_lower_tex.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index a618b86b34c..7058
On 12/01/2019 18:24, Ilia Mirkin wrote:
On Sat, Jan 12, 2019 at 9:40 AM Gert Wollny wrote:
I will not push it with
the strong NAK you gave, Ilia. To me consensus means that all who
contribute significantly to the project (like you certainly do) agree
or abstain, but don't object.
A single
On 12/01/2019 15:29, Jason Ekstrand wrote:
On January 12, 2019 03:06:07 Lionel Landwerlin
wrote:
On 12/01/2019 03:45, Jason Ekstrand wrote:
Instead of emitting all of the conditions for the cases of a switch
statement up-front, emit them on-the-fly as we emit the code for each
case
On 12/01/2019 03:45, Jason Ekstrand wrote:
Instead of emitting all of the conditions for the cases of a switch
statement up-front, emit them on-the-fly as we emit the code for each
case. The original justification for this was that we were going to
have to build a default case anyway which
On 12/01/2019 08:04, Jason Ekstrand wrote:
Even though no one's been brave enough to ever use this pass, I like to
keep it functionally working.
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_opt_gcm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/nir
For the series :
Reviewed-by: Lionel Landwerlin
On 11/01/2019 21:05, Jason Ekstrand wrote:
A long time in a galaxy far far away, there was a GLSLang bug with how
it handled samplers passed in as function parameters. (The bug can be
found here: https://github.com/KhronosGroup/glslang/issues
it had in v1,
the version in v2 was not equivalent and was incorrect. (Lionel)
Thanks! Do you think this should go to stable?
Anyway :
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c| 7 +--
src/intel/vulkan/anv_nir_apply_pipeline_layout
On 11/01/2019 12:40, Iago Toral wrote:
On Fri, 2019-01-11 at 12:31 +, Lionel Landwerlin wrote:
On 11/01/2019 12:12, Iago Toral Quiroga wrote:
We had defined MAX_IMAGES as 8, which we used to size the array for
image push constant data. The comment there stated that this was
for
gen8
On 11/01/2019 12:12, Iago Toral Quiroga wrote:
We had defined MAX_IMAGES as 8, which we used to size the array for
image push constant data. The comment there stated that this was for
gen8, but anv_nir_apply_pipeline_layout runs for all gens and writes
that array, asserting that we don't exceed
On 11/01/2019 12:05, Iago Toral Quiroga wrote:
Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching NIR'
Thanks a bunch :
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_pipeline_cache.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/intel/vulkan
On 11/01/2019 11:41, Iago Toral wrote:
On Fri, 2019-01-11 at 11:13 +, Lionel Landwerlin wrote:
On 11/01/2019 10:50, Iago Toral Quiroga wrote:
Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching
NIR'
---
src/intel/vulkan/anv_pipeline_cache.c | 5 +++--
1 file changed, 3
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