Re: [Mesa-dev] [PATCH] anv: Split dispatch tables into device and instance

Nice! Reviewed-by: Lionel Landwerlin On 13/10/2018 19:35, Jason Ekstrand wrote: There's no reason why we need generate trampoline functions for instance functions or carry N copies of the instance dispatch table around for every hardware generation. Splitting the tables and being more

[Mesa-dev] [PATCH] anv: Implement VK_EXT_pci_bus_info

Even though the Intel GPU are always at the same PCI location, all the info we need is already provided by libdrm. Let's be future proof. Signed-off-by: Lionel Landwerlin --- src/intel/vulkan/anv_device.c | 24 +++- src/intel/vulkan/anv_extensions.py | 1 + src/intel

Re: [Mesa-dev] [PATCH] vulkan: Add the fuchsia headers

Acked-by: Lionel Landwerlin On 13/10/2018 16:00, Jason Ekstrand wrote: These were missing in the last couple of spec updates. --- include/vulkan/vulkan.h | 4 +++ include/vulkan/vulkan_fuchsia.h | 58 + 2 files changed, 62 insertions(+) create

Re: [Mesa-dev] [PATCH 2/5] anv: Drop some VK_IMAGE_TILING_OPTIMAL checks

On 11/10/2018 17:21, Jason Ekstrand wrote: On Wed, Oct 10, 2018 at 5:17 PM Chad Versace > wrote: On Mon 01 Oct 2018, Jason Ekstrand wrote: > The DRM format modifiers extension adds a TILING_DRM_FORMAT_MODIFIER > which will be used for modifiers so we

Re: [Mesa-dev] [Mesa-stable] [PATCH] anv: Use separate MOCS settings for external BOs

On 10/10/2018 16:34, Juan A. Suarez Romero wrote: On Tue, 2018-10-02 at 16:11 -0500, Jason Ekstrand wrote: On Broadwell and above, we have to use different MOCS settings to allow the kernel to take over and disable caching when needed for external buffers. On Broadwell, this is especially

Re: [Mesa-dev] [PATCH 5/5] anv: add missing unlock in error path.

Oh dear... Reviewed-by: Lionel Landwerlin Eric, Jason : Could it be the wsi CTS test you've seen locking up forever? On 05/10/2018 01:00, Dave Airlie wrote: From: Dave Airlie Not going to matter, but be consistent. Found by coverity --- src/intel/vulkan/anv_allocator.c | 1 + 1 file

Re: [Mesa-dev] [PATCH] intel: Introducing Whiskey Lake platform

5/whl: Introducing Whiskey Lake platform") and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") v2: Lionel noticed that GT{1,2,3} on kernel wasn't following spec when looking to number of EUs, so kernel has been updated. Cc: Lionel Landwerlin Cc: José Roberto de So

Re: [Mesa-dev] [PATCH] vulkan/wsi/wayland: don't double free on error in get_presentation_support

Reviewed-by: Lionel Landwerlin On 05/10/2018 01:13, Dave Airlie wrote: From: Dave Airlie If we fail the init path then don't call the free path. Found by coverity --- src/vulkan/wsi/wsi_common_wayland.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vulkan

Re: [Mesa-dev] [PATCH] anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_START

for an MI_BATCH_BUFFER_START so we can just increment cmd_buffer->batch.end prior to emitting the command. Fixes: a0b133286a3 "anv/batch_chain: Simplify secondary batch return..." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926 Reviewed-by: Lionel Landwerlin --

Re: [Mesa-dev] [PATCH] anv: Use separate MOCS settings for external BOs

I'll reuse that! Reviewed-by: Lionel Landwerlin --- src/intel/vulkan/anv_allocator.c | 12 -- src/intel/vulkan/anv_batch_chain.c | 2 +- src/intel/vulkan/anv_blorp.c | 15 ++-- src/intel/vulkan/anv_device.c | 9 +-- src/intel/vulkan/anv_image.c | 5

[Mesa-dev] [PATCH] intel: error2aub: fix missing include

Signed-off-by: Lionel Landwerlin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108120 --- src/intel/tools/error2aub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 8a23d5ef1e7..b33cb1356f9 100644 --- a/src/intel/tools

Re: [Mesa-dev] [PATCH] intel/fs: Fix a typo in need_matching_subreg_offset

Wow... I was hoping to find a warning about this in coverity, but it doesn't seem to... Reviewed-by: Lionel Landwerlin On 02/10/2018 03:23, Jason Ekstrand wrote: This fixes a bunch of Vulkan subgroup tests on little core platforms. Fixes: 4150920b95 "intel/fs: Add a helper for emi

[Mesa-dev] [PATCH 17/20] intel/error2aub: add a verbose option

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 354e4e00924..2ad47010bdf 100644 --- a/src/intel/tools/error2aub.c +++ b/src

[Mesa-dev] [PATCH 19/20] intel/aub_viewer: add page editor from pml4 view

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer.cpp | 26 ++ 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp index 0f4528caf0d..b3cc1909bfa 100644 --- a/src

[Mesa-dev] [PATCH 10/20] intel/error2aub: build a list of BOs before writing them

them in the appropriate order. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 124 +--- 1 file changed, 87 insertions(+), 37 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 84dd8a126db..ff8622cde6d 100644

[Mesa-dev] [PATCH 20/20] intel/aub_viewer: make pphwsp/context image visible

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer.cpp | 64 1 file changed, 46 insertions(+), 18 deletions(-) diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp index b3cc1909bfa..21c76bb2f11 100644

[Mesa-dev] [PATCH 09/20] intel/aub_write: factorize context image/pphwsp/ring creation

We allocate GGTT entries and physical addresses are we create engines rather than having a fixed layout. Context images now receive a parameter argument which is used to setup pml4 & ring buffer addresses. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c |

[Mesa-dev] [PATCH 12/20] intel/error2aub: strenghten batchbuffer identifier marker

Found out that some base64 data matched the '---' identifier. We can avoid this by adding the surrounding spaces. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel

[Mesa-dev] [PATCH 11/20] intel/error2aub: identify buffers by engine

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 84 ++--- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index ff8622cde6d..ed11b35ffb1 100644 --- a/src/intel/tools

[Mesa-dev] [PATCH 13/20] intel/error2aub: parse other buffer types

We don't write them in the aub file yet. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 35 ++- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index ef8cd9dacf9

[Mesa-dev] [PATCH 16/20] intel/error2aub: write GGTT buffers into the aub file

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 69 +++ src/intel/tools/aub_write.h | 5 +++ src/intel/tools/error2aub.c | 82 +++-- 3 files changed, 144 insertions(+), 12 deletions(-) diff --git a/src/intel/tools

[Mesa-dev] [PATCH 14/20] intel/error2aub: annotate buffer with their address space

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 37 ++--- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 99c84bd15ef..0400da53470 100644 --- a/src/intel/tools

[Mesa-dev] [PATCH 05/20] intel/aub_write: switch to use i915_drm engine classes

Error states can contain vcs0/vcs1. The current ring_flag doesn't deal with this very well, leading to confusion between buffers of different types. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 73 +++- src/intel/tools/aub_write.h | 4

[Mesa-dev] [PATCH 15/20] intel/error2aub: store engine last ring buffer head/tail pointers

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 0400da53470..72531a97b18 100644 --- a/src/intel/tools/error2aub.c +++ b/src/intel/tools

[Mesa-dev] [PATCH 18/20] intel/error2aub: deal with GuC log buffer

When Guc is enabled, the error state will contain a "global" buffer for the GuC log buffer. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 2

[Mesa-dev] [PATCH 03/20] intel/aub_write: write header in init

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 152 --- src/intel/tools/aub_write.h | 3 +- src/intel/tools/error2aub.c | 4 +- src/intel/tools/intel_dump_gpu.c | 7 +- 4 files changed, 84 insertions(+), 82 deletions(-) diff

[Mesa-dev] [PATCH 07/20] intel/aub_write: store the physical page allocator in struct

We want to use this allocator in the next commit for GGTT pages. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 47 + src/intel/tools/aub_write.h | 1 + 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/src/intel/tools

[Mesa-dev] [PATCH 08/20] intel/aub_write: turn context images arrays into functions

We'll make them more parameterized in a later commit. As this is just a transitional commit, we allow ourself to leak the context images allocated in get_context_init(). We'll fix this in the next commit. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 62 src

[Mesa-dev] [PATCH 04/20] intel/aub_write: break execlist write in 2

We want to reuse the execlist submission, but won't need the ring buffer update. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 100 ++-- 1 file changed, 62 insertions(+), 38 deletions(-) diff --git a/src/intel/tools/aub_write.c b/src/intel

[Mesa-dev] [PATCH 00/20] intel/error2aub: place all buffers (GGTT/PPGTT)

the logical ring buffer and the context image of the context that triggered the hang. Cheers, Lionel Landwerlin (20): intel/aub_read: handle video engine execlists writes intel/aub_write: split comment section from HW setup intel/aub_write: write header in init intel/aub_write: break execlist write

[Mesa-dev] [PATCH 06/20] intel/aub_write: log mmio writes

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c index 7b435fcd893..a4cb474e1e7 100644 --- a/src/intel/tools/aub_write.c +++ b/src/intel/tools/aub_write.c @@ -238,6

[Mesa-dev] [PATCH 02/20] intel/aub_write: split comment section from HW setup

In the future we'll want error2aub to reuse the context image saved by i915 instead of the default one we write in intel_dump_gpu. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 75 +--- src/intel/tools/aub_write.h | 1 + src/intel

[Mesa-dev] [PATCH 01/20] intel/aub_read: handle video engine execlists writes

We don't strictly need this, but because we setup the engine in aub_write, it might be worth parsing it correctly for the sake of completeness. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_read.c | 23 +++ src/intel/tools/aub_read.h | 3 +++ 2 files changed, 26

Re: [Mesa-dev] [PATCH 1/4] anv/so_memcpy: Don't consider src/dst_offset when computing block size

Reviewed-by: Lionel Landwerlin On 12/09/2018 06:06, Jason Ekstrand wrote: The only thing that matters is the size since we never specify any offsets in terms of blocks. --- src/intel/vulkan/genX_gpu_memcpy.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel

Re: [Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block

On 16/09/2018 21:57, Bas Nieuwenhuizen wrote: On Tue, Sep 11, 2018 at 10:23 PM Lionel Landwerlin wrote: This new extension adds an implicitly allocated block of uniforms into the descriptors sets through a new descriptor type. We implement this by having a single BO in the descriptor set pool

Re: [Mesa-dev] [PATCH 1/5] anv/query: Increment an index while writing results

This series looks great to me. Thanks for the helpers everywhere :) Reviewed-by: Lionel Landwerlin On 15/09/2018 04:14, Jason Ekstrand wrote: Instead of computing an index at the end which we hope maps to the number of things written, just count the number of things as we go. --- src/intel

Re: [Mesa-dev] [PATCH 2/5] anv/query: Write both dwords in emit_zero_queries

I did wonder about using a PIPE_CONTROL with WriteImmediate, but there is a workaround in gpgpu mode so not really worth it... On 15/09/2018 04:14, Jason Ekstrand wrote: Each query slot is a uint64_t and we were only zeroing half of it. Fixes: 7ec6e4e68980 "anv/query: implement multiview

Re: [Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block

against MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS when creating pipeline layout. I'm not sure if such is necessary (since it's implicit rule), do you think there should there be check/assert? one minor possible addition below .. On 11.09.2018 23:22, Lionel Landwerlin wrote: This new extension adds

Re: [Mesa-dev] [PATCH v3 2/4] intel/decoder: Avoid freeing invalid pointer

Reviewed-by: Lionel Landwerlin On 06/09/2018 20:37, Sagar Ghuge wrote: v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin) v3: Handle case where genxml is empty (Lionel Landwerlin) Signed-off-by: Sagar Ghuge --- src/intel/common/gen_decoder.c | 18 +- 1

[Mesa-dev] [PATCH 1/2] anv: descriptors: split allocation function

The following commits will make the allocation more complicated so split the free list allocation logic out. Signed-off-by: Lionel Landwerlin --- src/intel/vulkan/anv_descriptor_set.c | 68 +++ src/intel/vulkan/anv_private.h| 5 +- 2 files changed, 42 insertions

[Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block

This new extension adds an implicitly allocated block of uniforms into the descriptors sets through a new descriptor type. We implement this by having a single BO in the descriptor set pool from which we source uniforms. Signed-off-by: Lionel Landwerlin --- src/intel/vulkan/anv_cmd_buffer.c

[Mesa-dev] [PATCH 0/2] anv: add support for VK_EXT_inline_uniform_block

Hi, Not much to explain here, it's all in the commits :) Cheers, Lionel Landwerlin (2): anv: descriptors: split allocation function anv: add support for VK_EXT_inline_uniform_block src/intel/vulkan/anv_cmd_buffer.c | 3 + src/intel/vulkan/anv_descriptor_set.c | 298

Re: [Mesa-dev] [PATCH] intel/tools: fix initial position of window in aubinator viewer

Reviewed-by: Lionel Landwerlin On 11/09/2018 08:32, Tapani Pälli wrote: Currently position is set before widgets are sized by gtk and calculation can get wrong results where window is positioned offscreen. Patch fixes this by setting aubfile window position as 0,0 only when size_allocate has

Re: [Mesa-dev] [PATCH] i965: Fix calculation of layers array length for isl_view

On 07/09/2018 16:32, Ilia Mirkin wrote: On Fri, Sep 7, 2018 at 11:09 AM, Danylo Piliaiev wrote: On 9/7/18 5:48 PM, Ilia Mirkin wrote: On Fri, Sep 7, 2018 at 10:41 AM, Danylo Piliaiev wrote: Comment for array_len field states: "Indicates the number of array elements starting at Base

[Mesa-dev] [PATCH] i965: compute the right number of array layers use base layer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856 Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri

[Mesa-dev] [PATCH] intel/genxml: remove SLM Enable bit from Gen11

Documentation says this bit is gone and we've indeed set all the slm field to 0 in common/gen_l3_config.c Signed-off-by: Lionel Landwerlin --- src/intel/genxml/gen11.xml | 1 - src/intel/vulkan/genX_cmd_buffer.c | 6 -- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

Re: [Mesa-dev] [PATCH v5] intel: compiler option msse2 and mstackrealign

It's good, pushed. On 07/09/2018 10:57, Lionel Landwerlin wrote: There was a test that failed, but I think it might be flakyness. I'm retrying one more time. Will get back to you in ~1h. - Lionel On 07/09/2018 10:32, Sergii Romantsov wrote: Hello, Lionel. Any regression with CI? On Thu, Sep

Re: [Mesa-dev] [PATCH 2/2] intel/genxml: remove SLM Enable bit on Gen11

Arg didn't this on anv which sets this be through genxml even though the documentation says it's reserved. Will send an update. On 07/09/2018 11:55, Lionel Landwerlin wrote: Signed-off-by: Lionel Landwerlin --- src/intel/genxml/gen11.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/src

[Mesa-dev] [PATCH 2/2] intel/genxml: remove SLM Enable bit on Gen11

Signed-off-by: Lionel Landwerlin --- src/intel/genxml/gen11.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 1b3befbbfc9..f497c2df825 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3544,7 +3544,6

[Mesa-dev] [PATCH 1/2] intel/genxml: turn SLM Enable bit into boolean

Signed-off-by: Lionel Landwerlin --- src/intel/genxml/gen10.xml | 2 +- src/intel/genxml/gen8.xml | 2 +- src/intel/genxml/gen9.xml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 541e4405716..abd5da297d6

[Mesa-dev] [PATCH] gallium: freedreno: fix compile issue

Signed-off-by: Lionel Landwerlin Fixes: daa19363def83c ("gallium: split depth_clip into depth_clip_near & depth_clip_far") --- src/gallium/drivers/freedreno/freedreno_draw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/freed

Re: [Mesa-dev] [PATCH v5] intel: compiler option msse2 and mstackrealign

There was a test that failed, but I think it might be flakyness. I'm retrying one more time. Will get back to you in ~1h. - Lionel On 07/09/2018 10:32, Sergii Romantsov wrote: Hello, Lionel. Any regression with CI? On Thu, Sep 6, 2018 at 12:33 PM, Lionel Landwerlin mailto:lionel.g.landwer

Re: [Mesa-dev] [PATCH 2/8] intel/decoders: add address space indicator to get BOs

On 06/09/2018 21:01, Jason Ekstrand wrote: On Thu, Sep 6, 2018 at 5:35 AM Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>> wrote: Some commands like MI_BATCH_BUFFER_START have this indicator. Signed-off-by: Lionel Landwerlin mailto:lionel.g.landwer...@int

Re: [Mesa-dev] [PATCH 1/8] intel/decoders: fix end of batch limit

On 06/09/2018 12:39, Eric Engestrom wrote: On Thursday, 2018-09-06 11:34:44 +0100, Lionel Landwerlin wrote: Pointer arithmetic... Signed-off-by: Lionel Landwerlin --- src/intel/common/gen_batch_decoder.c | 2 +- src/intel/tools/aubinator_viewer_decoder.cpp | 2 +- 2 files changed

Re: [Mesa-dev] [PATCH v1 1/2] i965/tools: 32bit compilation with meson

And pushed. On 06/09/2018 11:53, Lionel Landwerlin wrote: Oh right, I see, this is the only using gen_invalidate_range(). Thanks! Reviewed-by: Lionel Landwerlin On 06/09/2018 11:40, Sergii Romantsov wrote: With -Dtools=all compilation is passed now. At this moment looking additionally

Re: [Mesa-dev] [PATCH v1 1/2] i965/tools: 32bit compilation with meson

Oh right, I see, this is the only using gen_invalidate_range(). Thanks! Reviewed-by: Lionel Landwerlin On 06/09/2018 11:40, Sergii Romantsov wrote: With -Dtools=all compilation is passed now. At this moment looking additionally on linkage issue with building, have solution but would like

[Mesa-dev] [PATCH 6/8] intel/aubinator: fix ring buffer pointer

We can only start parsing commands from the head pointer. This was working fine up to now because we only dealt with a "made up" ring buffer (generated by aub_write) which always had its head at 0. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator.c | 4 ++--

[Mesa-dev] [PATCH 7/8] intel/aub_viewer: fix dynamic state printing

Identical fix to : commit cbd4bc1346f7397242e157bb66099b950a8c5643 Author: Jason Ekstrand Date: Fri Aug 24 16:04:03 2018 -0500 intel/batch_decoder: Fix dynamic state printing Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer_decoder.cpp | 4 ++-- 1 file changed, 2

[Mesa-dev] [PATCH 5/8] intel/decoders: limit number of decoded batchbuffers

IGT has this test hang test that works by having a batch buffer call itself. As our implementation of the decoding is perfectly mimicking the hardware, our decoder also "hangs". This change limits the number of batch buffer we'll decode before we bail to 100. Signed-off-by: Lionel

[Mesa-dev] [PATCH 2/8] intel/decoders: add address space indicator to get BOs

Some commands like MI_BATCH_BUFFER_START have this indicator. Signed-off-by: Lionel Landwerlin --- src/intel/common/gen_batch_decoder.c | 34 ++ src/intel/common/gen_decoder.h| 3 +- src/intel/tools/aubinator.c | 23 src

[Mesa-dev] [PATCH 1/8] intel/decoders: fix end of batch limit

Pointer arithmetic... Signed-off-by: Lionel Landwerlin --- src/intel/common/gen_batch_decoder.c | 2 +- src/intel/tools/aubinator_viewer_decoder.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/common/gen_batch_decoder.c b/src/intel/common

[Mesa-dev] [PATCH 8/8] intel/aub_viewer: Print blend states properly

Identical fix to : commit 70de31d0c106f58d6b7e6d5b79b8d90c1c112a3b Author: Jason Ekstrand Date: Fri Aug 24 16:05:08 2018 -0500 intel/batch_decoder: Print blend states properly Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer_decoder.cpp | 18 -- 1

[Mesa-dev] [PATCH 0/8] intel/tools: decoding fixes

) : https://github.com/djdeath/mesa/tree/wip/djdeath/tools_changes Cheers, Lionel Landwerlin (8): intel/decoders: fix end of batch limit intel/decoders: add address space indicator to get BOs intel/decoders: handle decoding MI_BBS from ring intel/decoders: read ring buffer length intel

[Mesa-dev] [PATCH 4/8] intel/decoders: read ring buffer length

Use this value to limit reading the ring buffer. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator.c | 4 +++- src/intel/tools/aubinator_viewer.cpp | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/aubinator.c b/src/intel/tools

[Mesa-dev] [PATCH 3/8] intel/decoders: handle decoding MI_BBS from ring

An MI_BATCH_BUFFER_START in the ring buffer acts as a second level batchbuffer (aka jump back to ring buffer when running into a MI_BATCH_BUFFER_END). Signed-off-by: Lionel Landwerlin --- src/intel/common/gen_batch_decoder.c | 6 +++--- src/intel/common/gen_decoder.h| 2

Re: [Mesa-dev] [PATCH v2] i965: clearify map_gtt cases

On 05/09/2018 18:01, Kenneth Graunke wrote: On Tuesday, September 4, 2018 3:30:42 AM PDT Lionel Landwerlin wrote: Both brw_bo_map_cpu() & brw_bo_map_wc() assert if mapping the underlying BO fails. Failing back to brw_bo_map_gtt() doesn't seem to make any sense for that reason. We also

Re: [Mesa-dev] [PATCH v1 1/2] i965/tools: 32bit compilation with meson

Aren't other tools affected as well? Thanks, - Lionel On 06/09/2018 10:59, Sergii Romantsov wrote: Building of 32bit mesa with meson causes issue: "implicit declaration of function ‘__builtin_ia32_clflush’". Fixed by adding msse2 compilation flag. Bugzilla:

Re: [Mesa-dev] [PATCH v2 2/4] intel/decoder: Avoid freeing invalid pointer

On 06/09/2018 05:12, Sagar Ghuge wrote: v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin) Signed-off-by: Sagar Ghuge --- src/intel/common/gen_decoder.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/intel/common/gen_decoder.c b/src

Re: [Mesa-dev] [PATCH v5] intel: compiler option msse2 and mstackrealign

Romantsov Reviewed-by: Dylan Baker Reviewed-by: Emil Velikov Reviewed-by: Lionel Landwerlin --- src/intel/Makefile.vulkan.am | 2 +- src/intel/meson.build | 1 + src/intel/vulkan/meson.build | 4 ++-- src/mesa/Android.libmesa_dricore.mk | 2 +- src/mesa

Re: [Mesa-dev] [PATCH 2/4] intel/decoder: Avoid freeing invalid pointer

On 05/09/2018 19:02, Sagar Ghuge wrote: Hi Lionel, Thanks for reviewing patches and comments. On 09/05/2018 10:29 AM, Lionel Landwerlin wrote: On 05/09/2018 18:19, Sagar Ghuge wrote: Signed-off-by: Sagar Ghuge ---   src/intel/common/gen_decoder.c | 4   1 file changed, 4 deletions

Re: [Mesa-dev] [PATCH] anv/pipeline: Only consider double elements which actually exist

On 05/09/2018 13:19, Jason Ekstrand wrote: On September 5, 2018 05:35:40 Lionel Landwerlin wrote: On 05/09/2018 11:24, Lionel Landwerlin wrote: On 05/09/2018 00:04, Jason Ekstrand wrote: The brw_vs_prog_data::double_inputs_read field comes directly from shader_info::double_inputs which may

Re: [Mesa-dev] [PATCH 4/4] intel: aubinator: Fix memory leaks

On 05/09/2018 18:19, Sagar Ghuge wrote: Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin --- src/intel/tools/aubinator.c | 25 + 1 file changed, 25 insertions(+) diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c index 55672fa073

Re: [Mesa-dev] [PATCH 3/4] intel/decoder: construct correct xml filename

On 05/09/2018 18:19, Sagar Ghuge wrote: construct correct gen xml filename when we try to load hardware xml description from a given path Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin --- src/intel/common/gen_decoder.c | 18 -- 1 file changed, 12

Re: [Mesa-dev] [PATCH 2/4] intel/decoder: Avoid freeing invalid pointer

On 05/09/2018 18:19, Sagar Ghuge wrote: Signed-off-by: Sagar Ghuge --- src/intel/common/gen_decoder.c | 4 1 file changed, 4 deletions(-) diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c index dbd060d53c..c44b8f060d 100644 ---

Re: [Mesa-dev] [PATCH 1/4] intel/decoder: add gen_spec_init method

(uint32_t) (uintptr_t) key; } +static struct gen_spec * +gen_spec_init() I think in C, you would write : gen_spec_init(void) With that fixed : Reviewed-by: Lionel Landwerlin +{ + struct gen_spec *spec; + spec = rzalloc(NULL, struct gen_spec); + if (spec == NULL) + return

Re: [Mesa-dev] [PATCH v4] i965: compiler option msse2 and mstackrealign

for Android's mks where msee4.1 is used. v4: Added for Vulkan also. CC: Fixes: 6b05c080f202 (i965: Compile with -msse3) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779 Signed-off-by: Sergii Romantsov Looks good to me : Reviewed-by: Lionel Landwerlin I would like Dylan

Re: [Mesa-dev] [PATCH v3] i965: compiler option msse2 and mstackrealign

On 05/09/2018 12:14, Sergii Romantsov wrote: Seems in case of 32-bit library, usage of msse2 makes some stack corruption or incorrect instructions. Usage with mstackrealign fixes that case. v2: fixed meson v3: Definition of c_sse2_args moved on the top (L.Landwerlin). Added mstackrealign

Re: [Mesa-dev] [PATCH] anv/pipeline: Only consider double elements which actually exist

On 05/09/2018 11:24, Lionel Landwerlin wrote: On 05/09/2018 00:04, Jason Ekstrand wrote: The brw_vs_prog_data::double_inputs_read field comes directly from shader_info::double_inputs which may contain inputs which are not actually read.  Instead of using it directly, AND it with inputs_read

Re: [Mesa-dev] [PATCH] anv/pipeline: Only consider double elements which actually exist

, we may end up subtracting too many elements when computing elem_count. Cc: mesa-sta...@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103241 Reviewed-by: Lionel Landwerlin --- src/intel/vulkan/genX_pipeline.c | 3 ++- 1 file changed, 2 insertions(+), 1

Re: [Mesa-dev] [PATCH v2] i965: compiler option msse2 and mstackrealign

On 05/09/2018 10:54, Sergii Romantsov wrote: Seems in case of 32-bit library, usage of msse2 makes some stack corruption or incorrect instructions. Usage with mstackrealign fixes that case. v2: fixed meson Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779 Signed-off-by: Sergii

Re: [Mesa-dev] [PATCH v1] i965: compiler option msse2 and mstackrealign

On 05/09/2018 10:55, Sergii Romantsov wrote: Hello, sorry for delay in answer. I think you might need to update the other build systems (Android.mk/meson) Have done it for meson, but with Android i can't check if issue present or if it will be fixed. And seems it requires some extra

Re: [Mesa-dev] [PATCH v1] i965: compiler option msse2 and mstackrealign

On 04/09/2018 11:46, Sergii Romantsov wrote: Seems in case of 32-bit library, usage of msse2 makes some stack corruption or incorrect instructions. Usage with mstackrealign fixes that case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779 Signed-off-by: Sergii Romantsov ---

[Mesa-dev] [PATCH v2] i965: clearify map_gtt cases

eter reserved for buffer objects which are always allocated linear). So explicitly assert if we ever run into this case. This makes checking the kernel about whether GTT maps are actually coherent unnecessary. v2: Add some explanation (Chris/Lionel) Signed-off-by: Lionel Landwerlin --- src/mesa/dri

[Mesa-dev] [PATCH] i965: clearify map_gtt cases

eter reserved for buffer object which are always allocated linear). So explicitly assert if we ever run into this case. This makes checking the kernel about whether GTT maps are actually coherent unnecessary. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_bufmgr.c

Re: [Mesa-dev] [PATCH] i965: Deny persistent mappings of incoherent GTT mmaps

, Lionel Landwerlin wrote: We would need a fairly recent kernel (drm-tip?) to test this in CI. I can't see any issue with this because we always have the meta path as a fallback for tiled buffers. Reviewed-by: Lionel Landwerlin On 30/08/2018 16:22, Chris Wilson wrote: On more recent HW

Re: [Mesa-dev] [PATCH] intel: compiler: remove dead local variables at optimization pass

On 03/09/2018 17:15, Jason Ekstrand wrote: On September 3, 2018 10:47:11 Lionel Landwerlin wrote: We're hitting an assert in gfxbench because one of the local variable is a sampler (according to Jason this isn't valid) : testfw_app: ../src/compiler/nir_types.cpp:551: void

Re: [Mesa-dev] [PATCH] intel: compiler: remove dead local variables at optimization pass

On 03/09/2018 16:47, Lionel Landwerlin wrote: We're hitting an assert in gfxbench because one of the local variable is a sampler (according to Jason this isn't valid) : testfw_app: ../src/compiler/nir_types.cpp:551: void glsl_get_natural_size_align_bytes(const glsl_type*, unsigned int

[Mesa-dev] [PATCH] intel: compiler: remove dead local variables at optimization pass

e constant removal (Jason/Lionel) Signed-off-by: Lionel Landwerlin --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ef5034d1e1e..8c1bcb99f8c 100644 --- a/src/intel/compiler/brw_nir.c +++ b

Re: [Mesa-dev] [PATCH v3] intel/decoder: fix the possible out of bounds group_iter

Done. - Lionel On 03/09/2018 08:55, andrey simiklit wrote: Hi all, Could somebody push this small patch to mesa? Regards, Andrii. On Mon, Aug 20, 2018 at 9:13 PM Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>> wrote: On 20/08/2018 17:20, asimiklit.w...@gma

Re: [Mesa-dev] [PATCH] i965: Deny persistent mappings of incoherent GTT mmaps

On 31/08/2018 12:43, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-08-31 12:32:23) On 31/08/2018 12:22, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-08-31 12:16:19) We would need a fairly recent kernel (drm-tip?) to test this in CI. Unpatched mesa, assumes all is fine. Post

Re: [Mesa-dev] [PATCH] i965: Deny persistent mappings of incoherent GTT mmaps

On 31/08/2018 12:22, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-08-31 12:16:19) We would need a fairly recent kernel (drm-tip?) to test this in CI. Unpatched mesa, assumes all is fine. Post-patch mesa, assumes all is broken. So we can quickly see if anything actually fails

Re: [Mesa-dev] [PATCH] i965: Deny persistent mappings of incoherent GTT mmaps

We would need a fairly recent kernel (drm-tip?) to test this in CI. I can't see any issue with this because we always have the meta path as a fallback for tiled buffers. Reviewed-by: Lionel Landwerlin On 30/08/2018 16:22, Chris Wilson wrote: On more recent HW, the indirect writes via

[Mesa-dev] [PATCH] intel/genxml: add FAULT_REG for Gen10/11

Signed-off-by: Lionel Landwerlin --- src/intel/genxml/gen10.xml | 33 + src/intel/genxml/gen11.xml | 33 + 2 files changed, 66 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 541e4405716

Re: [Mesa-dev] [PATCH 1/3] intel: aubinator: Adding missed platforms to the error message.

: Jordan Justen Signed-off-by: Rodrigo Vivi Reviewed-by: Lionel Landwerlin --- src/intel/tools/aubinator.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c index c22d191f14..edd11fe0f5 100644 --- a/src/intel/tools

Re: [Mesa-dev] [PATCH 2/3] intel: Introducing Amber Lake platform

ucing Amber Lake platform") Reported-by: Timo Aaltonen Cc: José Roberto de Souza Cc: Anuj Phogat Signed-off-by: Rodrigo Vivi Reviewed-by: Lionel Landwerlin --- include/pci_ids/i965_pci_ids.h | 3 ++- src/intel/compiler/test_eu_validate.cpp | 1 + src/intel/dev/gen_dev

Re: [Mesa-dev] [PATCH 3/3] intel: Introducing Whiskey Lake platform

On 30/08/2018 22:41, Rodrigo Vivi wrote: Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. This follows the ids and approach used on kernel's commit b9be78531d27 ("drm/i915/whl:

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel: decoder: unify MI_BB_START field naming

On 30/08/2018 16:23, Dylan Baker wrote: Quoting Lionel Landwerlin (2018-08-30 06:58:39) On 28/08/2018 17:01, Dylan Baker wrote: Quoting Lionel Landwerlin (2018-08-28 02:39:58) Yes, I think so. You asked on another commit too, both are related and this depends on other commits from Jason

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel: decoder: unify MI_BB_START field naming

On 28/08/2018 17:01, Dylan Baker wrote: Quoting Lionel Landwerlin (2018-08-28 02:39:58) Yes, I think so. You asked on another commit too, both are related and this depends on other commits from Jason. Here is a list in order of cherry picking : commit f430a37fa75f534c3a114b0ec546fa14f05f5da1

[Mesa-dev] [PATCH] anv: blorp: support multiple aspect blits

Newer blit tests are enabling depth blits. We currently don't support it but can do by iterating over the aspects masks (copy some logic from the CopyImage function). Signed-off-by: Lionel Landwerlin Fixes: 9f44745eca0e41 ("anv: Use blorp to implement VkBlitImage") Reviewed-by: Jaso

[Mesa-dev] [PATCH] intel: limit urb size for SKL/KBL/CFL GT1

EQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d Signed-off-by: Lionel Landwerlin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107505 --- src/intel/dev/gen_device_info.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/dev/gen_device_info.c b/src

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