Reviewed-by: Lionel Landwerlin
On 19/06/18 16:05, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/intel/tools/aubinator.c | 16
1 file changed, 16 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index e4fb8adada354253143c
On 19/06/18 16:05, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/intel/tools/aubinator.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index c8d79ae377d68285bd1e..e4fb8adada354253143c 100644
---
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.am |2 +
src/intel/tools/intel_dump_gpu.c | 1313 +
src/intel/tools/intel_dump_gpu.in | 107 +++
src/intel/tools/meson.build | 18 +
4 files changed, 1440 insertions(+)
create mode
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_aub.h | 2 +-
src/intel/tools/intel_dump_gpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/intel_aub.h b/src/intel/tools/intel_aub.h
index 2888515048f..74ca26ab9bb 100644
--- a/src/intel
Signed-off-by: Lionel Landwerlin
---
src/intel/dev/gen_device_info.c | 47 ++---
src/intel/dev/gen_device_info.h | 5
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index
Scott added new stuff in IGT.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_aub.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/src/intel/tools/intel_aub.h b/src/intel/tools/intel_aub.h
index 5f0aba8e68e..9ca548edaf3 100644
--- a/src/intel/tools
We already embed the headers, no need to redefine defines/structs.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_dump_gpu.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/src/intel/tools/intel_dump_gpu.c b/src/intel/tools
From: Scott D Phillips
Reviewed-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index 3852f32de36..2b6978da92d
From: Scott D Phillips
For gen8+, write out PPGTT tables in aub files so that full 48-bit
addresses can be serialized.
v2: Fix handling of `end` index in map_ppgtt
Signed-off-by: Scott D Phillips
Signed-off-by: Lionel Landwerlin
Cc: Jordan Justen
---
src/intel/tools/intel_aub.h | 3
From: Scott D Phillips
v2: by Lionel
Fix memfd_create compilation issue
Fix pml4 address stored on 32 instead of 64bits
Return no buffer if first ppgtt page is not mapped
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 76 -
1
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 82 -
1 file changed, 54 insertions(+), 28 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 3f9047e69a8..0438f96cd1b 100644
--- a/src/intel/tools
With PPGTT mappings, our aubinator implementation can be quite slow if
we request a buffer that doesn't exist. Instead of doing a PPGTT walk
for invalid addresses (0 lengths), wait until we're sure we want to
decode the data.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
---
src/intel/common/gen_batch_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index 81d8298c28b..fc0ff95a476 100644
from the aub file and
fetch them on request by the batch decoder. As a result we can get rid
of the 1<<40 mmapped address space and only rely on the mmap aub file
\o/
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 130
1 file changed, 72
We use memfd to store physical pages as they get read/written to and
the GGTT entries translating virtual address to physical pages.
Based on a commit by Scott Phillips.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 256 ++--
1 file changed
These memory offsets are stored in the gen_batch_decode_ctx.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index c8d79ae377d..949ba96e556 100644
--- a/src/intel
From: Jason Ekstrand
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you embed a
rb_node struct the data structure you intend to put into the
tree.
The
Now that we rely on mmap of the data to parse, we can't process the
standard input anymore.
This isn't much of a big deal because we have in-process batch decoder
(run with INTEL_DEBUG=batch) that supports essentially doing the same
thing.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools
Hi all,
This is a respin of v1 to break down the dense ppgtt handling commit.
This series also includes a copy of aubdump with the changes that
Scott made there to emit PPGTT mappings.
Cheers,
Jason Ekstrand (1):
util: rb-tree: A simple, invasive, red-black tree
Lionel Landwerlin (12
read (at least for me). Are these
changes so related that they couldn't be split up?
Rafael
On Thu, Jun 14, 2018 at 06:11:38PM +0100, Lionel Landwerlin wrote:
From: Scott D Phillips
v2: by Lionel
Fix memfd_create compilation issue
Fix pml4 address stored on 32 instead of 64bits
Re
I forgot that the last patch won't make it (too big).
The branch is here :
https://github.com/djdeath/mesa/tree/wip/djdeath/perf-extract
Cheers,
-
Lionel
On 18/06/18 18:39, Lionel Landwerlin wrote:
Hi all,
This series can be broken in 3 parts :
- Making the performace query code API
One register that was in the configuration turned out to be IVB
specific. Let's just drop it.
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-hsw.xml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel/perf/oa-hsw.xml b/src/intel/perf/oa-hsw.xml
index
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-glk.xml | 113 +-
1 file changed, 112 insertions(+), 1 deletion(-)
diff --git a/src/intel/perf/oa-glk.xml b/src/intel/perf/oa-glk.xml
index 68fcd2d6dde..e3da757f46f 100644
--- a/src/intel/perf/oa-glk.xml
The Gen10+ expected format adds an additional counter which we can't
disclose yet. We can still make the size of the expected query result
match.
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/gen_perf_mdapi.h| 1 +
.../drivers/dri/i965
One more thing we want to share between the different APIs.
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/gen_perf_mdapi.h | 3 +++
src/mesa/drivers/dri/i965/brw_performance_query_mdapi.c | 3 +--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src
No functional changes, just cleaning up the names of the counters.
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-chv.xml | 50 +++
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/intel/perf/oa-chv.xml b/src/intel/perf/oa-chv.xml
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-bxt.xml | 113 +-
1 file changed, 112 insertions(+), 1 deletion(-)
diff --git a/src/intel/perf/oa-bxt.xml b/src/intel/perf/oa-bxt.xml
index 5b18369b2cb..db018a3d62b 100644
--- a/src/intel/perf/oa-bxt.xml
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-bdw.xml | 203 +-
1 file changed, 202 insertions(+), 1 deletion(-)
diff --git a/src/intel/perf/oa-bdw.xml b/src/intel/perf/oa-bdw.xml
index 258fcacfd59..714a1f08ea7 100644
--- a/src/intel/perf/oa-bdw.xml
---
src/intel/perf/gen_perf_mdapi.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/perf/gen_perf_mdapi.h b/src/intel/perf/gen_perf_mdapi.h
index a2f8066dcf4..45fe171b030 100644
--- a/src/intel/perf/gen_perf_mdapi.h
+++ b/src/intel/perf/gen_perf_mdapi.h
@@ -108,6 +108,10 @@
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-cflgt2.xml | 103 ++-
src/intel/perf/oa-cflgt3.xml | 103 ++-
2 files changed, 204 insertions(+), 2 deletions(-)
diff --git a/src/intel/perf/oa-cflgt2.xml b/src/intel/perf/oa
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-sklgt2.xml | 103 ++-
src/intel/perf/oa-sklgt3.xml | 103 ++-
src/intel/perf/oa-sklgt4.xml | 103 ++-
3 files changed, 306 insertions(+), 3
We'll want to reuse this in our Vulkan extension.
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/gen_perf.c | 135 ++
src/intel/perf/gen_perf.h | 81 ++-
.../drivers/dri/i965/brw_performance_query.c | 134
Signed-off-by: Lionel Landwerlin
---
src/intel/perf/oa-kblgt2.xml | 103 ++-
src/intel/perf/oa-kblgt3.xml | 103 ++-
2 files changed, 204 insertions(+), 2 deletions(-)
diff --git a/src/intel/perf/oa-kblgt2.xml b/src/intel/perf/oa
Signed-off-by: Lionel Landwerlin
---
src/intel/dev/gen_device_info.h | 1 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 3 +--
src/mesa/drivers/dri/i965/intel_screen.c | 4 +++-
src/mesa/drivers/dri/i965/intel_screen.h | 3 ---
4 files changed, 5
We'll want to reuse those structures later on.
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.sources| 3 +-
src/intel/perf/gen_perf_mdapi.h | 119 ++
.../dri/i965/brw_performance_query_mdapi.c| 103 ++-
3 files
We want to reuse this in Anv.
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.sources| 3 +-
src/intel/perf/gen_perf_mdapi.c | 116 ++
src/intel/perf/gen_perf_mdapi.h | 8 ++
src/intel/perf/meson.build
Signed-off-by: Lionel Landwerlin
---
src/intel/dev/gen_device_info.h | 7 +++
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_performance_query.c | 8 ++--
.../dri/i965/brw_performance_query_mdapi.c| 6 +++---
src/mesa
Those 2 registers have masks on the upper 16bits of field values that
should be applied in HW.
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 3 +++
src/intel/genxml/gen11.xml | 3 +++
src/intel/genxml/gen7.xml | 4
src/intel/genxml/gen75.xml | 4
src/intel/genxml
We would like to reuse performance query metrics in other APIs. Let's
make the query code dealing with the processing of raw counters into
human readable values API agnostic.
Signed-off-by: Lionel Landwerlin
---
src/intel/Android.mk | 1 +
src/intel/Android.perf.mk
atch 19)
Cheers,
Lionel Landwerlin (19):
intel: genxml: add mask fields for INSTPM/CS_DEBUG_MODE2 registers
i965: store device revision in gen_device_info
i965: extract performance query metrics
i965: move mdapi data structure to intel/perf
i965: move OA accumulation code to intel/perf
i96
Hey Danylo,
Thanks for this patch.
I'm not really an expert here but my understanding is that it should
reflect the number of bits in fixed point precision.
We use 32bits floats in the packets sent to the hardware.
Quoting the spec :
"If the implementation truely has floating point viewport
I was wondering whether we should pick up the patch version from the
registry.
Anyway :
Reviewed-by: Lionel Landwerlin
On 18/06/18 00:29, Jason Ekstrand wrote:
The Vulkan API has only one patch version shared among all of the
major.minor versions. We should also advertise the same patch
Had the same patch in a branch :)
Patches 1 & 2 are
Reviewed-by: Lionel Landwerlin
On 15/06/18 21:12, Rafael Antognolli wrote:
---
src/intel/genxml/gen10.xml | 4
src/intel/genxml/gen11.xml | 4
src/intel/genxml/gen6.xml | 5 +
src/intel/genxml/gen7.xml | 5 +
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index 81d8298c28b..fc0ff95a476 100644
--- a/src/intel/common
The Masking is only needed for entry matching.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 2a1b91c0e54..6f2e0d503df 100644
--- a/src/intel
With PPGTT mappings, our aubinator implementation can be quite slow if
we request a buffer that doesn't exist. Instead of doing a PPGTT walk
for invalid addresses (0 lengths), wait until we're sure we want to
decode the data.
Signed-off-by: Lionel Landwerlin
---
src/intel/common
Now that we rely on mmap of the data to parse, we can't process the
standard input anymore.
This isn't much of a big deal because we have in-process batch decoder
(run with INTEL_DEBUG=batch) that supports essentially doing the same
thing.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools
y Kristian.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 85 -
1 file changed, 28 insertions(+), 57 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 6f2e0d503df..c9308b56137 100644
--- a/src/i
No functional changes.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 95 +++--
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 99cd010dd9d..2a1b91c0e54 100644
From: Jason Ekstrand
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you embed a
rb_node struct the data structure you intend to put into the
tree.
The
From: Scott D Phillips
Reviewed-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index 3852f32de36..2b6978da92d
with those mappings.
This series replaces what I sent earlier in :
https://patchwork.freedesktop.org/series/44535/
Cheers,
Jason Ekstrand (1):
util: rb-tree: A simple, invasive, red-black tree
Lionel Landwerlin (6):
intel: batch-decoder: don't asks for constant BO until decoding
intel: batch
From: Scott D Phillips
v2: by Lionel
Fix memfd_create compilation issue
Fix pml4 address stored on 32 instead of 64bits
Return no buffer if first ppgtt page is not mapped
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 460
1
On 14/06/18 14:01, Lionel Landwerlin wrote:
On 13/06/18 21:26, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 46 ++
src/mesa/drivers/dri/i965/brw_bufmgr.h | 1 -
2 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers
On 13/06/18 21:26, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 46 ++
src/mesa/drivers/dri/i965/brw_bufmgr.h | 1 -
2 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
On 11/06/18 14:22, Eric Engestrom wrote:
From: Eric Engestrom
v2: intel_miptree_release() already takes care of the planes, no need
to hand-code the loop (Lionel)
Coverity ID: 1436909
Cc: Lionel Landwerlin
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for plana
On 10/06/18 18:42, Eric Engestrom wrote:
Coverity ID: 1436909
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV
images"
Signed-off-by: Eric Engestrom
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 10 insertions(+), 2
On 10/06/18 13:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-10 13:15:10)
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which uses
from the aub file and
fetch them on request by the batch decoder. As a result we can get rid
of the 1<<40 mmapped address space and only rely on the mmap aub file
\o/
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 116 +---
1 file changed, 68
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index a8e709358cd..963adbec271 100644
--- a/src/intel/common
Sorry for missing that.
Fixes: e73d136a023080 ("vulkan/wsi/x11: Implement FIFO mode.")
Reviewed-by: Lionel Landwerlin
On 01/06/18 12:16, Cameron Kumar wrote:
The queue_manager thread can access the images from x11_present_to_x11,
hence this reorder prevents dereferencing of danglin
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/intel_screen.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly
handle RGBX formats. Also, we don't want to make decisions based on
those in the first place because we can't render to RGBA and we use the
non-sRGB
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_screen.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
This reworks it to work like query_dma_buf_modifiers and, in particular,
makes it more flexible so that we can disallow a non-static set of
formats.
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in. We also
check against the array size of the table because some valid formats
such as CCS
You left out isl_buffer_fill_image_param() in isl_storage_image.c
Regardless, this is an improvement and with this I actually hit the
assert :)
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
We add two assertions instead of one because the first assertion
Reviewed-by: Lionel Landwerlin
On 07/06/18 01:48, Jason Ekstrand wrote:
There were some places that were calling anv_semaphore_impl_cleanup and
neither deleting the semaphore nor setting the type back to NONE. Just
set it to NONE in impl_cleanup to avoid these issues.
Bugzilla: https
sing them shouldn't hurt.
On Wed, Jun 6, 2018 at 10:36 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Found by Eero.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin mailto:lionel.g.landw
Found by Eero.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Plamena Manolova (v2)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 16
1
On 06/06/18 18:27, Jason Ekstrand wrote:
On Wed, Jun 6, 2018 at 7:57 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Found by Eero.
v2: Add G16R16 formats (Lionel)
Signed-off-by: Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>>
Bug
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:17, Jason Ekstrand wrote:
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in. We also
check against the array size of the table because some valid formats
such as CCS
s > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits > 0 &&
+ fmtl->channels.a.type == ISL_VOID;
}
enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
Do you want to use it in isl_buffer_fill_
Found by Eero.
v2: Add G16R16 formats (Lionel)
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index a591dfcd7d2
We have no corresponding ISL format for XBGR2101010.
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/i965/intel_screen.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src
An invalid format could be computed through the
modifier_is_supported() helper. Better verify each step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/drivers/dri/i965
An invalid format could be computed through the
modifier_is_supported() helper. Better verify each step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10664
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/drivers/dri/i965
On 05/06/18 11:28, Lionel Landwerlin wrote:
Looks like we forgot to update this bit of the driver for softpin.
Signed-off-by: Lionel Landwerlin
I guess :
Fixes: 4affeba1e9eb42 ("anv: Soft-pin everything else")
---
src/intel/vulkan/anv_intel.c | 2 ++
1 file changed, 2
Looks like we forgot to update this bit of the driver for softpin.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c
index 431cef5c6ac..06db5787a9c 100644
--- a/src
Reviewed-by: Lionel Landwerlin
On 04/06/18 11:18, Kenneth Graunke wrote:
On pre-4.13 kernels, which don't support I915_EXEC_BATCH_FIRST, we move
the validation list entry to the end...but incorrectly left the exec_bo
array alone, causing a mismatch where exec_bos[0] no longer corresponded
Reviewed-by: Lionel Landwerlin
On 04/06/18 01:38, Mauro Rossi wrote:
Changes to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, >bo_cache, dma_
Reviewed-by: Lionel Landwerlin
On 04/06/18 01:48, Mauro Rossi wrote:
Changes to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, >bo_cache, dma_
anks for the fix!
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_android.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c
index ed5da5b537..45a21dcfc3 100644
--- a/src/intel/vulkan/anv_android.c
+++ b/
On 03/06/18 21:22, Mauro Rossi wrote:
Hi there,
2018-06-03 21:52 GMT+02:00 Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>:
On 03/06/18 19:41, Mauro Rossi wrote:
Change to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
On 03/06/18 19:41, Mauro Rossi wrote:
Change to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, >bo_cache, dma_buf, );
~~~
Acked-by: Lionel Landwerlin
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On 22/05/18 18:02, Eric Engestrom wrote:
The modifiers array hasn't been initialised by then, much less with data
that would need freeing.
Move the label after the loop to fix this.
Signed-off-by: Eric Engestrom <eric.engest...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.
On 21/05/18 23:25, Lionel Landwerlin wrote:
On 21/05/18 23:21, Anuj Phogat wrote:
2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).
Reported-by: Clayton Craft <clayton.a.cr...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmai
desktop.org>
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: Francisco Jerez <curroje...@riseup.net>
It matches my reading of the documentation :)
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/dev/gen_device_info.c | 2 +-
1 file
stall prior to ISP disable"
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
I dropped it thinking that because the end of batchbuffer was right
after that, it wouldn't matter.
Since the similator complains :
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Than
<rafael.antogno...@intel.com>
On Wed, May 09, 2018 at 12:39:51AM +0100, Lionel Landwerlin wrote:
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/
gno...@intel.com>
On Wed, May 09, 2018 at 12:39:51AM +0100, Lionel Landwerlin wrote:
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel
It's just not possible to have a device with no subslices.
CID: 1433511
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/dev/gen_device_info.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel scoreboard
v4: Drop the post sync operation (Lionel)
Signed-off-by: Li
Hi,
A quick update on the i965 patch, dropping the Post-Sync operation.
Thanks a lot,
Lionel Landwerlin (2):
i965: require post sync operation prior to ISP disable
anv: emit stall at pixel scoreboard before ISP disable
src/intel/vulkan/genX_cmd_buffer.c | 9 -
src/mesa
We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context
restore.")
---
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel scoreboard
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com
We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context
restore.")
---
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