Re: [Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

On Wed, May 03, 2017 at 11:36:29PM -0700, Kenneth Graunke wrote: > On Wednesday, May 3, 2017 7:52:01 PM PDT Pohjolainen, Topi wrote: > > On Wed, May 03, 2017 at 05:11:45PM -0700, Rafael Antognolli wrote: > > > On Wed, May 03, 2017 at 08:28:24PM +0300, Pohjolainen, Topi wrote: &

[Mesa-dev] [PATCH] i965: Move MOCS macros to brw_state.h.

brw_state.h is a better place to keep them, instead of brw_context.h. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h | 42 - src/mesa

Re: [Mesa-dev] [PATCH 1/3] mesa: Simplify _mesa_primitive_restart_index().

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> On Thu, May 04, 2017 at 08:13:05AM -0700, Kenneth Graunke wrote: > We can use a simple shift equation rather than a switch statement. > --- > src/mesa/main/varray.c | 12 ++-- > 1 file changed, 2 insertion

[Mesa-dev] [PATCH] genxml: Fix 3DSTATE_DEPTH_BUFFER length on gen5.

The hardware docs are wrong, but the length used in the xml is also wrong. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen5.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/ge

Re: [Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

On Wed, May 03, 2017 at 08:28:24PM +0300, Pohjolainen, Topi wrote: > On Mon, May 01, 2017 at 06:43:02PM -0700, Rafael Antognolli wrote: > > These macros are defined in brw_defines.h, which contains a lot of > > macros that conflict with autogenerated code from genxml. But we need

Re: [Mesa-dev] [PATCH v03 17/38] genxml: Add rules to build gen4, gen45 and ge5.

t 06:43:05PM -0700, Rafael Antognolli wrote: > > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> > > --- > > src/mesa/drivers/dri/i965/Makefile.am | 12 > > src/mesa/drivers/dri/i965/Makefile.sources | 9 + > > src/mesa

Re: [Mesa-dev] i965: Use isl for hiz and stencil

o start using isl state emitter for > depth-hiz-stencil. > > CC: Jason Ekstrand <ja...@jlekstrand.net> > CC: Nanley Chery <nanley.g.ch...@intel.com> > CC: Chad Versace <chadvers...@chromium.org> > CC: Rafael Antognolli <rafael.antogno...@intel.com> > &g

Re: [Mesa-dev] [PATCH] i965: Drop "Destination Element Offset" from Ironlake SGVs.

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> On Fri, Apr 28, 2017 at 05:04:05PM -0700, Kenneth Graunke wrote: > The Ironlake documentation is terrible, so it's unclear whether or not > this field exists there. It definitely doesn't exist on Sandybridge > and later.

Re: [Mesa-dev] [PATCH 08/11] intel/decoder: Fix indentation

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> On Mon, May 01, 2017 at 01:54:52PM -0700, Matt Turner wrote: > --- > src/intel/common/gen_decoder.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/intel/common/gen_decoder

Re: [Mesa-dev] [PATCH 05/11] genxml: Remove brackets from kernel start pointer names

Patch is Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> On Mon, May 01, 2017 at 01:54:49PM -0700, Matt Turner wrote: > Newer Gens' names don't have the brackets. Having common names will make > some later patches simpler. > --- > src/intel/genxml/gen4.xml |

[Mesa-dev] [PATCH] i965: Make the field computed_depth_mode an enum.

Since the enum is in the same header now, we can use it as the type of the field. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- PS: We can merge this with the previous patch too if that's better. src/intel/compiler/brw_compiler.h | 2 +- src/intel/compiler/brw_

[Mesa-dev] [PATCH] i965: Move enums to brw_compiler.h.

These enums live inside struct brw_wm_prog_data, so it makes sense to keep them in the same header. It also allows to use them without including brw_eu_defines.h. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/compiler/brw_compiler.h

Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

On Tue, May 02, 2017 at 08:44:05AM -0700, Jason Ekstrand wrote: > On Tue, May 2, 2017 at 8:28 AM, Rafael Antognolli > <rafael.antogno...@intel.com> > wrote: > > On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote: > > On Mon, May 1, 2017 at

Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote: > On Mon, May 1, 2017 at 6:43 PM, Rafael Antognolli > <rafael.antogno...@intel.com> > wrote: > > We need to use some enums inside genX_state_upload.c, but including the > whole header will cause s

Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

On Tue, May 02, 2017 at 09:38:53AM +0100, Emil Velikov wrote: > On 2 May 2017 at 09:32, Emil Velikov <emil.l.veli...@gmail.com> wrote: > > Hi Rafael, > > > > On 2 May 2017 at 02:43, Rafael Antognolli <rafael.antogno...@intel.com> > > wrote

[Mesa-dev] [PATCH v03 37/38] i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen6_cc.c | 90 + src/mesa/drivers/dri/i965/genX_state_up

[Mesa-dev] [PATCH v03 33/38] i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.

Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the scissor states using GENX(SCISSOR_RECT_pack), generated from genxml. v3: - Remove old code (Ken) - Style fixes (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke

[Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h | 41 +- src/mesa/drivers/dri/i965/brw_defines.h | 42 +-- 2 files changed, 41 insertions(+), 42 deletions(-) diff --git a/src/mesa/drive

[Mesa-dev] [PATCH v03 13/38] anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

In a previous patch some enums were split out from brw_eu_defines.h, so they could be used by genxml based code. anv can also benefit from this. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/vulkan/genX_pipeline.c | 4 +++- 1 file changed, 3 insertions

[Mesa-dev] [PATCH v03 38/38] i965: Port gen4+ state emitting code to genxml.

On this patch, we port: - brw_polygon_stipple - brw_polygon_stipple_offset - brw_line_stipple - brw_drawing_rect v2: - Also emit states for gen4-5 with this code. v3: - Style fixes and remove excessive checks (Ken). Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.

[Mesa-dev] [PATCH v03 07/38] genxml: 3DSTATE_VS rename Function Enable to Enable.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/blorp/blorp_genX_exec.h | 2 +- src/intel/genxml/gen6.xml | 2 +- src/intel/genxml/gen7.xml | 2 +- src/intel/genxml/gen75.xml| 2 +

[Mesa-dev] [PATCH v03 11/38] genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>

[Mesa-dev] [PATCH v03 19/38] i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs from genxml. v3: - Lots style fixes (Ken) - Do not set CullTestEnableBitMask on Gen8+ (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h

[Mesa-dev] [PATCH v03 31/38] i965: Port gen6+ blend state code to genxml.

Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from genxml. v3: - style fixes (Ken) - cleanup to remove excessive #ifdef's (Ken) - remove memset (Ken) - disable blend.AlphaToCoverageDitherEnable on gen6 (Ken) Signed-off-by: Rafael Antognolli <rafael.anto

[Mesa-dev] [PATCH v03 21/38] i965: Add brw_get_line_width_float.

That helper function returns the line width as a float, and is then used by brw_get_line_width to return the fixed point width. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH v03 25/38] i965: Port gen7+ 3DSTATE_SOL to genxml.

Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Add helpers to assign struct brw_address (Kristian) v3: - Rename MOCS -> SOBufferMOCS - Do not re-declare MOCS macros (Ken). - Style and code reorganization (Ken). Signed-off-by: Raf

[Mesa-dev] [PATCH v03 20/38] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from genxml. v3: - Style fixes (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_state.h | 1

[Mesa-dev] [PATCH v03 36/38] i965: Port gen6+ multisample state emitting code to genxml.

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit. v3: - Remove dead code (Ken) - Simplify #if/#endif (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_context.h|

[Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

-by: Rafael Antognolli <rafael.antogno...@intel.com> Acked-by: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/Makefile.sources | 1 +- src/intel/compiler/brw_defines_common.h | 46 ++- src/intel/compiler/brw_eu_define

[Mesa-dev] [PATCH v03 17/38] genxml: Add rules to build gen4, gen45 and ge5.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.am | 12 src/mesa/drivers/dri/i965/Makefile.sources | 9 + src/mesa/drivers/dri/i965/brw_state.h | 1 + 3 files changed, 22 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH v03 09/38] genxml: Rename "Function Enable" to "Enable".

Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen6.xml| 2 +- src/intel/gen

[Mesa-dev] [PATCH v03 28/38] i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.

Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses pack structs from genxml. v3: - Style fixes and moving code around to be cleaner (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> -

[Mesa-dev] [PATCH v03 18/38] i965: Port Gen6+ DEPTH_STENCIL state to genxml.

ecape.org> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.sources| 2 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/gen6_

[Mesa-dev] [PATCH v03 26/38] i965: Port gen7+ 3DSTATE_PS to genxml.

Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use render_bo helper to setup brw_address (Kristian) v3: - Style fixes and code cleanup (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke

[Mesa-dev] [PATCH v03 23/38] i965: Port Gen7+ 3DSTATE_SBE state to genxml.

Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use ACTIVE_COMPONENT_XYZW from gen9.xml. v3: - Style fixes (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org&

[Mesa-dev] [PATCH v03 22/38] i965: Port gen6+ 3DSTATE_SF to genxml.

Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs from genxml. v3: - Reorganize code and reduce #if/#endif's (Ken) - Style fixes (Ken) - Always set AALINEDISTANCE_TRUE (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drive

[Mesa-dev] [PATCH v03 24/38] i965: Remove calculate_attr_overrides.

This function now lives inside genX_state_upload.c. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.sources | 1 +- src/mesa/drivers/dri/i965/brw_state.h | 8 +- src/

[Mesa-dev] [PATCH v03 29/38] i965: Port gen6+ 3DSTATE_VS to genxml.

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use render_bo helper to setup brw_address (Kristian) v3: - Bring back some comments for gen6 and remove _NEW_TRANSFORM blocks from gen7+. Signed-off-by: Rafael Antognolli <rafael.anto

[Mesa-dev] [PATCH v03 16/38] i965: Get real per-gen atom lists

From: Kenneth Graunke Make atoms initalization compile conditionally based on the target platform. --- src/mesa/drivers/dri/i965/brw_state.h | 12 +- src/mesa/drivers/dri/i965/brw_state_upload.c | 385 +---

[Mesa-dev] [PATCH v03 35/38] i965: Port gen4+ emit vertices code to genxml.

) - Use macros for MOCS values. - Do not use #ifndef NDEBUG on code that is actually used (Ken) v3: - Style and code clenup (Ken) - Keep some of the common code inside brw_draw_upload.c (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH v03 34/38] i965: Port push constant code to genxml.

macro (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 4 +- src/mesa/drivers/dri/i965/brw_state.h | 5 +- src/mesa/drivers/dri/i965/gen6_gs_state.c | 33 +--- src/mesa/drivers/dri/i965/gen6_vs_s

[Mesa-dev] [PATCH v03 03/38] genxml: Update xml for 3DSTATE_SF.

- Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <

[Mesa-dev] [PATCH v03 30/38] i965: Port gen6+ state emitting code to genxml.

Ported in this patch: - 3DSTATE_DS - 3DSTATE_GS - 3DSTATE_HS - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL v3: - Remove NEW_TRANSFORM blocks (Ken) - Bring back some comments and workaround for Ivybridge (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --

[Mesa-dev] [PATCH v03 27/38] i965: Port gen6+ 3DSTATE_WM to genxml.

) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 14 +- src/mesa/drivers/dri/i965/gen6_wm_state

[Mesa-dev] [PATCH v03 05/38] genxml: Add alias for MOCS.

Use an alias, so we can set the same value as the #define's. v3: - Call it "SO Buffer MOCS" to follow the most common naming scheme. - Add alias for gen7 and gen75 too (Ken). Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen7.xml

[Mesa-dev] [PATCH v03 15/38] i965: Add genxml related plumbing in a new genX_state_upload.c file.

From: Kenneth Graunke v3: - Drop aub parameter (Ken) Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources| 15 ++- src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++- 2 files changed, 119

[Mesa-dev] [PATCH v03 02/38] genxml: Rename clip enable property.

There are two variants: - Clip Enable - CLIP Enable (on gen6) Rename everything to Clip Enable. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen4.xml | 2 +- src/intel/genxml/gen45.xml

[Mesa-dev] [PATCH v03 08/38] genxml: Clip guardbands are float, not int.

This makes genxml create the right struct types, and generate the right batch commands. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen6.xml | 8 1 file changed, 4 insertions(+),

[Mesa-dev] [PATCH v03 10/38] genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

Name the options to "Pixel Location": - PIXLOC_CENTER -> CENTER - PIXLOC_UL_CORNER -> UL_CORNER Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/blorp/blorp_genX_exec.h | 4 +--

[Mesa-dev] [PATCH v03 32/38] i965: Port gen7+ 3DSTATE_TE to genxml.

Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 1

[Mesa-dev] [PATCH v03 06/38] genxml: Make "Reorder Mode" fields consistent.

From: Kenneth Graunke <kenn...@whitecape.org> Both GS and SOL have these fields. Some were ReorderEnable = true, some were ReorderMode = REORDER_TRAILING, and some were just TRAILING. Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Rafael Antognolli <

[Mesa-dev] [PATCH v03 04/38] genxml: Add missing field values to 3DSTATE_SBE.

Fill out "Attribute Active Component Format" possible values. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen9.xml | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-)

[Mesa-dev] [PATCH v03 00/38] Rebased and reviewed series to convert state emitting code to genxml.

g in a new genX_state_upload.c file. i965: Get real per-gen atom lists i965: Port Gen6+ DEPTH_STENCIL state to genxml. Louis-Francis Ratté-Boulianne (1): genxml: Fill out Gen4, Gen45 and Gen5 XML Rafael Antognolli (33): genxml: Rename clip enable property. genxml: Update xml for 3DSTATE_SF

Re: [Mesa-dev] [PATCH v02 26/37] i965: Port gen6+ 3DSTATE_WM to genxml.

On Wed, Apr 26, 2017 at 11:15:45PM -0700, Kenneth Graunke wrote: > On Monday, April 24, 2017 3:19:21 PM PDT Rafael Antognolli wrote: > [snip] > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c > > b/src/mesa/drivers/dri/i965/genX_state_upload.c > > index

Re: [Mesa-dev] [PATCH] i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

Makes sense to me. Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> On Wed, Apr 26, 2017 at 11:14:47PM -0700, Kenneth Graunke wrote: > Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not. We ought to > be consistent - the answer depends on the API, not the hardwar

[Mesa-dev] [PATCH v3 06/37] genxml: Add alias for MOCS.

Use an alias, so we can set the same value as the #define's. v3: - Call it "SO Buffer MOCS" to follow the most common naming scheme. - Add alias for gen7 and gen75 too (Ken). Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen7.xml

Re: [Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

On Mon, Apr 24, 2017 at 03:59:07PM -0700, Kenneth Graunke wrote: > On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote: > > Use an alias, so we can set the same value as the #define's. > > > > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com

[Mesa-dev] [PATCH v02 00/37] Updated series to convert part of the state emitting code to genxml.

er Mode" fields consistent. i965: Add genxml related plumbing in a new genX_state_upload.c file. i965: Get real per-gen atom lists i965: Port Gen6+ DEPTH_STENCIL state to genxml. Louis-Francis Ratté-Boulianne (1): genxml: Fill out Gen4, Gen45 and Gen5 XML Rafael Antognolli (32): genxml: Fi

[Mesa-dev] [PATCH v02 18/37] i965: Port Gen6+ DEPTH_STENCIL state to genxml.

From: Kenneth Graunke <kenn...@whitecape.org> This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE (and the relevant pointer packets) on Gen6-7.5 from a single function. Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Rafael Antognolli <

[Mesa-dev] [PATCH v02 20/37] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +--- src/mesa/drive

[Mesa-dev] [PATCH v02 02/37] genxml: Fix gen4-5 xml to make it compile correctly.

Set the type of some fields, instead of prefix. Also fix the SAMPLER_BORDER_COLOR_STATE fields of gen5.xml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen4.xml | 13 +- src/intel/genxml/gen45.xml | 12 - src/intel/genxml/gen5.xml

[Mesa-dev] [PATCH v02 13/37] i965: Split out enum from brw_eu_defines.h

-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/Makefile.sources | 1 +- src/intel/compiler/brw_defines_common.h | 46 ++- src/intel/compiler/brw_eu_defines.h | 22 + 3 files changed, 48 insertions(+), 21 deletions(-)

[Mesa-dev] [PATCH v02 17/37] genxml: Add rules to build gen4, gen45 and ge5.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.am | 12 src/mesa/drivers/dri/i965/Makefile.sources | 9 + src/mesa/drivers/dri/i965/brw_state.h | 1 + 3 files changed, 22 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH v02 27/37] i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.

Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses pack structs from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 10 +- src/mesa/drive

[Mesa-dev] [PATCH v02 21/37] i965: Port gen6+ 3DSTATE_SF to genxml.

Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 3 +- src/mesa/drivers/dri/i965/brw_util.h | 25 +- src/mesa/drivers/dr

[Mesa-dev] [PATCH v02 34/37] i965: Port gen4+ emit vertices code to genxml.

) - Use macros for MOCS values. - Do not use #ifndef NDEBUG on code that is actually used (Ken) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h |6 +- src/mesa/drivers/dri/i965/brw_draw.h |2 +- sr

[Mesa-dev] [PATCH v02 19/37] i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen6_clip_state.c | 139 +-- sr

[Mesa-dev] [PATCH v02 36/37] i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen6_cc.c | 90 + src/mesa/drivers/dri/i965/genX_state_up

[Mesa-dev] [PATCH v02 03/37] genxml: Rename clip enable property.

There are two variants: - Clip Enable - CLIP Enable (on gen6) Rename everything to Clip Enable. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen4.xml | 2 +- src/intel/genxml/gen45.xml

[Mesa-dev] [PATCH v02 28/37] i965: Port gen6+ 3DSTATE_VS to genxml.

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use render_bo helper to setup brw_address (Kristian) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 2 +- src/mesa/drive

[Mesa-dev] [PATCH v02 14/37] anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

In a previous patch some enums were split out from brw_eu_defines.h, so they could be used by genxml based code. anv can also benefit from this. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/vulkan/genX_pipeline.c | 4 +++- 1 file changed, 3 insertions

[Mesa-dev] [PATCH v02 15/37] i965: Add genxml related plumbing in a new genX_state_upload.c file.

From: Kenneth Graunke Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources| 15 ++- src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++- 2 files changed, 119 insertions(+), 5 deletions(-) create

[Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

Use an alias, so we can set the same value as the #define's. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen8.xml | 1 + src/intel/genxml/gen9.xml | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/ge

[Mesa-dev] [PATCH v02 25/37] i965: Port gen7+ 3DSTATE_PS to genxml.

Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use render_bo helper to setup brw_address (Kristian) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drive

[Mesa-dev] [PATCH v02 05/37] genxml: Add missing field values to 3DSTATE_SBE.

Fill out "Attribute Active Component Format" possible values. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen9.xml | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.x

[Mesa-dev] [PATCH v02 22/37] i965: Port Gen7+ 3DSTATE_SBE state to genxml.

Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use ACTIVE_COMPONENT_XYZW from gen9.xml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 2 +- src/mesa/drivers/dr

[Mesa-dev] [PATCH v02 26/37] i965: Port gen6+ 3DSTATE_WM to genxml.

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Use render_bo helper to setup brw_address (Kristian) - Remove TODO and use BRW_PSCDEPTH_OFF. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH v02 11/37] genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

Name the options to "Pixel Location": - PIXLOC_CENTER -> CENTER - PIXLOC_UL_CORNER -> UL_CORNER Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/blorp/blorp_genX_exec.h | 4 +--- src/intel/genxml/gen6.xml | 4 ++-- src/intel/genxm

[Mesa-dev] [PATCH v02 30/37] i965: Port gen6+ blend state code to genxml.

Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 3 +- src/mesa/drivers/dri/i965/gen

[Mesa-dev] [PATCH v02 32/37] i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.

Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the scissor states using GENX(SCISSOR_RECT_pack), generated from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dr

[Mesa-dev] [PATCH v02 04/37] genxml: Update xml for 3DSTATE_SF.

- Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <r

[Mesa-dev] [PATCH v02 29/37] i965: Port gen6+ state emitting code to genxml.

Ported in this patch: - 3DSTATE_DS - 3DSTATE_GS - 3DSTATE_HS - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources | 6 +- src/mesa/drivers/dri/i965/brw_state.h

[Mesa-dev] [PATCH v02 33/37] i965: Port push constant code to genxml.

The following states are ported on this patch: - gen6_gs_push_constants - gen6_vs_push_constants - gen6_wm_push_constants - gen7_tes_push_constants v2: - Use helper to setup brw_address (Kristian) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/d

[Mesa-dev] [PATCH v02 16/37] i965: Get real per-gen atom lists

From: Kenneth Graunke Make atoms initalization compile conditionally based on the target platform. --- src/mesa/drivers/dri/i965/brw_state.h | 12 +- src/mesa/drivers/dri/i965/brw_state_upload.c | 385 +---

[Mesa-dev] [PATCH v02 08/37] genxml: 3DSTATE_VS rename Function Enable to Enable.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/blorp/blorp_genX_exec.h | 2 +- src/intel/genxml/gen6.xml | 2 +- src/intel/genxml/gen7.xml | 2 +- src/intel/genxml/gen75.xml| 2 +- src/intel/genxml/gen8.xml | 2 +- src/intel/

[Mesa-dev] [PATCH v02 12/37] genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>

[Mesa-dev] [PATCH v02 10/37] genxml: Rename "Function Enable" to "Enable".

Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen6.xml| 2 +- src/intel/genxml/gen7.xml| 6 +++--- src/intel/genxml/gen

[Mesa-dev] [PATCH v02 09/37] genxml: Clip guardbands are float, not int.

This makes genxml create the right struct types, and generate the right batch commands. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen6.xml | 8 1 file changed, 4 insertions(+),

[Mesa-dev] [PATCH v02 31/37] i965: Port gen7+ 3DSTATE_TE to genxml.

Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen7_te_state.c

[Mesa-dev] [PATCH v02 35/37] i965: Port gen6+ multisample state emitting code to genxml.

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h| 9 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/gen6_multisample_state.c

[Mesa-dev] [PATCH v02 07/37] genxml: Make "Reorder Mode" fields consistent.

From: Kenneth Graunke Both GS and SOL have these fields. Some were ReorderEnable = true, some were ReorderMode = REORDER_TRAILING, and some were just TRAILING. Signed-off-by: Kenneth Graunke --- src/intel/genxml/gen6.xml| 5 -

[Mesa-dev] [PATCH v02 23/37] i965: Remove calculate_attr_overrides.

This function now lives inside genX_state_upload.c. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources | 1 +- src/mesa/drivers/dri/i965/brw_state.h | 8 +- src/mesa/drivers/dri/i965/gen6_sf_state.c

[Mesa-dev] [PATCH v02 24/37] i965: Port gen7+ 3DSTATE_SOL to genxml.

Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack structs from genxml. v2: - Add helpers to assign struct brw_address (Kristian) Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/Makefile.sources| 1 +- src/mesa/drive

Re: [Mesa-dev] [PATCH 20/35] genxml: Make "Reorder Mode" fields consistent.

On Mon, Apr 24, 2017 at 03:03:56PM -0700, Kenneth Graunke wrote: > On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote: > > From: Kenneth Graunke <kenn...@whitecape.org> > > > > Both GS and SOL have these fields. Some were ReorderEnable = true

Re: [Mesa-dev] [PATCH 22/35] i965: Port gen6+ 3DSTATE_VS to genxml.

On Thu, Apr 20, 2017 at 09:55:56AM -0700, Kristian H. Kristensen wrote: > Rafael Antognolli <rafael.antogno...@intel.com> writes: > > > Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack > > structs from genxml. > > > > Signed-off-b

[Mesa-dev] [PATCH 32/35] i965: Port gen6+ multisample state emitting code to genxml.

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h| 9 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/gen6_multisample_state.c

[Mesa-dev] [PATCH 35/35] i965: Port gen6+ state emitting code to genxml.

On this patch, we port: - brw_polygon_stipple - brw_polygon_stipple_offset - brw_line_stipple - brw_drawing_rect The original code is still left behind because it is being used by gen4-5. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH 21/35] genxml: 3DSTATE_VS rename Function Enable to Enable.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/blorp/blorp_genX_exec.h | 2 +- src/intel/genxml/gen6.xml | 2 +- src/intel/genxml/gen7.xml | 2 +- src/intel/genxml/gen75.xml| 2 +- src/intel/genxml/gen8.xml | 2 +- src/intel/

[Mesa-dev] [PATCH 10/35] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from genxml. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_state.h | 1 +- src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +--- src/mesa/drive

[Mesa-dev] [PATCH 24/35] genxml: Rename "Function Enable" to "Enable".

Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/genxml/gen6.xml| 2 +- src/intel/genxml/gen7.xml| 6 +++--- src/intel/genxml/gen

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