On 4/17/23 13:41, Samuel Iglesias Gonsálvez wrote:
Hello!
Registration & Call for Proposals are now open for XDC 2023, which will
take place on October 17-19, 2023.
Forgot to mention, it will be in A Coruña, Spain :)
https://xdc2023.x.org
As usual, the conference is free of ch
Hello!
Registration & Call for Proposals are now open for XDC 2023, which will
take place on October 17-19, 2023.
https://xdc2023.x.org
As usual, the conference is free of charge and open to the general
public. If you plan on attending, please make sure to register as early
as possible!
In
Hi,
First of all, thanks organizers for such a great conference. It was
smooth and, although there were some issues as it is usual in any
conference, they were fixed promptly :-)
I would like also to thank all of you for attending and participating
either via submitting talks, watching them or
Deadline is at the end of this month. Do not forget to submit your XDC
2022 hosting proposal!
Sam
On Thu, 2021-07-29 at 21:01 +0200, Samuel Iglesias Gonsálvez wrote:
> Remember before enjoying your holiday that the deadline for XDC 2022
> proposals is *September 1st, 2021* :-)
>
&g
Remember before enjoying your holiday that the deadline for XDC 2022
proposals is *September 1st, 2021* :-)
Feel free to submit your proposal before, so we can give you early
feedback on it!
Sam
On Thu, 2021-07-01 at 18:14 +0200, Samuel Iglesias Gonsálvez wrote:
> This is a remin
On Tue, 2021-07-06 at 09:38 +0200, Samuel Iglesias Gonsálvez wrote:
> Hi!
>
> We have decided to extend the Call for Proposals until September 1st
> or
> until we will all the available talk slots, whichever occurs first.
>
> Remember that talks will get accepted by order
On Sat, 2021-06-26 at 08:35 +0200, Samuel Iglesias Gonsálvez wrote:
> One week!
>
> Don't forget to submit your proposals!
>
> Sam
>
> On Tue, 2021-06-08 at 12:38 +0200, Samuel Iglesias Gonsálvez wrote:
> > Kind reminder. Deadline is Sunday, 4 July 2021 :-)
> >
This is a reminder that the call for proposals for hosting XDC 2022
period finishes in two months.
Be sure to prepare your submission before you leave on holiday!
Sam
On Thu, 2021-05-20 at 12:15 +0200, Samuel Iglesias Gonsálvez wrote:
> Hello everyone!
>
> The X.org board is s
One week!
Don't forget to submit your proposals!
Sam
On Tue, 2021-06-08 at 12:38 +0200, Samuel Iglesias Gonsálvez wrote:
> Kind reminder. Deadline is Sunday, 4 July 2021 :-)
>
> Sam
>
> On Thu, 2021-05-20 at 10:01 +, Szwichtenberg, Radoslaw wrote:
> > Hello!
> >
Kind reminder. Deadline is Sunday, 4 July 2021 :-)
Sam
On Thu, 2021-05-20 at 10:01 +, Szwichtenberg, Radoslaw wrote:
> Hello!
>
> Registration & Call for Proposals are now open for XDC 2021, which
> will
> take place on September 15-17, 2021. This year we will repeat as
> virtual event.
>
Hello everyone!
The X.org board is soliciting proposals to host XDC in 2022. Since
XDC 2021 is being held in Europe this year (although virtually), we've
decided to host in North America. However, the board is open to other
locations, especially if there's an interesting co-location with
another
For turnip:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10205
Sam
On Fri, 2021-04-09 at 09:39 -0700, Dylan Baker wrote:
> Hi all,
>
> I've been a little behind on release work recently, and I'm tryinng to
> cleanup the backlog of patches against the 21.0 branch that haven't
> been
Deadline is November 1st, just in a few weeks!
Don't forget to submit your XDC 2021 proposal to bo...@foundation.x.org
.
Sam
On Thu, 2020-09-03 at 12:16 -0400, Lyude Paul wrote:
> (Including a bunch more emails in the To: that got missed the first
> time)
>
> Hello everyone!
>
> The X.org
Hi all,
Huge thanks again to the entire team from Intel, for their great work
organizing XDC 2020, our first virtual conference!
As usual we're looking for feedback on both XDC itself, and the CFP
process and program selection. Both about what was great and should be
kept for next year's
On 7/3/20 4:41 PM, Samuel Iglesias Gonsálvez wrote:
> Hi,
>
> In the last meeting, X.Org Foundation board has decided that XDC 2020
> will be a virtual conference, given the uncertain COVID-19 situation in
> Europe by September, including the possibility of a second wave,
> ou
On 7/3/20 4:41 PM, Samuel Iglesias Gonsálvez wrote:
> Hi,
>
> In the last meeting, X.Org Foundation board has decided that XDC 2020
> will be a virtual conference, given the uncertain COVID-19 situation in
> Europe by September, including the possibility of a second wave,
> ou
Hi,
In the last meeting, X.Org Foundation board has decided that XDC 2020
will be a virtual conference, given the uncertain COVID-19 situation in
Europe by September, including the possibility of a second wave,
outbreaks and travel restrictions, either in Poland or in other
countries.
XDC 2020
Hi,
This is a kindly reminder that the CFP deadline is in less than two
weeks :)
On Fri, 2020-05-15 at 14:15 +, Szwichtenberg, Radoslaw wrote:
> Hello!
>
> Registration & Call for Proposals are now open for XDC 2020, which
> will
> take place at the Gdańsk University of Technology in
Hi all,
Once more huge thanks to the entire team from Collabora,
for their great work organizing XDC 2019!
As usual we're looking for feedback on both XDC itself, and the CFP
process and program selection. Both about what was great and should be
kept for next year's edition, and where there's
On Tue, 2019-10-08 at 17:27 +0200, Samuel Iglesias Gonsálvez wrote:
> Hi all,
>
> Once more huge thanks to the entire team from Collabora,
> for their great work organizing XDC 2019!
>
> As usual we're looking for feedback on both XDC itself, and the CFP
> process and pr
not have a descriptorType of
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT".
There is no explicit mention in vkCmdPushDescriptorSetKHR() to forbid
this case but it is implied in the creation of the descriptor set
layout as aforementioned.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/amd/vulkan/radv_cmd_buffer.c | 8
On 6/11/19 12:05 PM, Józef Kucia wrote:
> On Tue, Jun 11, 2019 at 11:57 AM Samuel Iglesias Gonsálvez
> wrote:
>> According to the Vulkan spec, uniform blocks are not allowed to be
>> updated through vkCmdPushDescriptorSetKHR().
>>
>> There are these spec quotes from
_INLINE_UNIFORM_BLOCK_EXT".
There is no explicit mention in vkCmdPushDescriptorSetKHR() to forbid
this case but it is implied in the creation of the descriptor set
layout as aforementioned.
Signed-off-by: Samuel Iglesias Gonsálvez
---
My only doubt is I did well in the case of
radv_meta_push
_INLINE_UNIFORM_BLOCK_EXT".
There is no explicit mention in vkCmdPushDescriptorSetKHR() to forbid
this case but it is implied in the creation of the descriptor set
layout as aforementioned.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_cmd_buffer.c | 13 -
1 file
On Thu, 2019-03-28 at 16:21 +0100, Samuel Pitoiset wrote:
> On 3/25/19 8:16 AM, Samuel Iglesias Gonsálvez wrote:
> > On Fri, 2019-03-22 at 17:21 +0100, Samuel Pitoiset wrote:
> > > Does this fix anything known?
> > >
> > I am writing CTS tests for VK_EXT_host_quer
f,
> undef, undef, alpha) to help with linking but then keep the one
> output var so it we still get the write in the shader.
>
OK, thanks for the suggestion!
Sam
>
> On Mon, Mar 4, 2019 at 4:56 AM Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
> > Stil
d-by: Samuel Pitoiset
>
OK, thanks! It seems I did a wrong squash of patches on patch 1. I will
fix it and push both patches to master.
Sam
> On 3/22/19 1:03 PM, Samuel Iglesias Gonsálvez wrote:
> > If VK_QUERY_RESULT_WITH_AVAILABILY_BIT is set and
> > VK_QUERY_RESULT_WAIT_BIT and V
s set."
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/amd/vulkan/radv_query.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 8578680f09d..63a2ab773a8 100644
--- a/src/amd/vulkan/radv_query.c
pData for queries
that are in the unavailable state at the time of the call, and
vkGetQueryPoolResults returns VK_NOT_READY. However, availability state
is still written to pData for those queries
if VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/
Reviewed-by: Samuel Iglesias Gonsálvez
Sam
On Tue, 2019-03-12 at 15:24 -0500, Jason Ekstrand wrote:
> We've been fairly inconsistent about this so we should really choose
> whether we're going to use VK_TRUE/FALSE or the C boolean
> values. The
> Vulkan #defines are set to 1 and 0
Still unreviewed.
Sam
On Thu, 2019-02-21 at 12:08 +0100, Samuel Iglesias Gonsálvez wrote:
> CL#3532 added a test for alpha to coverage without a color
> attachment.
> First the test draws a primitive with alpha 0 and a subpass with only
> a depth buffer. No writes to a depth buffer
Reviewed-by: Samuel Iglesias Gonsálvez
On Wed, 2019-02-27 at 00:15 -0600, Jason Ekstrand wrote:
> No idea how this fell through the cracks besides the fact that the
> sampler bound at 0 almost always works and the CTS isn't amazing. In
> any case, this appears to have been broken f
It is still unreviewed.
Sam
On 2/8/19 8:17 AM, Samuel Iglesias Gonsálvez wrote:
> First three versions of this branch were sent for review to the mailing
> list. In order to avoid flooding the list with more emails, I create
> this MR to continue the review process there.
>
Lionel, are you going to push it with this quote? I can add it
otherwise.
Sam
On Thu, 2019-02-21 at 13:41 +, Lionel Landwerlin wrote:
> On 21/02/2019 13:30, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-02-21 12:57:09)
> > > I did not find the PRM bit that says it must be 64b
};
As g120 is not initialized, we see random writes to the depth buffer
due to the alphaToCoverage enablement. This commit fixes that by
keeping the output and creating a null render target for it.
Fixes tests:
dEQP-VK.pipeline.multisample.alpha_to_coverage_no_color_attachment.*
Signed-off-by: Samuel Iglesi
The cacheline size was a requirement for using the BLT engine, which
we don't use anymore except for a few things on old HW, so we drop it.
Fixes CTS's CL#3500 test:
dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/isl/isl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5c34efb9a13..7fb469687fa 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1519,6 +1519,9 @@ isl_surf_init_s(const
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_image.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 3999c7399d0..f4a65044a3b 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel
-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/isl/isl.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index eaaa28014a3..7f1f2339931
-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/isl/isl.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index eaaa28014a3..7f1f2339931
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_image.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 3999c7399d0..f4a65044a3b 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel
On 2/6/19 12:47 PM, Connor Abbott wrote:
>
>
> On Wed, Feb 6, 2019 at 11:46 AM Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
> According to Vulkan spec, the new execution modes affect only
> correctly rounded SPIR-V instructions, whic
First three versions of this branch were sent for review to the mailing
list. In order to avoid flooding the list with more emails, I create
this MR to continue the review process there.
Reminder: this patch series relies on VK_KHR_shader_float16_int8 patch
series which is currently under review.
On 2/6/19 12:47 PM, Connor Abbott wrote:
>
>
> On Wed, Feb 6, 2019 at 11:46 AM Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
> According to Vulkan spec, the new execution modes affect only
> correctly rounded SPIR-V instructions, whic
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_device.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6b272ecf558..3d5ffa641a0 100644
--- a/src/intel/vulkan/anv_device.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index defe263b2fb..fb8e9d593a3 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index adc8bb4ddf5..1ee0e4d3e4e 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
v2:
- Fix bug in the rounding mode change (Alejandro)
v3:
- Fix rounding modes.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 13 -
1 file changed, 12
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 809c7971c94..dfa6176340a 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel
ctive of the rounding mode."
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index ac5067f7ecc..ef1ed9b7f0a 100644
--- a/src/inte
We need this function to emit code that setups the control register later with
the defined execution mode for the shader.
v2:
- Fix bug in setting the default mode mask in brw_rnd_mode_from_nir()
- Fix support for rounding modes in brw_rnd_mode_from_nir()
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 71e5a96e0a3..aab06a525bc 100644
--- a/src/intel
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index ef1ed9b7f0a..9dacff9785b 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src
The denorm mode is set in the control register, no need to do something else.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4 ---
src/intel/compiler/brw_eu_emit.c| 36 -
src/intel/compiler/brw_fs_generator.cpp | 13 +++--
3 files changed, 11 insertions(+), 42 deletions(-)
diff --git a/src
v2:
- Fix bug in defining BRW_CR0_FP_MODE_MASK.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 10 ++
src/intel/compiler/brw_eu_emit.c| 26 +
src/intel/compiler
---
src/intel/compiler/brw_fs_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index aab06a525bc..86ab8c48135 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@
-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_nir.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 1d62f2adde8..e797794bfb8 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes fadd,
fsub and fmul.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 17 +
1 file changed, 17 insertions(+)
diff --git a/src
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_double_ops.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_lower_double_ops.c
b/src/compiler/nir/nir_lower_double_ops.c
index 4d4cdf635ea..525f2d19dc7 100644
--- a/src
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index b0092bcb2ad..b62641f3db5 100644
--- a/src/compiler
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 8128ed346af..b6036cf876e 100644
--- a/src/compiler/spirv/vtn_glsl450
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/Makefile.sources | 2 +
src/util/double.c | 197 ++
src/util/double.h | 46 +
src/util/meson.build | 2 +
4 files changed, 247 insertions(+)
create mode 100644 src/util
Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 20 ++--
src/compiler/nir/nir_opcodes_c.py | 4 ++--
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 21f6ee6f742..f8997444c28 100644
Until now, it was using the floating point version of fmin/fmax,
instead of the double version.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir
serve execution mode."
v2:
- Add nir_op_unpack_half_2x16_flush_to_zero opcode (Connor)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_constant_expressions.py | 13 +
src/compiler/nir/nir_lower_alu_to_scalar.c | 11 +--
src/compiler/nir/nir_
This way, we can implement its support later if SPIR-V supports it.
Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only
applies to f2f16 conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 4
1 file changed, 4 insertions(+)
diff
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_algebraic.py | 73 +++
1 file changed, 73 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 71c626e1b3f..3800db1da20 100644
--- a/src
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index b62641f3db5..e9b1b0b8fec 100644
--- a/src/compiler
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes Fract.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_constant_expressions.py | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_constant_expressions.py
b/src/compiler/nir/nir_constant_expressions.py
index e79590f8359..0b3da1b21ac
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which is the case for ldexp.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/compiler/nir
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index a6d2c5fdd07..b0092bcb2ad 100644
--- a/src/compiler/spirv
If x < 0 -> atan2(x, x) = -3*pi/4.
If x > 0 -> atan2(x, x) = pi/4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_gls
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index e9b1b0b8fec..8128ed346af 100644
--- a/src/compiler/spirv
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_alu.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 848fbbdb07c..881a9bab314 100644
--- a/src/compiler/spirv
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_alu.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 881a9bab314..06320adf152 100644
--- a/src/compiler/spirv
v2:
- Fixed bug in rounding modes for conversion ops, it was not considering
the rounding mode of the destination data type.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 16
src/compiler/spirv/vtn_alu.c | 14 +-
2 files changed, 29
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_algebraic.py | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebraic.py
index fe9d1051e67..9aa1b1928b8 100644
--- a/src/compiler/nir
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/half_float.c | 74 +++
src/util/half_float.h | 7
2 files changed, 81 insertions(+)
diff --git a/src/util/half_float.c b/src/util/half_float.c
index 63aec5c5c14..5fdcb20045b 100644
--- a/src/util
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes FaceForward.
FaceForward is lowered into fdot* instructions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_builder.h | 32 +++
src
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h| 3 ++
src/compiler/nir/nir_opcodes.py | 90 ---
src/compiler/nir/nir_opcodes_c.py | 4 +-
3 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src
---
src/compiler/nir/nir_opt_algebraic.py | 70 +++
1 file changed, 70 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 3800db1da20..3384c9c2e67 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++
v2:
- Add support for rounding modes for each floating point bit size.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_enums.h | 20 +++
src/compiler/shader_info.h| 3 +++
src/compiler/spirv/spirv_to_nir.c | 41 +++
3 files
xcept when the opcode is OpQuantizeToF16."
v3:
- Fix bit size (Connor)
- Fix execution mode on nir_loop_analize (Connor)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_constant_expressions.h | 3 +-
src/compiler/nir/nir_constant_expressions.py | 71 ++--
sr
We were returning 3*pi/4 when we should return 0.0 according to IEEE 754.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 66 ++
1 file changed, 66 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 740c64d2a94..a84c46507e2 100644
--- a/src/compiler/nir/nir.h
+++ b/src
feedback: move some code from nir_constant_expressions.py to
nir_opcodes.py, fix bug in nir_constant_expressions.py related to bit_size,
fix bug in nir_loop_analyze.c related to float controls mode usage.
- Fixed several bugs found while working on this v3.
Thanks,
Sam
Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index e9d887a8f4b..45fb00a9cfe 100644
--- a/src/compiler
On 30/01/2019 16:18, Connor Abbott wrote:
>
>
> On Tue, Dec 18, 2018 at 11:35 AM Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
> v2:
> - Refactor conditions and shared function (Connor)
> - Move code to nir_eval_const_opcode(
for your feedback.
Sam
> On Tue, Dec 18, 2018 at 11:35 AM Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
> Signed-off-by: Samuel Iglesias Gonsálvez <mailto:sigles...@igalia.com>>
> ---
> src/compiler/nir/nir_constant_expressio
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Signed-off-by: Samuel Iglesias Gonsálvez
---
Lionel, I have doubts if this is only for gen9 or it should be gen9+.
Can you confirm on gen10 if the sRGB bug is happening there and if this
fixes it? (You would need to adapt the GEN_GEN
The denorm mode is set in the control register, no need to do something else.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_device.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 67ea86c4b66..1b57e7b56f5 100644
--- a/src/intel/vulkan/anv_device.c
We need this function to emit code that setups the control register later with
the defined execution mode for the shader.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.h | 1 +
src/intel/compiler/brw_fs_visitor.cpp | 52 +++
2 files
This way, we can implement its support later if SPIR-V supports it.
Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only
applies to f2f16 conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 4
1 file changed, 4 insertions(+)
diff
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index c303ba321c3..2781b8f0ee0 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 10 ++
src/intel/compiler/brw_eu_emit.c| 26 +
src/intel/compiler/brw_fs_generator.cpp | 8 +++-
src/intel
-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_nir.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 3b4d25213f5..2debce72db2 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
v2:
- Fix bug in the rounding mode change (Alejandro)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
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