On Fri, 2017-04-21 at 10:23 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Thu, 2017-04-20 at 10:26 -0700, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > It was setting XYWZ swizzle to al
Series is,
Reviewed-by: Samuel Iglesias Gonsálvez
Sam
On Fri, 2017-04-21 at 11:53 +0200, Samuel Pitoiset wrote:
> The glsl_type helpers interface is quite nice and this (trivial)
> series tends to make use of the is_XXX() functions everywhere it's
> possible.
>
> Ple
On Thu, 2017-04-20 at 10:26 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > It was setting XYWZ swizzle to all uniforms, no matter if they were
> > a vector or not.
> >
> > Signed-off-by: Samuel Iglesias Gonsálvez
> > Cc: curroje...@
Thu, 2017-04-20 at 14:02 +0200, Samuel Iglesias Gonsálvez wrote:
> > It helps to find the envvar you are looking for.
> >
> > Signed-off-by: Samuel Iglesias Gonsálvez
> > ---
> > docs/envvars.html | 58 +++
> > ---
It helps to find the envvar you are looking for.
Signed-off-by: Samuel Iglesias Gonsálvez
---
docs/envvars.html | 58 +++
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/docs/envvars.html b/docs/envvars.html
index a064f569c8b
-by: Samuel Iglesias Gonsálvez
Cc: curroje...@riseup.net
---
src/intel/compiler/brw_vec4.cpp | 86 +++--
1 file changed, 65 insertions(+), 21 deletions(-)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 0b92ba704e5
It was setting XYWZ swizzle to all uniforms, no matter if they were
a vector or not.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: curroje...@riseup.net
---
src/intel/compiler/brw_vec4_nir.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_vec4_nir.cpp
b/src/intel
Series is:
Reviewed-by: Samuel Iglesias Gonsálvez
On Thu, 2017-04-06 at 13:37 -0700, Jordan Justen wrote:
> Since '---' can exist within an ascii85 encoded string, we should
> avoid these strings when looking for header lines in the error state
> file.
>
> One of th
Reviewed-by: Samuel Iglesias Gonsálvez
On Fri, 2017-04-07 at 07:55 +1000, Timothy Arceri wrote:
> We don't need to call _mesa_reference_renderbuffer() for the first
> assignment as refCount starts at 1. For swrast we work around the
> fact we will indirectly call _mesa_referenc
On Thu, 2017-04-06 at 11:59 -0700, Jason Ekstrand wrote:
> On Thu, Apr 6, 2017 at 1:58 AM, Samuel Iglesias Gonsálvez igalia.com> wrote:
> > On Broadwell we still need to do a resolve between the subpass
> > that writes and the subpass that reads when there is a
> > se
-VK.renderpass.formats.*.input.clear.store.self_dep*
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_blorp.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 72a468a744a..daf13d360c4 100644
--- a
On Tue, Apr 04, 2017 at 06:04:28PM +0200, Andreas Boll wrote:
> Please update the release notes in the last patch.
OK, thanks!
Sam
>
> Thanks,
> Andreas
>
> 2017-03-20 10:16 GMT+01:00 Samuel Iglesias Gonsálvez :
> > Hi,
> >
> > This series implements in
As I am sending some patch updates, to avoid any confusion I want to
clarify than the patches waiting for review are: 9, 14, 16-24.
Sam
On Mon, Mar 20, 2017 at 10:16:57AM +0100, Samuel Iglesias Gonsálvez wrote:
> Hi,
>
> This series implements initial support for Ivybridge FP64
On Mon, Mar 27, 2017 at 06:30:19AM +0200, Samuel Iglesias Gonsálvez wrote:
> On Fri, Mar 24, 2017 at 12:39:38PM -0700, Francisco Jerez wrote:
> > Matt Turner writes:
> >
> > > On Fri, Mar 24, 2017 at 12:06 AM, Francisco Jerez
> > > wrote:
> &g
Use static inline function instead of fs_inst's method (Curro).
- Define the result as a constant (Curro).
- Fix indentation (Matt).
- Add braces to nested control flow (Matt).
v3 (Curro):
- Add get_exec_type() and other auxiliary functions and use them to
calculate its size.
Signed-off-by:
- Add comment into the code (Curro).
- Manage ARF registers like the others (Curro)
v4:
- Add get_exec_type() function and use it to calculate the execution
size.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_ir_vec4.h | 29 +
src/intel/com
On Fri, Mar 24, 2017 at 01:42:23PM -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > Generalize it to lower any unsupported narrower conversion.
> >
> > v2 (Curro):
> > - Add supports_type_conversion()
> > - Reuse existing intruction ins
On Fri, Mar 24, 2017 at 12:39:38PM -0700, Francisco Jerez wrote:
> Matt Turner writes:
>
> > On Fri, Mar 24, 2017 at 12:06 AM, Francisco Jerez
> > wrote:
> >> Samuel Iglesias Gonsálvez writes:
> >>
> >>> On Thu, 2017-03-23 at 13:50 -0700, Matt T
Iglesias Gonsálvez
---
This patch replaces the respective v3 one.
src/intel/compiler/brw_fs.cpp | 11 +--
src/intel/compiler/brw_fs_lower_d2x.cpp | 117 +++-
2 files changed, 91 insertions(+), 37 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src
This way we can set the destination type as double to all these new opcodes,
avoiding any optimizer's confusion that was happening before.
Signed-off-by: Samuel Iglesias Gonsálvez
---
This patch is going to be placed just after patch 17.
Please discard patch 19.
src/intel/com
have
something soon. If you prefer to land this now, please add my R-b but
you probably want to discuss it with Curro before:
Reviewed-by: Samuel Iglesias Gonsálvez
Sam
> ---
> src/intel/compiler/brw_fs_sel_peephole.cpp | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src
On Thu, 2017-03-23 at 12:14 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Wed, 2017-03-22 at 15:55 -0700, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > Now the VEC4_OPCODE_FROM_DOUBLE&
On Thu, 2017-03-23 at 12:01 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Wed, 2017-03-22 at 15:47 -0700, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > Generalize it to lower any unsupporte
On Thu, 2017-03-23 at 11:09 -0700, Nanley Chery wrote:
> On Thu, Mar 23, 2017 at 12:25:28PM +0100, Samuel Iglesias Gonsálvez
> wrote:
> > A resolve is not needed on Skylake in this case. We were forcing
> > a resolve because we set the input_aux_usage to ISL_AUX_USAGE_NONE.
>
A resolve is not needed on Skylake in this case. We were forcing
a resolve because we set the input_aux_usage to ISL_AUX_USAGE_NONE.
Signed-off-by: Samuel Iglesias Gonsálvez
---
This doesn't fix the problem with BDW but I found it while reviewing
the code.
src/intel/vulkan/genX_cmd_buf
On Thu, 2017-03-23 at 08:59 +0100, Samuel Iglesias Gonsálvez wrote:
> On Wed, 2017-03-22 at 15:47 -0700, Francisco Jerez wrote:
> > Samuel Iglesias Gonsálvez writes:
> >
> > > Generalize it to lower any unsupported narrower conversion.
> > &g
On Wed, 2017-03-22 at 15:55 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > Now the VEC4_OPCODE_FROM_DOUBLE's destination data is written with
> > stride 2. We need to take into account this when doing the split
> > so we don't ov
his patch get your R-b then?
Sam
> Samuel Iglesias Gonsálvez writes:
>
> > Signed-off-by: Samuel Iglesias Gonsálvez
> > ---
> > src/intel/Makefile.sources
> > | 2 +-
> > src/intel/compiler/brw_fs.cpp
On Wed, 2017-03-22 at 15:47 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > Generalize it to lower any unsupported narrower conversion.
> >
> > v2 (Curro):
> > - Add supports_type_conversion()
> > - Reuse existing intruction instead of
On Tue, 2017-03-21 at 16:34 +0100, Samuel Iglesias Gonsálvez wrote:
>
> On 21/03/17 16:14, Jason Ekstrand wrote:
> > On Tue, Mar 21, 2017 at 7:23 AM, Samuel Iglesias Gonsálvez
> > mailto:sigles...@igalia.com>> wrote:
> >
> > Input attachments are
On 21/03/17 16:14, Jason Ekstrand wrote:
> On Tue, Mar 21, 2017 at 7:23 AM, Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
> Input attachments are clear-color aware on Sky Lake, so we
> can frequently sample from them with no resolves at
.*.input.clear.store.self_dep*
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_blorp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 1f4fec5f35b..2fa56f49d18 100644
--- a/src/intel/vulkan/anv_blorp.c
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
src/mesa/drivers/dri/i965/intel_screen.c | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b
Signed-off-by: Samuel Iglesias Gonsálvez
Acked-by: Francisco Jerez
---
docs/features.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index b4e54a7d1a5..d34bef157c8 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -107,7
From: "Juan A. Suarez Romero"
In the generator we must generate slightly different code for
Ivybridge/Baytrail, because of the way the stride works in
this hardware.
v2:
- Use stride and don't need to fix dst (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src
From: "Juan A. Suarez Romero"
Keep the original type when dealing with null registers. Especially
because we do no want to introduce an implicit conversion between
types that could affect the conditional flags.
This affects especially when the original type is DF, and we are working
on Ivybridge
different instructions:
VEC4_OPCODE_FROM_DOUBLE just do the conversion and
VEC4_OPCODE_PICK_LOW_32BIT will gather the data.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4_generator.cpp | 8
src/intel/compiler/brw_vec4_nir.cpp | 1 +
2 files changed, 1 insertion
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index
in account this offset < 32 in liveness analysis too (Curro)
v3:
- Change formula in var_from_reg() (Curro)
- Remove useless changes (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4_live_variables.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
dif
>.xyxyDF-g9<2>DF{ align16 2N };
ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)
Reviewed-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jer
ce registers must be the same
The intention was to emit mov(4)s for the instructions that have ERROR
annotations.
See tests/spec/arb_gpu_shader_fp64/execution/vs-isinf-dvec.shader_test
for example.
v2 (Samuel):
- Instead of setting the exec size to a fixed value, don't double it
(Curro).
- Add PICK
killed any previous definition of the
same subregister even if the write was less than 8 channels wide,
which can cause live flag register updates to be dead
code-eliminated incorrectly.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4_dead_code_eliminate.cpp | 2 +-
1 file
horiz_offset() doesn't make sense to destination registers on some
cases like null registers.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_ir_vec4.h | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_ir
Now the VEC4_OPCODE_FROM_DOUBLE's destination data is written with
stride 2. We need to take into account this when doing the split
so we don't overwrite data.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4.cpp | 7 ++-
1 file changed, 6 insertions(+),
On IVB, DF instructions have lowered the SIMD width to 4 but the
exec_size will be later doubled. Fix the assert to avoid crashing in
this case.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4_generator.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_vec4.h | 3 ++-
src/intel/compiler/brw_vec4_nir.cpp | 15 ---
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index d12405c22e1
Generalize it to lower any unsupported narrower conversion.
v2 (Curro):
- Add supports_type_conversion()
- Reuse existing intruction instead of cloning it.
- Generalize d2x to narrower and equal size conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp
- Add comment into the code (Curro).
- Manage ARF registers like the others (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_ir_vec4.h | 14 ++
src/intel/compiler/brw_vec4.cpp | 10 ++
src/intel/compiler/brw_vec4_generator.cpp
tly (Matt).
- Use Baytrail instead of Valleview (Matt).
- Use IvyBridge instead of Ivy (Matt)
- Double the exec_size in code emission (Curro)
v3:
- Change hstride doubling by an assert and fix commit log (Curro).
- Substitute remaining compiler->devinfo by devinfo (Curro).
v4:
- Fix comment
s registers that are available, but by the EU decompression
logic not handling VxH indirect addressing correctly.
This patch limits the SIMD width to 4 in this case.
v2:
- Fix typo (Matt).
- Fix condition (Curro)
v3:
- Add spec quote (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: J
Then the SIMD lowering pass will get rid of any compressed instructions with
scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.
Signed-off-by: Samuel Iglesias Gonsálvez
Suggested-by: Francisco Jerez
Reviewed-by: Francisco Jerez
---
src
From: Francisco Jerez
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_generator.cpp | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index
The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/intel
From: Matt Turner
Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead
of two.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu_emit.c | 28 +++-
src/intel/compiler/brw_vec4_generator.cpp | 13 +
2 files
'is_dst' argument of brw_reg_from_fs_reg() (Curro)
- Fix comment (Curro).
- Relax hstride assert (Curro)
Signed-off-by: Juan A. Suarez Romero
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_generator.cpp | 68 -
1 file changed,
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/Makefile.sources | 2 +-
src/intel/compiler/brw_fs.cpp | 2 +-
src/intel/compiler/brw_fs.h | 2
Use static inline function instead of fs_inst's method (Curro).
- Define the result as a constant (Curro).
- Fix indentation (Matt).
- Add braces to nested control flow (Matt).
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/intel/compiler/brw_fs.cpp | 6 +-
ent explaining the reason (Curro).
Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
---
src/intel/compiler/brw_fs_generator.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_g
From: Matt Turner
On IVB/BYT, region parameters and execution size for DF are in terms of
32-bit elements, so they are doubled. For evaluating the validity of an
instruction, we halve them.
v2 (Sam):
- Add comments.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler
i965: Use source region <1,2,0> when converting to DF.
i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.
i965: Use correct VertStride on align16 instructions.
Samuel Iglesias Gonsálvez (14):
i965/fs: clamp exec_size when an instruction has a scalar DF source
i965/f
From: Iago Toral Quiroga
4-wide DF operations where NibCtrl applies require and execsize of 8
in IvyBridge/BayTrail.
v2:
- Refactor NibCtrl printing (Matt)
Reviewed-by: Matt Turner
Reviewed-by: Francisco Jerez
---
src/intel/compiler/brw_disasm.c | 6 +++---
1 file changed, 3 insertions(+), 3
Series is:
Reviewed-by: Samuel Iglesias Gonsálvez
On Sun, 2017-03-19 at 20:28 -0700, Kenneth Graunke wrote:
> In commit d2590eb65ff28a9cbd592353d15d7e6cbd2c6fc6 I enabled GL 4.5
> on Haswell...but failed to check if we could do indirect compute
> shader dispatch...and query buffe
-02-14 at 14:01 +0100, Samuel Iglesias Gonsálvez wrote:
> From: "Juan A. Suarez Romero"
>
> When splitting a CMP/MOV instruction with NULL dest, DF sources, and
> conditional modifier; we can't use directly the flag registers, as
> they will
> have the w
On 16/03/17 04:23, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 00:19, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> Add support to SEL instruction and add an assert to detect unsupported
On 16/03/17 04:23, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 00:19, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> Add support to SEL instruction and add an assert to detect unsupported
On 14/03/17 11:17, Samuel Iglesias Gonsálvez wrote:
>
>
> On 04/03/17 00:19, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>>> Add support to SEL instruction and add an assert to detect unsupported
>>> instructions than do d2x con
On 04/03/17 00:19, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> Add support to SEL instruction and add an assert to detect unsupported
>> instructions than do d2x conversions.
>>
>> Signed-off-by: Samuel Iglesias Gonsálvez
>> ---
&
On 08/03/17 20:30, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 07/03/17 22:24, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> On 04/03/17 01:04, Francisco Jerez wrote:
>>>>> Samuel Igles
On 07/03/17 22:38, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 01:26, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> From: Matt Turner
>>>>
>>>> Otherwise for a pa
On 07/03/17 22:24, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 01:04, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> From: "Juan A. Suarez Romero"
>>>>
>>>&
On 07/03/17 22:39, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 07/03/17 14:10, Samuel Iglesias Gonsálvez wrote:
>>>
>>>
>>> On 04/03/17 01:13, Francisco Jerez wrote:
>>>> Samuel Iglesias Gonsálvez writes:
>>>
On 07/03/17 22:39, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 01:44, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> From: Matt Turner
>>>>
>>>> In commit c35fa7a,
On 07/03/17 14:10, Samuel Iglesias Gonsálvez wrote:
>
>
> On 04/03/17 01:13, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>>> From: "Juan A. Suarez Romero"
>>>
>>> Take into account offset values less than a full
On 04/03/17 01:44, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Matt Turner
>>
>> In commit c35fa7a, we changed the "width" of DF source registers to 2,
>> which is conceptually fine. Unfortunately a VertStride of 2 is not
>&
On 04/03/17 01:26, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Matt Turner
>>
>> Otherwise for a pack_double_2x32_split opcode, we emit:
>>
>>vec1 64 ssa_135 = pack_double_2x32_split ssa_133, ssa_134
>>
On 04/03/17 01:16, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> Add a new setup_imm_df() that allows the insertion of the instructions
>> before another one. This will be used in the lowering passes for DF
>> instructions.
>>
>> v2:
>&g
On 04/03/17 01:38, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: "Juan A. Suarez Romero"
>>
>> When splitting a CMP/MOV instruction with NULL dest, DF sources, and
>> conditional modifier; we can't use directly the flag regi
On 04/03/17 01:13, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: "Juan A. Suarez Romero"
>>
>> Take into account offset values less than a full register (32 bytes)
>> when getting the var from register.
>>
>> This is
On 04/03/17 01:04, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: "Juan A. Suarez Romero"
>>
>> When splitting VEC4_OPCODE_FROM_DOUBLE in Ivybridge/Baytrail, the second
>> part should use a temporal register, and then move
On 04/03/17 00:55, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: "Juan A. Suarez Romero"
>>
>> In the generator we must generate slightly different code for
>> Ivybridge/Baytrail, because of the way the stride works in
>>
On 04/03/17 00:32, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> We need to split DF instructions in two on IVB/BYT as it needs an
>> execsize 8 to process 4 DF values (one GRF in total).
>>
>> v2:
>> - Rename helper and make it sta
On 04/03/17 00:19, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> Add support to SEL instruction and add an assert to detect unsupported
>> instructions than do d2x conversions.
>>
>> Signed-off-by: Samuel Iglesias Gonsálvez
>> ---
&
On 27/02/17 22:02, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> Previously, if we had accesses with different sizes to the same uniform, we
>> might not
>> push it aligned with the bigger one. This is a problem in BSW/BXT when we
>> access
On 24/02/17 21:54, Jason Ekstrand wrote:
> On Fri, Feb 24, 2017 at 6:05 AM, Samuel Iglesias Gonsálvez
> mailto:sigles...@igalia.com>> wrote:
>
>
>
> On 24/02/17 02:14, Jason Ekstrand wrote:
> > Each of the pop functions (and push_else) take a c
Patches 2-5 and 7-8 are:
Reviewed-by: Samuel Iglesias Gonsálvez
On 24/02/17 02:14, Jason Ekstrand wrote:
> ---
> src/compiler/glsl/glsl_to_nir.cpp | 38 +++---
> 1 file changed, 11 insertions(+), 27 deletions(-)
>
> diff --git a/sr
On 24/02/17 02:14, Jason Ekstrand wrote:
> Each of the pop functions (and push_else) take a control flow parameter as
> their second argument. If NULL, it assumes that the builder is in a block
> that's a direct child of the control-flow node you want to pop off the
> virtual stack. This is wha
. However this problem can happen with
other
generations and bitsizes.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 50
1 file changed, 34 insertions(+), 16 deletions(-)
diff --git a/src/mesa/driver
amuel Iglesias Gonsálvez
Cc: "17.0"
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 41
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a977ee4273..10
This bug can make that we don't detect the end of a contiguous area
correctly and push larger areas than the real ones.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
---
I am sending this mini-series to replace this patch from v2:
"[PATCH v2 1/3] i965/fs: fix indir
ents must be a
multiple of 4, which is what we were asserting before. However as we are
asserting the limits for raw surfaces, this doesn't apply here.
> Reviewed-by: Jason Ekstrand <mailto:ja...@jlekstrand.net>>
>
Thanks!
Sam
> On Wed, Feb 22, 2017 at 3:39 AM, Samu
value is 1, according to the spec. The spec quote
was already added into the code by 028f6d8317f00.
Fixes crashing tests under:
dEQP-VK.robustness.buffer_access.*
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: ja...@jlekstrand.net
---
src/intel/isl/isl_surface_state.c | 2 +-
1 file changed, 1 inser
On 21/02/17 21:07, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 20/02/17 21:31, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>>> On Mon, 2017-02-20 at 08:58 +0100, Samuel Iglesias Gonsálvez wrote:
>>
On 20/02/17 21:31, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On Mon, 2017-02-20 at 08:58 +0100, Samuel Iglesias Gonsálvez wrote:
>>> On Sat, 2017-02-18 at 18:58 -0800, Francisco Jerez wrote:
>>>> Samuel Iglesias Gonsálvez writes:
>&g
Reviewed-by: Samuel Iglesias Gonsálvez
On Mon, 2017-02-20 at 15:28 +0200, Lonnberg, Toni wrote:
> The function definition is now next to where the other similar
> functions are
> defined.
> ---
> src/mesa/drivers/dri/i965/brw_eu.h | 3 +--
> 1 file changed, 1 inserti
On Mon, 2017-02-20 at 08:58 +0100, Samuel Iglesias Gonsálvez wrote:
> On Sat, 2017-02-18 at 18:58 -0800, Francisco Jerez wrote:
> > Samuel Iglesias Gonsálvez writes:
> >
> > > The lowered BSW/BXT indirect move instructions had incorrect
> > > source types, which
On Sat, 2017-02-18 at 18:58 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > The lowered BSW/BXT indirect move instructions had incorrect
> > source types, which luckily wasn't causing incorrect assembly to be
> > generated due to the bug fixed
Reviewed-by: Samuel Iglesias Gonsálvez
On Sat, 2017-02-11 at 17:21 +0100, Alejandro Piñeiro wrote:
> ---
> src/mesa/main/formatquery.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/main/formatquery.c
> b/src/mesa/main/for
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 5c6f3d490f0..5ef92897b62
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 93ab84b5845..8f57069398a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
handle is actually unsigned. This patch fixes these cases before
applying the aforementioned patch.
Signed-off-by: Samuel Iglesias Gonsálvez
Cc: "17.0"
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/m
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