On Jul 8, 2017 1:59 PM, "Christian König" wrote:
Am 08.07.2017 um 00:27 schrieb Marek Olšák:
> On Fri, Jul 7, 2017 at 9:37 PM, Dave Airlie wrote:
>
>> On 8 July 2017 at 04:07, Christian König wrote:
>>
>>> Am 07.07.2017 um
Am 08.07.2017 um 00:27 schrieb Marek Olšák:
On Fri, Jul 7, 2017 at 9:37 PM, Dave Airlie wrote:
On 8 July 2017 at 04:07, Christian König wrote:
Am 07.07.2017 um 18:51 schrieb Marek Olšák:
On Fri, Jul 7, 2017 at 11:18 AM, Christian König
On Fri, Jul 7, 2017 at 9:37 PM, Dave Airlie wrote:
> On 8 July 2017 at 04:07, Christian König wrote:
>> Am 07.07.2017 um 18:51 schrieb Marek Olšák:
>>>
>>> On Fri, Jul 7, 2017 at 11:18 AM, Christian König
>>> wrote:
From: Dave Airlie
(this patch doesn't seem to work fully, hopefully AMD can tell us
more info on the rules, and how to calculate the magic).
It appears that to get full access to memory bandwidth with MRT
rendering the pro vulkan driver seems to offset each image by 0x3800.
On 8 July 2017 at 04:07, Christian König wrote:
> Am 07.07.2017 um 18:51 schrieb Marek Olšák:
>>
>> On Fri, Jul 7, 2017 at 11:18 AM, Christian König
>> wrote:
>>>
>>> What tilling format have the destination textures?
>>>
>>> Sounds like the
Am 07.07.2017 um 18:51 schrieb Marek Olšák:
On Fri, Jul 7, 2017 at 11:18 AM, Christian König
wrote:
What tilling format have the destination textures?
Sounds like the offset is just added so that we distribute memory accesses
more equally over memory channels.
You
On Fri, Jul 7, 2017 at 11:18 AM, Christian König
wrote:
> What tilling format have the destination textures?
>
> Sounds like the offset is just added so that we distribute memory accesses
> more equally over memory channels.
You can't set an offset that is not aligned.
On 7 Jul. 2017 19:29, "Christian König" wrote:
What tilling format have the destination textures?
Sounds like the offset is just added so that we distribute memory accesses
more equally over memory channels.
>From the traces i think tile index mode was 10.
Dave.
What tilling format have the destination textures?
Sounds like the offset is just added so that we distribute memory
accesses more equally over memory channels.
Regards,
Christian.
Am 07.07.2017 um 09:18 schrieb Dave Airlie:
From: Dave Airlie
(this patch doesn't seem
From: Dave Airlie
(this patch doesn't seem to work fully, hopefully AMD can tell us
more info on the rules, and how to calculate the magic).
It appears that to get full access to memory bandwidth with MRT
rendering the pro vulkan driver seems to offset each image by 0x3800.
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