From: XiaoYuan Zheng <xiaoyuan.zh...@amd.com> --- src/amd/addrlib/addrinterface.h | 3 +++ src/amd/addrlib/core/addrlib1.cpp | 31 +++++++++++++++---------- src/amd/addrlib/core/addrlib1.h | 8 +++++++ src/amd/addrlib/r800/ciaddrlib.cpp | 47 +++++++++++++++++++++++++++++++++++++- src/amd/addrlib/r800/ciaddrlib.h | 4 ++++ 5 files changed, 80 insertions(+), 13 deletions(-)
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index 01d8788..0795967 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -844,28 +844,31 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT { UINT_32 size; ///< Size of this structure in bytes UINT_32 pitch; ///< Pitch, in pixels UINT_32 height; ///< Height in pixels UINT_32 x; ///< X coordinate UINT_32 y; ///< Y coordinate UINT_32 slice; ///< Index of slice UINT_32 numSlices; ///< Number of slices BOOL_32 isLinear; ///< Linear or tiled HTILE layout + ADDR_HTILE_FLAGS flags; ///< htile flags AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 ADDR_TILEINFO* pTileInfo; ///< Tile info INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it /// while the global useTileIndex is set to 1 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) ///< README: When tileIndex is not -1, this must be valid + UINT_32 bpp; ///< depth/stencil buffer bit per pixel size + UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; /** *************************************************************************************************** * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * * @brief * Output structure for AddrComputeHtileAddrFromCoord *************************************************************************************************** */ diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index 1dc61e0..f0fd08c 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -1415,32 +1415,39 @@ ADDR_E_RETURNCODE AddrLib1::ComputeHtileAddrFromCoord( input.pTileInfo = &tileInfoNull; returnCode = HwlSetupTileCfg(0, input.tileIndex, input.macroModeIndex, input.pTileInfo); // Change the input structure pIn = &input; } if (returnCode == ADDR_OK) { - pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch, - pIn->height, - pIn->x, - pIn->y, - pIn->slice, - pIn->numSlices, - 1, - pIn->isLinear, - isWidth8, - isHeight8, - pIn->pTileInfo, - &pOut->bitPosition); + if (pIn->flags.tcCompatible) + { + HwlComputeHtileAddrFromCoord(pIn, pOut); + } + else + { + pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch, + pIn->height, + pIn->x, + pIn->y, + pIn->slice, + pIn->numSlices, + 1, + pIn->isLinear, + isWidth8, + isHeight8, + pIn->pTileInfo, + &pOut->bitPosition); + } } } return returnCode; } /** *************************************************************************************************** * AddrLib1::ComputeHtileCoordFromAddr diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h index 1bdfd5b..25af637 100644 --- a/src/amd/addrlib/core/addrlib1.h +++ b/src/amd/addrlib/core/addrlib1.h @@ -283,20 +283,28 @@ protected: } /// Virtual function to get cmask address for tc compatible cmask virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const { return ADDR_NOTSUPPORTED; } + /// Virtual function to get htile address for tc compatible htile + virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const + { + return ADDR_NOTSUPPORTED; + } + // Compute attributes // HTILE UINT_32 ComputeHtileInfo( ADDR_HTILE_FLAGS flags, UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pHtileBytes, UINT_32* pMacroWidth = NULL, UINT_32* pMacroHeight = NULL, diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index d4f8c64..57416dc 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -301,34 +301,79 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord( (pIn->flags.tcCompatible == TRUE)) { UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); UINT_32 numOfBanks = pIn->pTileInfo->banks; UINT_64 fmaskAddress = pIn->fmaskAddr; UINT_32 elemBits = pIn->bpp; UINT_32 blockByte = 64 * elemBits / 8; UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(fmaskAddress, 0, 0, - 4, + 4, // cmask 4 bits elemBits, blockByte, m_pipeInterleaveBytes, numOfPipes, numOfBanks, 1); pOut->addr = (metaNibbleAddress >> 1); pOut->bitPosition = (metaNibbleAddress % 2) ? 4 : 0; returnCode = ADDR_OK; } return returnCode; } + +/** +*************************************************************************************************** +* CiAddrLib::HwlComputeHtileAddrFromCoord +* +* @brief +* Compute tc compatible Htile address from depth/stencil address +* +* @return +* ADDR_E_RETURNCODE +*************************************************************************************************** +*/ +ADDR_E_RETURNCODE CiAddrLib::HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, ///< [in] depth/stencil addr/bpp/tile input + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] htile address + ) const +{ + ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED; + + if ((m_settings.isVolcanicIslands == TRUE) && + (pIn->flags.tcCompatible == TRUE)) + { + UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); + UINT_32 numOfBanks = pIn->pTileInfo->banks; + UINT_64 zStencilAddr = pIn->zStencilAddr; + UINT_32 elemBits = pIn->bpp; + UINT_32 blockByte = 64 * elemBits / 8; + UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(zStencilAddr, + 0, + 0, + 32, // htile 32 bits + elemBits, + blockByte, + m_pipeInterleaveBytes, + numOfPipes, + numOfBanks, + 1); + pOut->addr = (metaNibbleAddress >> 1); + pOut->bitPosition = 0; + returnCode = ADDR_OK; + } + + return returnCode; +} + /** *************************************************************************************************** * CiAddrLib::HwlConvertChipFamily * * @brief * Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision * @return * AddrChipFamily *************************************************************************************************** */ diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h index 1e3dc56..750b2b3 100644 --- a/src/amd/addrlib/r800/ciaddrlib.h +++ b/src/amd/addrlib/r800/ciaddrlib.h @@ -147,20 +147,24 @@ protected: AddrTileType* pTileType) const; virtual ADDR_E_RETURNCODE HwlComputeDccInfo( const ADDR_COMPUTE_DCCINFO_INPUT* pIn, ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const; virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const; + virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const; + virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const; virtual VOID HwlPadDimensions( AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign, UINT_32* pSlices, UINT_32 sliceAlign) const; private: VOID ReadGbTileMode( -- 2.7.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev