We need to do this in order to handle Yf and Ys tiling because they use a four-dimensional tile instead of laying everything out in two dimensions. --- src/intel/blorp/blorp_blit.c | 8 ++- src/intel/isl/isl.c | 60 ++++++++++++++++++---- src/intel/isl/isl.h | 37 ++++++++++--- src/intel/isl/isl_storage_image.c | 6 ++- .../isl/tests/isl_surf_get_image_offset_test.c | 4 +- src/mesa/drivers/dri/i965/intel_blit.c | 7 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 7 files changed, 102 insertions(+), 27 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 0757db0..46cfc37 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1927,11 +1927,15 @@ shrink_surface_params(const struct isl_device *dev, */ x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa; y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa; + uint32_t tile_z_sa, tile_a; isl_tiling_get_intratile_offset_sa(info->surf.tiling, info->surf.format, info->surf.row_pitch, - x_offset_sa, y_offset_sa, + info->surf.array_pitch_el_rows, + x_offset_sa, y_offset_sa, 0, 0, &byte_offset, - &info->tile_x_sa, &info->tile_y_sa); + &info->tile_x_sa, &info->tile_y_sa, + &tile_z_sa, &tile_a); + assert(tile_z_sa == 0 && tile_a == 0); info->addr.offset += byte_offset; diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index bba7310..cbe295b 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2087,7 +2087,9 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_sa, - uint32_t *y_offset_sa) + uint32_t *y_offset_sa, + uint32_t *z_offset_sa, + uint32_t *array_offset) { assert(level < surf->levels); assert(logical_array_layer < surf->logical_level0_px.array_len); @@ -2098,21 +2100,29 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf, case ISL_DIM_LAYOUT_GEN9_1D: get_image_offset_sa_gen9_1d(surf, level, logical_array_layer, x_offset_sa, y_offset_sa); + *z_offset_sa = 0; + *array_offset = 0; break; case ISL_DIM_LAYOUT_GEN4_2D: get_image_offset_sa_gen4_2d(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); + *z_offset_sa = 0; + *array_offset = 0; break; case ISL_DIM_LAYOUT_GEN4_3D: get_image_offset_sa_gen4_3d(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); + *z_offset_sa = 0; + *array_offset = 0; break; case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); + *z_offset_sa = 0; + *array_offset = 0; break; default: @@ -2126,7 +2136,9 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_el, - uint32_t *y_offset_el) + uint32_t *y_offset_el, + uint32_t *z_offset_el, + uint32_t *array_offset) { const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); @@ -2135,15 +2147,18 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf, assert(logical_z_offset_px < isl_minify(surf->logical_level0_px.depth, level)); - uint32_t x_offset_sa, y_offset_sa; + uint32_t x_offset_sa, y_offset_sa, z_offset_sa; isl_surf_get_image_offset_sa(surf, level, logical_array_layer, logical_z_offset_px, &x_offset_sa, - &y_offset_sa); + &y_offset_sa, + &z_offset_sa, + array_offset); *x_offset_el = x_offset_sa / fmtl->bw; *y_offset_el = y_offset_sa / fmtl->bh; + *z_offset_el = z_offset_sa / fmtl->bd; } void @@ -2190,18 +2205,29 @@ isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf, const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); uint32_t total_x_offset_el, total_y_offset_el; + uint32_t total_z_offset_el, total_array_offset; isl_surf_get_image_offset_el(surf, level, logical_array_layer, logical_z_offset_px, &total_x_offset_el, - &total_y_offset_el); + &total_y_offset_el, + &total_z_offset_el, + &total_array_offset); + uint32_t z_offset_el, array_offset; isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb, surf->row_pitch, + surf->array_pitch_el_rows, total_x_offset_el, total_y_offset_el, + total_z_offset_el, + total_array_offset, offset_B, x_offset_el, - y_offset_el); + y_offset_el, + &z_offset_el, + &array_offset); + assert(z_offset_el == 0); + assert(array_offset == 0); } void @@ -2248,26 +2274,34 @@ isl_surf_get_image_surf(const struct isl_device *dev, void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t bpb, - uint32_t row_pitch, + uint32_t row_pitch_B, + uint32_t array_pitch_el_rows, uint32_t total_x_offset_el, uint32_t total_y_offset_el, + uint32_t total_z_offset_el, + uint32_t total_array_offset, uint32_t *base_address_offset, uint32_t *x_offset_el, - uint32_t *y_offset_el) + uint32_t *y_offset_el, + uint32_t *z_offset_el, + uint32_t *array_offset) { if (tiling == ISL_TILING_LINEAR) { assert(bpb % 8 == 0); - *base_address_offset = total_y_offset_el * row_pitch + + assert(total_z_offset_el == 0 && total_array_offset == 0); + *base_address_offset = total_y_offset_el * row_pitch_B + total_x_offset_el * (bpb / 8); *x_offset_el = 0; *y_offset_el = 0; + *z_offset_el = 0; + *array_offset = 0; return; } struct isl_tile_info tile_info; isl_tiling_get_info(tiling, bpb, &tile_info); - assert(row_pitch % tile_info.phys_extent_B.width == 0); + assert(row_pitch_B % tile_info.phys_extent_B.width == 0); /* For non-power-of-two formats, we need the address to be both tile and * element-aligned. The easiest way to achieve this is to work with a tile @@ -2284,13 +2318,17 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, /* Compute the offset into the tile */ *x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w; *y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h; + assert(total_z_offset_el == 0); + assert(total_array_offset == 0); + *z_offset_el = 0; + *array_offset = 0; /* Compute the offset of the tile in units of whole tiles */ uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w; uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h; *base_address_offset = - y_offset_tl * tile_info.phys_extent_B.h * row_pitch + + y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B + x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w; } diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 142a92c..6cee631 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1864,7 +1864,9 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_sa, - uint32_t *y_offset_sa); + uint32_t *y_offset_sa, + uint32_t *z_offset_sa, + uint32_t *array_offset); /** * Calculate the offset, in units of surface elements, to a subimage in the @@ -1880,7 +1882,9 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_el, - uint32_t *y_offset_el); + uint32_t *y_offset_el, + uint32_t *z_offset_el, + uint32_t *array_offset); /** * Calculate the offset, in bytes and intratile surface samples, to a @@ -1960,21 +1964,31 @@ void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t bpb, uint32_t row_pitch, + uint32_t array_pitch_el_rows, uint32_t total_x_offset_el, uint32_t total_y_offset_el, + uint32_t total_z_offset_el, + uint32_t total_array_offset, uint32_t *base_address_offset, uint32_t *x_offset_el, - uint32_t *y_offset_el); + uint32_t *y_offset_el, + uint32_t *z_offset_el, + uint32_t *array_offset); static inline void isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, enum isl_format format, uint32_t row_pitch, + uint32_t array_pitch_el_rows, uint32_t total_x_offset_sa, uint32_t total_y_offset_sa, + uint32_t total_z_offset_sa, + uint32_t total_array_offset, uint32_t *base_address_offset, uint32_t *x_offset_sa, - uint32_t *y_offset_sa) + uint32_t *y_offset_sa, + uint32_t *z_offset_sa, + uint32_t *array_offset) { const struct isl_format_layout *fmtl = isl_format_get_layout(format); @@ -1984,15 +1998,22 @@ isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, */ assert(total_x_offset_sa % fmtl->bw == 0); assert(total_y_offset_sa % fmtl->bh == 0); - const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw; - const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh; + const uint32_t total_x_offset_el = total_x_offset_sa / fmtl->bw; + const uint32_t total_y_offset_el = total_y_offset_sa / fmtl->bh; + const uint32_t total_z_offset_el = total_z_offset_sa / fmtl->bd; isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch, - total_x_offset, total_y_offset, + array_pitch_el_rows, + total_x_offset_el, + total_y_offset_el, + total_z_offset_el, + total_array_offset, base_address_offset, - x_offset_sa, y_offset_sa); + x_offset_sa, y_offset_sa, + z_offset_sa, array_offset); *x_offset_sa *= fmtl->bw; *y_offset_sa *= fmtl->bh; + *z_offset_sa *= fmtl->bd; } /** diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c index 20f6fd5..0ae79a2 100644 --- a/src/intel/isl/isl_storage_image.c +++ b/src/intel/isl/isl_storage_image.c @@ -233,12 +233,16 @@ isl_surf_fill_image_param(const struct isl_device *dev, view->base_array_layer; } + uint32_t tile_z_el, phys_array_layer; isl_surf_get_image_offset_el(surf, view->base_level, surf->dim == ISL_SURF_DIM_3D ? 0 : view->base_array_layer, surf->dim == ISL_SURF_DIM_3D ? view->base_array_layer : 0, - ¶m->offset[0], ¶m->offset[1]); + ¶m->offset[0], ¶m->offset[1], + &tile_z_el, &phys_array_layer); + assert(tile_z_el == 0); + assert(phys_array_layer == 0); const int cpp = isl_format_get_layout(surf->format)->bpb / 8; param->stride[0] = cpp; diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c index 05fd79f..42c12c8 100644 --- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c +++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -85,9 +85,9 @@ t_assert_offset_el(const struct isl_surf *surf, uint32_t expected_x_offset_el, uint32_t expected_y_offset_el) { - uint32_t x, y; + uint32_t x, y, z, a; isl_surf_get_image_offset_el(surf, level, logical_array_layer, - logical_z_offset_px, &x, &y); + logical_z_offset_px, &x, &y, &z, &a); t_assert(x == expected_x_offset_el); t_assert(y == expected_y_offset_el); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index dcecab6..b93db1c 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -177,11 +177,16 @@ get_blit_intratile_offset_el(const struct brw_context *brw, uint32_t *x_offset_el, uint32_t *y_offset_el) { + uint32_t z_offset_el, array_offset; isl_tiling_get_intratile_offset_el(mt->surf.tiling, mt->cpp * 8, mt->surf.row_pitch, + mt->surf.array_pitch_el_rows, total_x_offset_el, total_y_offset_el, + 0, 0, base_address_offset, - x_offset_el, y_offset_el); + x_offset_el, y_offset_el, + &z_offset_el, &array_offset); + assert(z_offset_el == 0 && array_offset == 0); if (mt->surf.tiling == ISL_TILING_LINEAR) { /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress: * diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 6d35c9d..59dbfb9 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1341,7 +1341,7 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, return; } - uint32_t x_offset_sa, y_offset_sa; + uint32_t x_offset_sa, y_offset_sa, z_offset_sa, array_offset; /* Miptree itself can have an offset only if it represents a single * slice in an imported buffer object. @@ -1359,10 +1359,13 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0; slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice; isl_surf_get_image_offset_el(&mt->surf, level, slice, z, - &x_offset_sa, &y_offset_sa); + &x_offset_sa, &y_offset_sa, + &z_offset_sa, &array_offset); *x = x_offset_sa; *y = y_offset_sa; + assert(z_offset_sa == 0); + assert(array_offset == 0); } -- 2.5.0.400.gff86faf _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev