From: Nicolai Hähnle <nicolai.haeh...@amd.com> Signed-off-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/amd/addrlib/r800/ciaddrlib.cpp | 25 ++++++------------------- src/amd/addrlib/r800/egbaddrlib.cpp | 18 +++++++++--------- 2 files changed, 15 insertions(+), 28 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 3509024..fccf09d 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -1198,21 +1198,21 @@ VOID CiLib::HwlSetupTileInfo( // Turn off tc compatible if row_size is smaller than tile size (tile split occurs). if (m_rowSize < tileSize) { flags.tcCompatible = FALSE; pOut->tcCompatible = FALSE; } if (flags.depth && (flags.nonSplit || flags.tcCompatible || flags.needEquation)) { - // Texure readable depth surface should not be split + // Texture readable depth surface should not be split switch (tileSize) { case 128: index = 1; break; case 256: index = 2; break; case 512: index = 3; @@ -1300,26 +1300,26 @@ VOID CiLib::HwlSetupTileInfo( default: break; } } // See table entries 19-26 if (thickness > 1) { switch (tileMode) { - case ADDR_TM_1D_TILED_THICK: - //special check for bonaire, for the compatablity between old KMD and new UMD for bonaire + case ADDR_TM_1D_TILED_THICK: + // special check for bonaire, for the compatablity between old KMD and new UMD index = ((inTileType == ADDR_THICK) || m_settings.isBonaire) ? 19 : 18; break; - case ADDR_TM_2D_TILED_THICK: - // special check for bonaire, for the compatablity between old KMD and new UMD for bonaire + case ADDR_TM_2D_TILED_THICK: + // special check for bonaire, for the compatablity between old KMD and new UMD index = ((inTileType == ADDR_THICK) || m_settings.isBonaire) ? 20 : 24; break; case ADDR_TM_3D_TILED_THICK: index = 21; break; case ADDR_TM_PRT_TILED_THICK: index = 22; break; case ADDR_TM_2D_TILED_XTHICK: index = 25; @@ -1394,21 +1394,21 @@ VOID CiLib::HwlSetupTileInfo( // pass tile type back for post tile index compute pOut->tileType = inTileType; } // We only need to set up tile info if there is a valid index but macroModeIndex is invalid if (index != TileIndexInvalid && macroModeIndex == TileIndexInvalid) { macroModeIndex = HwlComputeMacroModeIndex(index, flags, bpp, numSamples, pTileInfo); - /// Copy to pOut->tileType/tileIndex/macroModeIndex + // Copy to pOut->tileType/tileIndex/macroModeIndex pOut->tileIndex = index; pOut->tileType = m_tileTable[index].type; // Or inTileType, the samea pOut->macroModeIndex = macroModeIndex; } else if (tileMode == ADDR_TM_LINEAR_GENERAL) { pOut->tileIndex = TileIndexLinearGeneral; // Copy linear-aligned entry?? *pTileInfo = m_tileTable[8].info; @@ -1456,22 +1456,20 @@ VOID CiLib::HwlSetupTileInfo( } } } /** **************************************************************************************************** * CiLib::ReadGbTileMode * * @brief * Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG. -* @return -* NA. **************************************************************************************************** */ VOID CiLib::ReadGbTileMode( UINT_32 regValue, ///< [in] GB_TILE_MODE register TileConfig* pCfg ///< [out] output structure ) const { GB_TILE_MODE gbTileMode; gbTileMode.val = regValue; @@ -1601,22 +1599,20 @@ BOOL_32 CiLib::InitTileSettingTable( return initOk; } /** **************************************************************************************************** * CiLib::ReadGbMacroTileCfg * * @brief * Convert GB_MACRO_TILE_CFG HW value to ADDR_TILE_CONFIG. -* @return -* NA. **************************************************************************************************** */ VOID CiLib::ReadGbMacroTileCfg( UINT_32 regValue, ///< [in] GB_MACRO_TILE_MODE register ADDR_TILEINFO* pCfg ///< [out] output structure ) const { GB_MACROTILE_MODE gbTileMode; gbTileMode.val = regValue; @@ -1773,23 +1769,20 @@ INT_32 CiLib::HwlComputeMacroModeIndex( return macroModeIndex; } /** **************************************************************************************************** * CiLib::HwlComputeTileDataWidthAndHeightLinear * * @brief * Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout * -* @return -* N/A -* * @note * MacroWidth and macroHeight are measured in pixels **************************************************************************************************** */ VOID CiLib::HwlComputeTileDataWidthAndHeightLinear( UINT_32* pMacroWidth, ///< [out] macro tile width UINT_32* pMacroHeight, ///< [out] macro tile height UINT_32 bpp, ///< [in] bits per pixel ADDR_TILEINFO* pTileInfo ///< [in] tile info ) const @@ -1939,23 +1932,20 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress( return metadataAddress; } /** **************************************************************************************************** * CiLib::HwlComputeSurfaceAlignmentsMacroTiled * * @brief * Hardware layer function to compute alignment request for macro tile mode * -* @return -* N/A -* **************************************************************************************************** */ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled( AddrTileMode tileMode, ///< [in] tile mode UINT_32 bpp, ///< [in] bits per pixel ADDR_SURFACE_FLAGS flags, ///< [in] surface flags UINT_32 mipLevel, ///< [in] mip level UINT_32 numSamples, ///< [in] number of samples ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure. UINT_32* pBaseAlign, ///< [out] base address alignment in bytes @@ -1974,23 +1964,20 @@ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled( } } /** **************************************************************************************************** * CiLib::HwlPadDimensions * * @brief * Helper function to pad dimensions * -* @return -* N/A -* **************************************************************************************************** */ VOID CiLib::HwlPadDimensions( AddrTileMode tileMode, ///< [in] tile mode UINT_32 bpp, ///< [in] bits per pixel ADDR_SURFACE_FLAGS flags, ///< [in] surface flags UINT_32 numSamples, ///< [in] number of samples ADDR_TILEINFO* pTileInfo, ///< [in] tile info UINT_32 mipLevel, ///< [in] mip level UINT_32* pPitch, ///< [in,out] pitch in pixels diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp index 9655c47..f413cff 100644 --- a/src/amd/addrlib/r800/egbaddrlib.cpp +++ b/src/amd/addrlib/r800/egbaddrlib.cpp @@ -885,33 +885,33 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled( ); pTileInfo->bankHeight = PowTwoAlign(pTileInfo->bankHeight, bankHeightAlign); // num_pipes * bank_width * macro_tile_aspect >= // (pipe_interleave_size * bank_interleave) / tile_size if (numSamples == 1) { // this restriction is only for mipmap (mipmap's numSamples must be 1) macroAspectAlign = Max(1u, - m_pipeInterleaveBytes * m_bankInterleave / - (tileSize * pipes * pTileInfo->bankWidth) - ); + m_pipeInterleaveBytes * m_bankInterleave / + (tileSize * pipes * pTileInfo->bankWidth) + ); pTileInfo->macroAspectRatio = PowTwoAlign(pTileInfo->macroAspectRatio, macroAspectAlign); } valid = HwlReduceBankWidthHeight(tileSize, - bpp, - flags, - numSamples, - bankHeightAlign, - pipes, - pTileInfo); + bpp, + flags, + numSamples, + bankHeightAlign, + pipes, + pTileInfo); // // The required granularity for pitch is the macro tile width. // macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes * pTileInfo->macroAspectRatio; *pPitchAlign = macroTileWidth; *pMacroTileWidth = macroTileWidth; -- 2.7.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev