On Tuesday, February 20, 2018 9:15:12 PM PST Matt Turner wrote:
> @@ -306,6 +312,7 @@ unsigned
> brw_reg_type_to_size(enum brw_reg_type type)
> {
> static const unsigned type_size[] = {
> + [BRW_REGISTER_TYPE_NF] = 8,
This is a bit of a fib, given that NF is 66 bits, but...probably
This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.
One weird thing to note: align1 ternary instructions may only have an
accumulator in the
