On Sun, 2016-08-28 at 13:16 -0400, Ilia Mirkin wrote:
> Please add documentation for this new cap in
> src/gallium/docs/source/screen.rst . What is this supposed to
> represent btw? All G80+ GPUs operate in a 40-bit virtual address
> space, but pre-fermi there's no ability to get a compute shader
Please add documentation for this new cap in
src/gallium/docs/source/screen.rst . What is this supposed to
represent btw? All G80+ GPUs operate in a 40-bit virtual address
space, but pre-fermi there's no ability to get a compute shader to
access more than a 32-bit window at a time (actually 16
Signed-off-by: Jan Vesely
---
src/gallium/drivers/ilo/ilo_screen.c | 6 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
src/gallium/drivers/radeon/r600_pipe_common.c | 8