- Separate out the depth stall from the depth count write, workarounds
say that a depth stall needs to be preceeded with a non-zero
post-sync op.
- Implement the cs stall workaround like the kernel does.
I've hoped that this would fix a occlusion query issue on snb, but
alas, it doesn't seem to help.
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 53 ++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 240fe32..52db050 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -337,22 +337,34 @@ brw_emit_query_begin(struct brw_context *brw)
return;
if (intel->gen >= 6) {
- BEGIN_BATCH(8);
+ BEGIN_BATCH(12);
- /* workaround: CS stall required before depth stall. */
+ /* Workaround: A non-zero post-sync op (i.e. the DEPTH_COUNT write below
+ * needs a pipe control with CS_STALL set beforehand.
+ * Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
+ * like the kernel. */
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_CS_STALL);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
+ OUT_BATCH(PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ /* The actual DEPTH_COUNT write. */
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_WRITE_DEPTH_COUNT);
+ OUT_BATCH(PIPE_CONTROL_WRITE_DEPTH_COUNT);
OUT_RELOC(brw->query.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE |
((brw->query.index * 2) * sizeof(uint64_t)));
OUT_BATCH(0);
+
+ /* We need to emit depth stall to get the right value for the depth
+ * count. As a workaround this needs a preceeding pipe control with a
+ * non-zero post-sync op, the depth count write above does that for us.
*/
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
ADVANCE_BATCH();
} else {
@@ -395,21 +407,34 @@ brw_emit_query_end(struct brw_context *brw)
return;
if (intel->gen >= 6) {
- BEGIN_BATCH(8);
- /* workaround: CS stall required before depth stall. */
+ BEGIN_BATCH(12);
+
+ /* Workaround: A non-zero post-sync op (i.e. the DEPTH_COUNT write below
+ * needs a pipe control with CS_STALL set beforehand.
+ * Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
+ * like the kernel. */
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_CS_STALL);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
+ OUT_BATCH(PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ /* The actual DEPTH_COUNT write. */
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_WRITE_DEPTH_COUNT);
+ OUT_BATCH(PIPE_CONTROL_WRITE_DEPTH_COUNT);
OUT_RELOC(brw->query.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE |
((brw->query.index * 2 + 1) * sizeof(uint64_t)));
OUT_BATCH(0);
+
+ /* We need to emit depth stall to get the right value for the depth
+ * count. As a workaround this needs a preceeding pipe control with a
+ * non-zero post-sync op, the depth count write above does that for us.
*/
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
ADVANCE_BATCH();
} else {
--
1.7.10.4
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