Because the check was moved to radv_emit_prefetch_L2(). Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()") Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/amd/vulkan/radv_cmd_buffer.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 526b618f2a..a6d85e1b35 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -646,9 +646,6 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_state *state = &cmd_buffer->state; uint32_t mask = state->prefetch_L2_mask; - if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK) - return; - if (vertex_stage_only) { /* Fast prefetch path for starting draws as soon as possible. */ @@ -3040,6 +3037,8 @@ static void radv_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info) { + bool has_prefetch = + cmd_buffer->device->physical_device->rad_info.chip_class >= CIK; bool pipeline_is_dirty = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) && cmd_buffer->state.pipeline && @@ -3077,7 +3076,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer, * run in parallel, but starting the draw first is more * important. */ - if (cmd_buffer->state.prefetch_L2_mask) { + if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) { radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, false); } @@ -3104,7 +3103,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer, /* Prefetch the remaining shaders after the draw has been * started. */ - if (cmd_buffer->state.prefetch_L2_mask) { + if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) { radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, false); } @@ -3407,6 +3406,8 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info) { struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + bool has_prefetch = + cmd_buffer->device->physical_device->rad_info.chip_class >= CIK; bool pipeline_is_dirty = pipeline && pipeline != cmd_buffer->state.emitted_compute_pipeline; @@ -3434,7 +3435,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, * will run in parallel, but starting the dispatch first is * more important. */ - if (pipeline_is_dirty) { + if (has_prefetch && pipeline_is_dirty) { radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]); } @@ -3444,7 +3445,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, */ si_emit_cache_flush(cmd_buffer); - if (pipeline_is_dirty) { + if (has_prefetch && pipeline_is_dirty) { radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]); } -- 2.16.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev