Re: [Mesa-dev] [PATCH 14/47] i965/fs: Set stride 2 when dealing with 16-bit floats/ints

2017-09-07 Thread Jason Ekstrand
On Thu, Aug 24, 2017 at 6:54 AM, Alejandro Piñeiro wrote: > From: Jose Maria Casanova Crespo > > From Skylake PRM, Volume 07 3D Media GPGPU, Section Register Region > Restrictions, SubSection 5. Special Cases for Word Operations (page > 781): > >"There is a relaxed alignment rule for word de

[Mesa-dev] [PATCH 14/47] i965/fs: Set stride 2 when dealing with 16-bit floats/ints

2017-08-24 Thread Alejandro Piñeiro
From: Jose Maria Casanova Crespo From Skylake PRM, Volume 07 3D Media GPGPU, Section Register Region Restrictions, SubSection 5. Special Cases for Word Operations (page 781): "There is a relaxed alignment rule for word destinations. When the destination type is word (UW, W, HF), destinati