From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/radeon_uvd.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 3e060e2..cd58c66 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1337,26 +1337,23 @@ static void ruvd_flush(struct pipe_video_codec *decoder)
*/
struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context
*context,
const struct
pipe_video_codec *templ,
ruvd_set_dtb set_dtb)
{
struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
struct r600_common_context *rctx = (struct r600_common_context*)context;
unsigned dpb_size;
unsigned width = templ->width, height = templ->height;
unsigned bs_buf_size;
- struct radeon_info info;
struct ruvd_decoder *dec;
int r, i;
- ws->query_info(ws, &info);
-
switch(u_reduce_video_profile(templ->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
return vl_create_mpeg12_decoder(context, templ);
/* fall through */
case PIPE_VIDEO_FORMAT_MPEG4:
width = align(width, VL_MACROBLOCK_WIDTH);
height = align(height, VL_MACROBLOCK_HEIGHT);
break;
@@ -1368,47 +1365,47 @@ struct pipe_video_codec
*si_common_uvd_create_decoder(struct pipe_context *conte
default:
break;
}
dec = CALLOC_STRUCT(ruvd_decoder);
if (!dec)
return NULL;
- if (info.drm_major < 3)
+ if (rctx->screen->info.drm_major < 3)
dec->use_legacy = true;
dec->base = *templ;
dec->base.context = context;
dec->base.width = width;
dec->base.height = height;
dec->base.destroy = ruvd_destroy;
dec->base.begin_frame = ruvd_begin_frame;
dec->base.decode_macroblock = ruvd_decode_macroblock;
dec->base.decode_bitstream = ruvd_decode_bitstream;
dec->base.end_frame = ruvd_end_frame;
dec->base.flush = ruvd_flush;
- dec->stream_type = profile2stream_type(dec, info.family);
+ dec->stream_type = profile2stream_type(dec, rctx->family);
dec->set_dtb = set_dtb;
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
}
- dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
+ dec->fb_size = (rctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
FB_BUFFER_SIZE;
bs_buf_size = width * height * (512 / (16 * 16));
for (i = 0; i < NUM_BUFFERS; ++i) {
unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
if (have_it(dec))
msg_fb_it_size += IT_SCALING_TABLE_SIZE;
if (!si_vid_create_buffer(dec->screen,
&dec->msg_fb_it_buffers[i],
msg_fb_it_size, PIPE_USAGE_STAGING)) {
RVID_ERR("Can't allocated message buffers.\n");
@@ -1427,40 +1424,40 @@ struct pipe_video_codec
*si_common_uvd_create_decoder(struct pipe_context *conte
dpb_size = calc_dpb_size(dec);
if (dpb_size) {
if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated dpb.\n");
goto error;
}
si_vid_clear_buffer(context, &dec->dpb);
}
- if (dec->stream_type == RUVD_CODEC_H264_PERF && info.family >=
CHIP_POLARIS10) {
+ if (dec->stream_type == RUVD_CODEC_H264_PERF && rctx->family >=
CHIP_POLARIS10) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated context buffer.\n");
goto error;
}
si_vid_clear_buffer(context, &dec->ctx);
}
- if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
+ if (rctx->family >= CHIP_POLARIS10 && rctx->screen->info.drm_minor >=
3) {
if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
UVD_SESSION_CONTEXT_SIZE,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated session ctx.\n");
goto error;
}
si_vid_clear_buffer(context, &dec->sessionctx);
}
- if (info.family >= CHIP_VEGA10) {
+ if (rctx->family >= CHIP_VEGA10) {
dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
} else {
dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
dec->reg.cntl = RUVD_ENGINE_CNTL;
}
--
2.7.4
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