Re: [Mesa-dev] [PATCH 3/3] i965: adjust gen6+ timestamp pipe_control writes

2012-07-02 Thread Daniel Vetter
On Sun, Jul 01, 2012 at 08:10:49PM -0700, Kenneth Graunke wrote: On 06/26/2012 07:28 AM, Daniel Vetter wrote: Similar treatment to the depth count pipe_control writes - Add the CS_STALL workaround, timestamp writes are non-zero post-sync ops, too. - Also ensure that we write the full

Re: [Mesa-dev] [PATCH 3/3] i965: adjust gen6+ timestamp pipe_control writes

2012-07-01 Thread Kenneth Graunke
On 06/26/2012 07:28 AM, Daniel Vetter wrote: Similar treatment to the depth count pipe_control writes - Add the CS_STALL workaround, timestamp writes are non-zero post-sync ops, too. - Also ensure that we write the full 64bits by using the 5 dword long variant of pipe_control. ---

[Mesa-dev] [PATCH 3/3] i965: adjust gen6+ timestamp pipe_control writes

2012-06-26 Thread Daniel Vetter
Similar treatment to the depth count pipe_control writes - Add the CS_STALL workaround, timestamp writes are non-zero post-sync ops, too. - Also ensure that we write the full 64bits by using the 5 dword long variant of pipe_control. --- src/mesa/drivers/dri/i965/brw_queryobj.c | 32