Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

2018-12-07 Thread Jason Ekstrand
On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the channel

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

2018-12-07 Thread Iago Toral
On Fri, 2018-12-07 at 15:06 +0200, Pohjolainen, Topi wrote: > On Tue, Dec 04, 2018 at 08:16:58AM +0100, Iago Toral Quiroga wrote: > > We use ALign16 mode for this, since it is more convenient, but the > > PRM > > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register > > region > >

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

2018-12-07 Thread Pohjolainen, Topi
On Tue, Dec 04, 2018 at 08:16:58AM +0100, Iago Toral Quiroga wrote: > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the

[Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

2018-12-03 Thread Iago Toral Quiroga
We use ALign16 mode for this, since it is more convenient, but the PRM for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region restrictions', Section '1. Special Restrictions': "In Align16 mode, the channel selects and channel enables apply to a pair of half-floats, because