Re: [Mesa-dev] [PATCH 40/95] i965/vec4: add a SIMD lowering pass

On Wed, 2016-08-03 at 14:32 -0700, Francisco Jerez wrote: > Iago Toral Quiroga  writes:...)writes:...) (...) > > +   return lo)+}++bool+vec4_visitor::lower_simd_width() > > +{ > > +   bool progress = false; > > + > > +   foreach_block_and_inst_safe(block, vec4_instruction,

Re: [Mesa-dev] [PATCH 40/95] i965/vec4: add a SIMD lowering pass

Iago Toral Quiroga writes: > Generally, instructions in Align16 mode only ever write to a single > register and don't need anny form of SIMD splitting, that's why we > have never had a SIMD splitting pass in the vec4 backend. However, > double-precision instructions typically

[Mesa-dev] [PATCH 40/95] i965/vec4: add a SIMD lowering pass

Generally, instructions in Align16 mode only ever write to a single register and don't need anny form of SIMD splitting, that's why we have never had a SIMD splitting pass in the vec4 backend. However, double-precision instructions typically write 2 registers and in some cases they run into