From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 54 ++++++-------------
.../drivers/radeonsi/si_shader_tgsi_mem.c | 18 +++----
.../drivers/radeonsi/si_shader_tgsi_setup.c | 14 ++---
3 files changed, 29 insertions(+), 57 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 29523474735..24ee45f578a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -371,38 +371,32 @@ get_tcs_in_current_patch_offset(struct si_shader_context
*ctx)
return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
}
static LLVMValueRef
get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
{
LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
- return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
- LLVMBuildMul(ctx->ac.builder, patch_stride,
- rel_patch_id, ""),
- "");
+ return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
patch0_offset);
}
static LLVMValueRef
get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
{
LLVMValueRef patch0_patch_data_offset =
get_tcs_out_patch0_patch_data_offset(ctx);
LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
- return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
- LLVMBuildMul(ctx->ac.builder, patch_stride,
- rel_patch_id, ""),
- "");
+ return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
patch0_patch_data_offset);
}
static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
{
unsigned tcs_out_vertices =
ctx->shader->selector ?
ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
/* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS
epilog. */
if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
@@ -808,26 +802,22 @@ LLVMValueRef si_get_indirect_index(struct
si_shader_context *ctx,
/* Set the second index to 0 for constants. */
if (ind->File == TGSI_FILE_CONSTANT)
src.Register.Dimension = 1;
result =
ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
TGSI_TYPE_SIGNED,
ind->Swizzle);
result = ac_to_integer(&ctx->ac, result);
}
- if (addr_mul != 1)
- result = LLVMBuildMul(ctx->ac.builder, result,
- LLVMConstInt(ctx->i32, addr_mul, 0), "");
- result = LLVMBuildAdd(ctx->ac.builder, result,
- LLVMConstInt(ctx->i32, rel_index, 0), "");
- return result;
+ return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul,
0),
+ LLVMConstInt(ctx->i32, rel_index, 0));
}
/**
* Like si_get_indirect_index, but restricts the return value to a (possibly
* undefined) value inside [0..num).
*/
LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
int rel_index, unsigned num)
{
@@ -840,29 +830,27 @@ static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context
LLVMValueRef
vertex_dw_stride,
LLVMValueRef base_addr,
LLVMValueRef
vertex_index,
LLVMValueRef
param_index,
unsigned input_index,
ubyte *name,
ubyte *index,
bool is_patch)
{
if (vertex_dw_stride) {
- base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
- LLVMBuildMul(ctx->ac.builder,
vertex_index,
- vertex_dw_stride, ""),
"");
+ base_addr = ac_build_imad(&ctx->ac, vertex_index,
+ vertex_dw_stride, base_addr);
}
if (param_index) {
- base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
- LLVMBuildMul(ctx->ac.builder,
param_index,
- LLVMConstInt(ctx->i32, 4,
0), ""), "");
+ base_addr = ac_build_imad(&ctx->ac, param_index,
+ LLVMConstInt(ctx->i32, 4, 0),
base_addr);
}
int param = is_patch ?
si_shader_io_get_unique_index_patch(name[input_index],
index[input_index]) :
si_shader_io_get_unique_index(name[input_index],
index[input_index], false);
/* Add the base address of the element. */
return LLVMBuildAdd(ctx->ac.builder, base_addr,
@@ -968,36 +956,29 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct
si_shader_context *ctx,
LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
LLVMValueRef param_stride, constant16;
vertices_per_patch = get_num_tcs_out_vertices(ctx);
num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
num_patches, "");
constant16 = LLVMConstInt(ctx->i32, 16, 0);
if (vertex_index) {
- base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
- vertices_per_patch, "");
-
- base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
- vertex_index, "");
-
+ base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
+ vertices_per_patch, vertex_index);
param_stride = total_vertices;
} else {
base_addr = rel_patch_id;
param_stride = num_patches;
}
- base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
- LLVMBuildMul(ctx->ac.builder, param_index,
- param_stride, ""), "");
-
+ base_addr = ac_build_imad(&ctx->ac, param_index, param_stride,
base_addr);
base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
if (!vertex_index) {
LLVMValueRef patch_data_offset =
si_unpack_param(ctx, ctx->param_tcs_offchip_layout,
12, 20);
base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
patch_data_offset, "");
}
return base_addr;
@@ -2816,23 +2797,23 @@ static void si_llvm_emit_streamout(struct
si_shader_context *ctx,
LLVMValueRef offset = LLVMConstInt(ctx->i32,
SI_VS_STREAMOUT_BUF0
+ i, 0);
so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
buf_ptr, offset);
LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
ctx->param_streamout_offset[i]);
so_offset = LLVMBuildMul(builder, so_offset,
LLVMConstInt(ctx->i32, 4, 0), "");
- so_write_offset[i] = LLVMBuildMul(builder,
so_write_index,
-
LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
- so_write_offset[i] = LLVMBuildAdd(builder,
so_write_offset[i], so_offset, "");
+ so_write_offset[i] = ac_build_imad(&ctx->ac,
so_write_index,
+
LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
+ so_offset);
}
/* Write streamout data. */
for (i = 0; i < so->num_outputs; i++) {
unsigned reg = so->output[i].register_index;
if (reg >= noutput)
continue;
if (stream != so->output[i].stream)
@@ -3051,32 +3032,31 @@ static void si_llvm_export_vs(struct si_shader_context
*ctx,
}
/**
* Forward all outputs from the vertex shader to the TES. This is only used
* for the fixed function TCS.
*/
static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef invocation_id, buffer, buffer_offset;
- LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
+ LLVMValueRef lds_vertex_stride, lds_base;
uint64_t inputs;
invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
buffer_offset = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
- lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
- lds_vertex_stride, "");
lds_base = get_tcs_in_current_patch_offset(ctx);
- lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset,
"");
+ lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
+ lds_base);
inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
while (inputs) {
unsigned i = u_bit_scan64(&inputs);
LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->i32, 4 * i, 0),
"");
LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 72faf755ade..54a0413e464 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -175,24 +175,22 @@ static LLVMValueRef force_dcc_off(struct
si_shader_context *ctx,
}
LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
LLVMValueRef list, LLVMValueRef index,
enum ac_descriptor_type desc_type, bool dcc_off)
{
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef rsrc;
if (desc_type == AC_DESC_BUFFER) {
- index = LLVMBuildMul(builder, index,
- LLVMConstInt(ctx->i32, 2, 0), "");
- index = LLVMBuildAdd(builder, index,
- ctx->i32_1, "");
+ index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32,
2, 0),
+ ctx->i32_1);
list = LLVMBuildPointerCast(builder, list,
ac_array_in_const32_addr_space(ctx->v4i32), "");
} else {
assert(desc_type == AC_DESC_IMAGE);
}
rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
if (desc_type == AC_DESC_IMAGE && dcc_off)
rsrc = force_dcc_off(ctx, rsrc);
return rsrc;
@@ -981,34 +979,34 @@ LLVMValueRef si_load_sampler_desc(struct
si_shader_context *ctx,
{
LLVMBuilderRef builder = ctx->ac.builder;
switch (type) {
case AC_DESC_IMAGE:
/* The image is at [0:7]. */
index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2,
0), "");
break;
case AC_DESC_BUFFER:
/* The buffer is in [4:7]. */
- index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4,
0), "");
- index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
+ index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32,
4, 0),
+ ctx->i32_1);
list = LLVMBuildPointerCast(builder, list,
ac_array_in_const32_addr_space(ctx->v4i32), "");
break;
case AC_DESC_FMASK:
/* The FMASK is at [8:15]. */
- index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2,
0), "");
- index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
+ index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32,
2, 0),
+ ctx->i32_1);
break;
case AC_DESC_SAMPLER:
/* The sampler state is at [12:15]. */
- index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4,
0), "");
- index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3,
0), "");
+ index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32,
4, 0),
+ LLVMConstInt(ctx->i32, 3, 0));
list = LLVMBuildPointerCast(builder, list,
ac_array_in_const32_addr_space(ctx->v4i32), "");
break;
}
return ac_build_load_to_sgpr(&ctx->ac, list, index);
}
/* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
*
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 975696d07ad..1f37b0ba37d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -245,21 +245,20 @@ get_array_range(struct lp_build_tgsi_context *bld_base,
*/
static LLVMValueRef
get_pointer_into_array(struct si_shader_context *ctx,
unsigned file,
unsigned swizzle,
unsigned reg_index,
const struct tgsi_ind_register *reg_indirect)
{
unsigned array_id;
struct tgsi_array_info *array;
- LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef idxs[2];
LLVMValueRef index;
LLVMValueRef alloca;
if (file != TGSI_FILE_TEMPORARY)
return NULL;
array_id = get_temp_array_id(&ctx->bld_base, reg_index, reg_indirect);
if (!array_id)
return NULL;
@@ -283,29 +282,24 @@ get_pointer_into_array(struct si_shader_context *ctx,
* TODO It should be possible to avoid the additional instructions
* if LLVM is changed so that it guarantuees:
* 1. the scratch space descriptor isolates the current wave (this
* could even save the scratch offset SGPR at the cost of an
* additional SALU instruction)
* 2. the memory for allocas must be allocated at the _end_ of the
* scratch space (after spilled registers)
*/
index = si_llvm_bound_index(ctx, index, array->range.Last -
array->range.First + 1);
- index = LLVMBuildMul(
- builder, index,
- LLVMConstInt(ctx->i32, util_bitcount(array->writemask), 0),
- "");
- index = LLVMBuildAdd(
- builder, index,
- LLVMConstInt(ctx->i32,
- util_bitcount(array->writemask & ((1 << swizzle) -
1)), 0),
- "");
+ index = ac_build_imad(&ctx->ac, index,
+ LLVMConstInt(ctx->i32,
util_bitcount(array->writemask), 0),
+ LLVMConstInt(ctx->i32,
+ util_bitcount(array->writemask & ((1
<< swizzle) - 1)), 0));
idxs[0] = ctx->i32_0;
idxs[1] = index;
return LLVMBuildGEP(ctx->ac.builder, alloca, idxs, 2, "");
}
LLVMValueRef
si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
LLVMTypeRef type,
LLVMValueRef ptr,
LLVMValueRef ptr2)
--
2.17.1
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