Re: [Mesa-dev] [PATCH v2] radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug

2017-09-05 Thread Marek Olšák
On Tue, Sep 5, 2017 at 9:56 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > When the HS wave is empty, the hardware writes the LS VGPRs starting at > v0 instead of v2. Workaround by shifting them back into place when > necessary. For simplicity,

[Mesa-dev] [PATCH v2] radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug

2017-09-05 Thread Nicolai Hähnle
From: Nicolai Hähnle When the HS wave is empty, the hardware writes the LS VGPRs starting at v0 instead of v2. Workaround by shifting them back into place when necessary. For simplicity, this is always done in the LS prolog. According to the hardware team, this will be