Make the algorithm easier to follow. --- src/mesa/drivers/dri/i965/brw_clear.c | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 653abae2d8f..cda47bcabac 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -215,26 +215,7 @@ brw_fast_clear_depth(struct gl_context *ctx) intel_miptree_set_depth_clear_value(brw, mt, clear_value); } - bool need_clear = false; - for (unsigned a = 0; a < num_layers; a++) { - enum isl_aux_state aux_state = - intel_miptree_get_aux_state(mt, depth_irb->mt_level, - depth_irb->mt_layer + a); - - if (aux_state != ISL_AUX_STATE_CLEAR) { - need_clear = true; - break; - } - } - - if (!need_clear) { - /* If all of the layers we intend to clear are already in the clear - * state then simply updating the miptree fast clear value is sufficient - * to change their clear value. - */ - return true; - } - + /* Fast-clear any of the layers that are not already in the clear state. */ for (unsigned a = 0; a < num_layers; a++) { enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, depth_irb->mt_level, @@ -244,16 +225,12 @@ brw_fast_clear_depth(struct gl_context *ctx) intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer + a, 1, ISL_AUX_OP_FAST_CLEAR); + intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level, + depth_irb->mt_layer + a, 1, + ISL_AUX_STATE_CLEAR); } } - /* Now, the HiZ buffer contains data that needs to be resolved to the depth - * buffer. - */ - intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level, - depth_irb->mt_layer, num_layers, - ISL_AUX_STATE_CLEAR); - return true; } -- 2.16.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev