Inspired by what is already in the kernel. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/intel_batchbuffer.c | 13 +++++++++++++ 3 files changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 2613b9fda22..0880d18b6f0 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1410,6 +1410,8 @@ void brw_store_register_mem64(struct brw_context *brw, struct brw_bo *bo, uint32_t reg, uint32_t offset); void brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm); +void brw_load_register_imm32_force_posted(struct brw_context *brw, + uint32_t reg, uint32_t imm); void brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm); void brw_load_register_reg(struct brw_context *brw, uint32_t src, diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 855f1c7d744..320426d6944 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1428,6 +1428,7 @@ enum brw_pixel_shader_coverage_mask_mode { #define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23)) #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23)) +#define MI_LOAD_REGISTER_IMM_FORCE_POSTED (1 << 12) #define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23)) #define MI_FLUSH_DW (CMD_MI | (0x26 << 23)) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index df999ffeb1d..250a8e812e5 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -1192,6 +1192,19 @@ brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) ADVANCE_BATCH(); } +void +brw_load_register_imm32_force_posted(struct brw_context *brw, uint32_t reg, uint32_t imm) +{ + assert(brw->screen->devinfo.gen >= 6); + + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2) | + MI_LOAD_REGISTER_IMM_FORCE_POSTED); + OUT_BATCH(reg); + OUT_BATCH(imm); + ADVANCE_BATCH(); +} + /* * Write a 64-bit register using immediate data. */ -- 2.17.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev