v2: allow for non debug builds as well v3: move reading out env var more global disable tg4 with multiple offsets with nir disable caps for 64 bit types v6: nv50 support disable MS images disable bindless textures
Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/nouveau_screen.c | 5 +++++ src/gallium/drivers/nouveau/nouveau_screen.h | 2 ++ .../drivers/nouveau/nv50/nv50_screen.c | 4 +++- .../drivers/nouveau/nvc0/nvc0_screen.c | 19 +++++++++++++------ 4 files changed, 23 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index c97b707955c..03c1c74160f 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.c +++ b/src/gallium/drivers/nouveau/nouveau_screen.c @@ -176,9 +176,14 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev) union nouveau_bo_config mm_config; char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG"); + char *use_nir = getenv("NV50_PROG_USE_NIR"); + if (nv_dbg) nouveau_mesa_debug = atoi(nv_dbg); + if (use_nir) + screen->prefer_nir = strtol(use_nir, NULL, 0) == 1; + /* These must be set before any failure is possible, as the cleanup * paths assume they're responsible for deleting them. */ diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau/nouveau_screen.h index e4fbae99ca4..1229b66b26f 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.h +++ b/src/gallium/drivers/nouveau/nouveau_screen.h @@ -62,6 +62,8 @@ struct nouveau_screen { struct disk_cache *disk_shader_cache; + bool prefer_nir; + #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS union { uint64_t v[29]; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 24324d7a11e..826c01c238e 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -317,6 +317,8 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader, enum pipe_shader_cap param) { + const struct nouveau_screen *screen = nouveau_screen(pscreen); + switch (shader) { case PIPE_SHADER_VERTEX: case PIPE_SHADER_GEOMETRY: @@ -370,7 +372,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return MIN2(16, PIPE_MAX_SAMPLERS); case PIPE_SHADER_CAP_PREFERRED_IR: - return PIPE_SHADER_IR_TGSI; + return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index b32a129c7e2..70c8a6ffbf4 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -87,9 +87,11 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen, if (bindings & PIPE_BIND_SHADER_IMAGE) { if (sample_count > 0 && - nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) { + (nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS || + nouveau_screen(pscreen)->prefer_nir)) { /* MS images are currently unsupported on Maxwell because they have to * be handled explicitly. */ + /* MS images are currently unsupported with NIR */ return false; } @@ -109,7 +111,8 @@ static int nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) { const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; - struct nouveau_device *dev = nouveau_screen(pscreen)->device; + const struct nouveau_screen *screen = nouveau_screen(pscreen); + struct nouveau_device *dev = screen->device; switch (param) { /* non-boolean caps */ @@ -217,7 +220,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: - case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: @@ -258,6 +260,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: case PIPE_CAP_QUERY_SO_OVERFLOW: return 1; + case PIPE_CAP_TEXTURE_GATHER_OFFSETS: + /* TODO: nir doesn't support tg4 with multiple offsets */ + return screen->prefer_nir ? 0 : 1; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0; case PIPE_CAP_TGSI_FS_FBFETCH: @@ -275,8 +280,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return class_3d >= GP100_3D_CLASS; case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_BALLOT: - case PIPE_CAP_BINDLESS_TEXTURE: return class_3d >= NVE4_3D_CLASS; + case PIPE_CAP_BINDLESS_TEXTURE: + return class_3d >= NVE4_3D_CLASS && !screen->prefer_nir; /* unsupported caps */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -347,7 +353,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader, enum pipe_shader_cap param) { - const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; + const struct nouveau_screen *screen = nouveau_screen(pscreen); + const uint16_t class_3d = screen->class_3d; switch (shader) { case PIPE_SHADER_VERTEX: @@ -363,7 +370,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, switch (param) { case PIPE_SHADER_CAP_PREFERRED_IR: - return PIPE_SHADER_IR_TGSI; + return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 1 << PIPE_SHADER_IR_TGSI | 1 << PIPE_SHADER_IR_NIR; -- 2.17.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev