Currently the status bits for fast clear include the flag telling if non-multisampled mcs buffer should be used at all. Once the state tracking is changed to follow individual levels/layers one still needs to have the mcs enabling information in the miptree. Therefore simply split it out to its own boolean.
Possible follow-up work is to combine disable_aux_buffers and no_ccs into single enum. v2 (Jason): Changed no_msrt_mcs to no_ccs and updated comment Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 +++++++++++-------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12 ++++++------ 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 99df21e..afb17d5 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -808,7 +808,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable)) can_fast_clear = false; - if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS || + if (irb->mt->no_ccs || !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor)) can_fast_clear = false; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 8482afe..5d35016 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -397,8 +397,9 @@ intel_miptree_create_layout(struct brw_context *brw, mt->logical_width0 = width0; mt->logical_height0 = height0; mt->logical_depth0 = depth0; - mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS; + mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; mt->disable_aux_buffers = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0; + mt->no_ccs = true; mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0; exec_list_make_empty(&mt->hiz_map); mt->cpp = _mesa_get_format_bytes(format); @@ -810,7 +811,7 @@ intel_miptree_create(struct brw_context *brw, */ if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) && intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { - mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; + mt->no_ccs = false; assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1); /* On Gen9+ clients are not currently capable of consuming compressed @@ -1645,6 +1646,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, { assert(mt->mcs_buf == NULL); assert(!mt->disable_aux_buffers); + assert(!mt->no_ccs); /* The format of the MCS buffer is opaque to the driver; all that matters * is that we get its size and pitch right. We'll pretend that the format @@ -2230,6 +2232,9 @@ intel_miptree_resolve_color(struct brw_context *brw, unsigned level, unsigned layer, int flags) { + if (mt->no_ccs) + return false; + intel_miptree_check_color_resolve(mt, level, layer); /* From gen9 onwards there is new compression scheme for single sampled @@ -2241,7 +2246,6 @@ intel_miptree_resolve_color(struct brw_context *brw, return false; switch (mt->fast_clear_state) { - case INTEL_FAST_CLEAR_STATE_NO_MCS: case INTEL_FAST_CLEAR_STATE_RESOLVED: /* No resolve needed */ return false; @@ -2273,9 +2277,8 @@ intel_miptree_all_slices_resolve_color(struct brw_context *brw, * process or another miptree. * * Fast color clears are unsafe with shared buffers, so we need to resolve and - * then discard the MCS buffer, if present. We also set the fast_clear_state - * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets - * allocated in the future. + * then discard the MCS buffer, if present. We also set the no_ccs flag to + * ensure that no MCS buffer gets allocated in the future. */ void intel_miptree_make_shareable(struct brw_context *brw, @@ -2290,7 +2293,7 @@ intel_miptree_make_shareable(struct brw_context *brw, if (mt->mcs_buf) { intel_miptree_all_slices_resolve_color(brw, mt, 0); - mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS; + mt->no_ccs = true; } } @@ -3372,7 +3375,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw, } else if (intel_miptree_is_lossless_compressed(brw, mt)) { assert(brw->gen >= 9); *usage = ISL_AUX_USAGE_CCS_E; - } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) { + } else if (!mt->no_ccs) { *usage = ISL_AUX_USAGE_CCS_D; } else { unreachable("Invalid MCS miptree"); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 95d9dad..b8cf0c3 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -220,12 +220,6 @@ enum intel_msaa_layout enum intel_fast_clear_state { /** - * There is no MCS buffer for this miptree, and one should never be - * allocated. - */ - INTEL_FAST_CLEAR_STATE_NO_MCS, - - /** * No deferred clears are pending for this miptree, and the contents of the * color buffer are entirely correct. An MCS buffer may or may not exist * for this miptree. If it does exist, it is entirely in the "no deferred @@ -703,6 +697,12 @@ struct intel_mipmap_tree bool disable_aux_buffers; /** + * Fast clear and lossless compression are always disabled for this + * miptree. + */ + bool no_ccs; + + /** * Tells if the underlying buffer is to be also consumed by entities other * than the driver. This allows logic to turn off features such as lossless * compression which is not currently understood by client applications. -- 2.5.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev