Hi everybody!
I'm currently working with the GLU tesselator and I need the ability to
abort a tesselation process at any state, as fast as possible (so
calling gluTessEndPolygon is not an option). Additionally i would like
to be able to re-use the GLUtesselator object afterwards.
Is the
Currently not supported by any driver implementation; this only adds the
API framework.
Signed-off-by: Oliver McFadden oliver.mcfad...@linux.intel.com
---
src/mesa/main/APIspec.xml |7 +++
src/mesa/main/extensions.c |1 +
src/mesa/main/glheader.h |5 +
On Die, 2012-05-22 at 13:32 +0800, Homer Hsing wrote:
I have a newbie question when tracing a bug in MESA.
After __glXFlushRenderBuffer calling xcb_glx_render, which code
will do drawing commands in ctx-buf ?
Reference: in MESA src/glx/glxext.c,
GLubyte *
Looks good to me.
Jose
- Original Message -
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/SConscript |2 +-
src/gallium/SConscript |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index
[ Please don't top-post ]
On Die, 2012-05-22 at 16:55 +0800, Homer Hsing wrote:
Thanks :) Btw, is the code executing the drawing commands also in
MESA? If it is, which files are they in? If not, where can I find the
code executing the drawing commands?
See xserver/glx/, though eventually
just a observation below,
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index efa63b0..376e62f 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -61,6 +61,8 @@
#define FIXED_GL_BIT 0x800
#define UNSIGNED_INT_2_10_10_10_REV_BIT 0x1000
#define
On Tue, May 22, 2012 at 10:02:59AM +0100, Dave Airlie wrote:
just a observation below,
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index efa63b0..376e62f 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -61,6 +61,8 @@
#define FIXED_GL_BIT
Fixes crash bug introduced with 210ddf0819b5 fd.o #49198
pthread_detach after a pthread_join is unneeded.
Signed-off-by: Maarten Lankhorst m.b.lankho...@gmail.com
---
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index
On 05/22/2012 03:52 AM, Oliver McFadden wrote:
On Tue, May 22, 2012 at 10:02:59AM +0100, Dave Airlie wrote:
just a observation below,
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index efa63b0..376e62f 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -61,6
On 05/22/2012 01:26 AM, Lukas Rössler wrote:
Hi everybody!
I'm currently working with the GLU tesselator and I need the ability
to abort a tesselation process at any state, as fast as possible (so
calling gluTessEndPolygon is not an option). Additionally i would like
to be able to re-use the
On 21 May 2012 22:01, Olivier Galibert galib...@pobox.com wrote:
On Mon, May 21, 2012 at 07:16:35PM -0700, Paul Berry wrote:
- Add the front-end API to allow the client to request per-sample shading
(I assume it's glEnable(GL_HAM_SANDWICH) or something like that, in which
case it should be
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16 +
src/gallium/state_trackers/dri/common/dri_screen.c | 23 +++
src/gallium/state_trackers/vega/vg_manager.c |1 +
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16 +
src/gallium/state_trackers/dri/common/dri_screen.c | 23
+++
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16 +
src/gallium/state_trackers/dri/common/dri_screen.c | 23
+++
On 22.05.12 15:40, Brian Paul wrote:
On 05/22/2012 01:26 AM, Lukas Rössler wrote:
Hi everybody!
I'm currently working with the GLU tesselator and I need the ability
to abort a tesselation process at any state, as fast as possible (so
calling gluTessEndPolygon is not an option). Additionally i
On 05/11/2012 11:03 AM, Paul Berry wrote:
On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA
surface could be accomplished with a single texturing operation. On
Gen7, the WM program must fetch each sample and blend them together
manually. This patch implements the manual
From: José Fonseca jfons...@vmware.com
This is a long standing problem, that recently surfaced with the change
to enable perspective correct color interpolation.
A fix for all possible formats is left to the future.
---
src/gallium/drivers/llvmpipe/lp_bld_alpha.c | 31
On 22 May 2012 08:04, Kenneth Graunke kenn...@whitecape.org wrote:
On 05/11/2012 11:03 AM, Paul Berry wrote:
On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA
surface could be accomplished with a single texturing operation. On
Gen7, the WM program must fetch each sample
On 05/11/2012 11:03 AM, Paul Berry wrote:
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for
On 05/22/2012 09:07 AM, jfons...@vmware.com wrote:
From: José Fonsecajfons...@vmware.com
This is a long standing problem, that recently surfaced with the change
to enable perspective correct color interpolation.
A fix for all possible formats is left to the future.
---
Am 22.05.2012 17:07, schrieb jfons...@vmware.com:
From: José Fonseca jfons...@vmware.com
This is a long standing problem, that recently surfaced with the change
to enable perspective correct color interpolation.
A fix for all possible formats is left to the future.
---
On 05/22/2012 08:37 AM, Christoph Bumiller wrote:
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16 +
src/gallium/state_trackers/dri/common/dri_screen.c | 23
On 05/22/2012 09:58 AM, Brian Paul wrote:
On 05/22/2012 08:37 AM, Christoph Bumiller wrote:
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16 +
On 05/22/2012 05:58 PM, Brian Paul wrote:
On 05/22/2012 08:37 AM, Christoph Bumiller wrote:
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h | 16
+
On 22 May 2012 08:19, Kenneth Graunke kenn...@whitecape.org wrote:
On 05/11/2012 11:03 AM, Paul Berry wrote:
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface.
- Original Message -
On 05/22/2012 09:07 AM, jfons...@vmware.com wrote:
From: José Fonsecajfons...@vmware.com
This is a long standing problem, that recently surfaced with the
change
to enable perspective correct color interpolation.
A fix for all possible formats is left
On 05/21/2012 07:16 PM, Paul Berry wrote:
On 21 May 2012 18:00, Ian Romanick i...@freedesktop.org
mailto:i...@freedesktop.org wrote:
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch modifies the blorp WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means
I finally got around to fixing my fast depth clear hack, and it turns
out it's a good payoff. Here's the summary:
Improves citybench high-res performance 3.0% +- 0.4%, n=10.
Improves Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78).
No significant difference on openarena (n=5,
---
src/mesa/drivers/dri/i965/brw_clear.c | 28 ++--
1 file changed, 2 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 604a680..6761e34 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
---
src/mesa/drivers/dri/i965/brw_clear.c |5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3316351..604a680 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++
---
src/mesa/drivers/dri/i915/intel_clear.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_clear.c
b/src/mesa/drivers/dri/i915/intel_clear.c
index 3316351..96d9c8f 100644
--- a/src/mesa/drivers/dri/i915/intel_clear.c
+++
This logic is wasted on i965 when we want to just always do GLSL tri
clears.
---
src/mesa/drivers/dri/i915/intel_clear.c| 204 +++-
src/mesa/drivers/dri/i965/Makefile.sources |2 +-
src/mesa/drivers/dri/i965/brw_clear.c | 203 +++
Our understanding is that the 3D engine is supposed to be faster
anyway. We used to have more overhead in our tri clear path than we
do today, which would have led to this choice. But given that we
almost always see a depth clear along with a color clear, the path was
hardly exercised anyway.
The GLSL clear path doesn't need any buffer presence checks, since
those are already handled in the normal drawing path code.
---
src/mesa/drivers/dri/i965/brw_clear.c | 58 +++--
1 file changed, 11 insertions(+), 47 deletions(-)
diff --git
---
src/mesa/drivers/dri/i965/brw_clear.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 84ea990..d171b7c 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++
This required moving gen6_hiz_op, and I put it in intel_resolve_map.h
for the next commit.
---
src/mesa/drivers/dri/i965/brw_blorp.cpp| 11 +++
src/mesa/drivers/dri/i965/brw_blorp.h | 16 +---
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 15
When doing fast clears, a fulsim warning said that the batch was being
emitted without the viewport set up. This could potentially have been
a problem if some other app set the viewport to a range other than the
[0,1] we want.
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 21
Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves
Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No
significant difference on openarena (n=5, didn't fast clear) or nexuiz
(n=3).
---
src/mesa/drivers/dri/i965/brw_blorp.cpp|1 -
---
src/mesa/drivers/dri/i965/brw_vtbl.c | 12 --
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 21 --
src/mesa/drivers/dri/i965/gen6_blorp.h | 12 --
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 22 ---
On 05/11/2012 11:03 AM, Paul Berry wrote:
On Gen7, push constants for shader programs are stored in the URB, so
blorp code needs to set aside space for them. This was previously
unnecessary because blorp code was based on HiZ operations, which
don't require any shaders.
This patch adds a call
Hi,
Here is an updated version of the compute patches for r600g. Patches 1, 9,
and 10 have been changed since v1 and patches 3 and 4 are new.
-Tom
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
v2:
- Drop HAVE_OPENCL variable for non-automake builds
- s/HAVE_OPENCL/HAVE_GALLIUM_COMPUTE
---
configure.ac |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/configure.ac b/configure.ac
index 3bb51a2..2805e7c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2072,6
---
src/gallium/include/pipe/p_defines.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index ad7f24e..5857c4f 100644
--- a/src/gallium/include/pipe/p_defines.h
+++
---
src/gallium/auxiliary/util/u_inlines.h | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_inlines.h
b/src/gallium/auxiliary/util/u_inlines.h
index 2ec153c..b647c8b 100644
--- a/src/gallium/auxiliary/util/u_inlines.h
+++
A device now has two function for getting information about the IR
it needs to return.
ir_target() = returns the preferred IR
llvm_triple() = returns the triple for the target that is understood by
clang/llvm.
---
src/gallium/state_trackers/clover/core/device.cpp | 19
---
configs/autoconf.in |3 +++
configure.ac|8
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/configs/autoconf.in b/configs/autoconf.in
index 3c8f4c1..a705236 100644
--- a/configs/autoconf.in
+++ b/configs/autoconf.in
@@ -187,6 +187,9 @@
---
configs/autoconf.in |2 ++
configure.ac|4
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/configs/autoconf.in b/configs/autoconf.in
index a705236..51024d5 100644
--- a/configs/autoconf.in
+++ b/configs/autoconf.in
@@ -34,8 +34,10 @@ X11_LIBS = @X11_LIBS@
---
configure.ac |3 +++
src/gallium/targets/opencl/Makefile.am | 18 +-
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/configure.ac b/configure.ac
index 9c7f54b..c4c9eca 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1846,6
$(LLVM_CFLAGS) for LLVM defines
-DLIBCLC_PATH for libclc path
-DCLANG_RESOURCE_DIR for clang includes
$(DEFINES) for -DHAVE_LLVM
---
src/gallium/state_trackers/clover/Makefile.am |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git
This is for the llvm code that can't use extended initializers.
v2:
- Use const references for vector arguments
- Move constructor defs before data members
- Initialize all values in the default constructors
---
src/gallium/state_trackers/clover/core/module.hpp | 13 +
1
v2:
-Separate IR type and LLVM triple
-Do the OpenCL C-LLVM IR and linking steps for all PIPE_SHADER_IR
types.
---
There really isn't much functional change in this patch from v1, the only
really difference is that the decision to emit LLVM or native machine code
is made after the linking
On 05/11/2012 11:03 AM, Paul Berry wrote:
On Gen6, texel fetch is always accomplished using the SAMPLE_LD
message, which accepts arguments (u, v, r, lod, si). On Gen7, there
are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking
arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA
On Mon, 21 May 2012 20:36:52 +0200, Sven Joachim svenj...@gmx.de wrote:
On 2012-05-17 17:17 +0200, Sven Joachim wrote:
On 2012-05-17 15:58 +0200, Brian Paul wrote:
On 05/17/2012 04:42 AM, Sven Joachim wrote:
Hi,
Commit 63720114b42 in mesa removed the GLw source which is now provided
On 05/11/2012 11:03 AM, Paul Berry wrote:
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch series provides preliminary support for MSAA (multisample
antialiasing) in i965/gen7. It depends on my previous MSAA patch
series [PATCH v2 0/5] i965/gen6: Begin implementing MSAA.
The patches can be grouped into 3 sets:
Patch 01 fixes a
On 22 May 2012 10:15, Ian Romanick i...@freedesktop.org wrote:
On 05/21/2012 07:16 PM, Paul Berry wrote:
On 21 May 2012 18:00, Ian Romanick i...@freedesktop.org
mailto:i...@freedesktop.org wrote:
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch modifies the blorp WM program
On 05/14/2012 03:47 PM, Paul Berry wrote:
This patch implements clipping and scissoring of the destination rect
for blits that use the blorp engine (e.g. MSAA blits).
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 72 --
1 files changed, 67 insertions(+), 5
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch separates out the portions of gen6_blorp_emit_batch_head()
that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
STATE_BASE_ADDRESS. This paves the way for making the blorp code work
on Gen7,
On 05/19/2012 10:08 AM, Paul Berry wrote:
When considering which components of a variable were killed by an
assignment, constant propagation would previously just use the write
mask of the assignment. This worked if the LHS of the assignment was
simple, e.g.:
v.xy = ...; // (assign (xy)
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/11/2012 11:03 AM, Paul Berry wrote:
On Gen7, push constants for shader programs are stored in the URB, so
blorp code needs to set aside space for them. This was previously
unnecessary because blorp code was based on HiZ operations, which
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch separates out the portions of gen6_blorp_emit_batch_head()
that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
STATE_BASE_ADDRESS. This paves the way for making the blorp code work
on Gen7, where additional command packets
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch modifies the blorp WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means that every single sample of a
multisampled render target is dispatched to the WM program, not just
every pixel).
Previously we were using the ugly hack
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/11/2012 11:03 AM, Paul Berry wrote:
When executing a blorp operation on Gen7 that does not need a WM
program (i.e. a HiZ operation), we use 32-pixel dispatch mode because
it's faster. However, when executing a blorp operation that does need
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/11/2012 11:03 AM, Paul Berry wrote:
Gen7 support for blorp (blits using the render bath) now works for
non-MSAA purposes. This patch enables it.
Since blorp operations re-use the logic for HiZ ops, this required
adding a case to the
On 05/11/2012 11:03 AM, Paul Berry wrote:
---
src/mesa/drivers/dri/i965/brw_defines.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index a087f70..4ad905b 100644
---
On 05/22/2012 12:55 AM, Oliver McFadden wrote:
Currently not supported by any driver implementation; this only adds the
API framework.
Signed-off-by: Oliver McFaddenoliver.mcfad...@linux.intel.com
Other than the (mostly pre-existing) error mentioned below and the minor
nit,
Reviewed-by:
On 05/11/2012 11:03 AM, Paul Berry wrote:
Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
allocate an integer number of 2x2 blocks; if we
I don't think you meant always use have in the commit message. :)
On 05/22/2012 10:21 AM, Eric Anholt wrote:
---
src/mesa/drivers/dri/i965/brw_clear.c |5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
[PATCH 01/15] i965/msaa: Expand odd-sized MSAA surfaces to account for
interleaving pattern.
Acked-by: Kenneth Graunke kenn...@whitecape.org
[PATCH 02/15] i965/blorp: Generalize sampling code in preparation for Gen7
[PATCH 03/15] i965/blorp: Emit sample index in SAMPLE_LD message when
s/vieport/viewport/ in the commit message,
Does GEN6 need similar treatment?
On 05/22/2012 10:21 AM, Eric Anholt wrote:
When doing fast clears, a fulsim warning said that the batch was being
emitted without the viewport set up. This could potentially have been
a problem if some other app set
On 05/22/2012 10:21 AM, Eric Anholt wrote:
I finally got around to fixing my fast depth clear hack, and it turns
out it's a good payoff. Here's the summary:
Improves citybench high-res performance 3.0% +- 0.4%, n=10.
Improves Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78).
On Fri, 11 May 2012 11:03:44 -0700, Paul Berry stereotype...@gmail.com wrote:
Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
allocate an
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/11/2012 11:03 AM, Paul Berry wrote:
Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
On 05/18/2012 08:00 PM, Eric Anholt wrote:
The i965 driver needed this as well for hardware setup, so instead of
duplicating the logic, just save it off.
This patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
I'll have to take your word for it on the other one. :)
---
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/22/2012 10:21 AM, Eric Anholt wrote:
When doing fast clears, a fulsim warning said that the batch was being
emitted without the viewport set up. This could potentially have been
a problem if some other app set the viewport to a range other
On Fri, 11 May 2012 11:03:50 -0700, Paul Berry stereotype...@gmail.com wrote:
When executing a blorp operation on Gen7 that does not need a WM
program (i.e. a HiZ operation), we use 32-pixel dispatch mode because
it's faster. However, when executing a blorp operation that does need
a WM
On Tue, May 22, 2012 at 11:38 AM, Eric Anholt e...@anholt.net wrote:
On Mon, 21 May 2012 20:36:52 +0200, Sven Joachim svenj...@gmx.de wrote:
On 2012-05-17 17:17 +0200, Sven Joachim wrote:
On 2012-05-17 15:58 +0200, Brian Paul wrote:
On 05/17/2012 04:42 AM, Sven Joachim wrote:
Hi,
Am 22.05.2012 18:12, schrieb Christoph Bumiller:
On 05/22/2012 05:58 PM, Brian Paul wrote:
On 05/22/2012 08:37 AM, Christoph Bumiller wrote:
On 05/22/2012 04:23 PM, Brian Paul wrote:
On 05/21/2012 03:46 PM, Christoph Bumiller wrote:
---
src/gallium/include/state_tracker/st_api.h |
On 2012-05-22 22:30 +0200, Brian Paul wrote:
On Tue, May 22, 2012 at 11:38 AM, Eric Anholt e...@anholt.net wrote:
Yeah, revving versions of split out packages back to 1.0 is a minor pain
for every distro, and is good to avoid.
I'm fine with bumping the version to 8.0.0. But I took a quick
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
configure.ac |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index da4d445..3f49773 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
dnl Process this file with autoconf to
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/22/2012 10:21 AM, Eric Anholt wrote:
I finally got around to fixing my fast depth clear hack, and it turns
out it's a good payoff. Here's the summary:
Improves citybench high-res performance 3.0% +- 0.4%, n=10.
Improves Lightsmark
From: Ian Romanick ian.d.roman...@intel.com
These look like debug messages from the switch-statement development.
NOTE: This is a candidate for the 8.0 release branch.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/ast_to_hir.cpp |3 ---
1 files changed, 0 insertions(+),
On 05/22/2012 03:13 PM, Sven Joachim wrote:
On 2012-05-22 22:30 +0200, Brian Paul wrote:
On Tue, May 22, 2012 at 11:38 AM, Eric Anholte...@anholt.net wrote:
Yeah, revving versions of split out packages back to 1.0 is a minor pain
for every distro, and is good to avoid.
I'm fine with
On Sat, 19 May 2012 10:08:20 -0700, Paul Berry stereotype...@gmail.com wrote:
When considering which components of a variable were killed by an
assignment, constant propagation would previously just use the write
mask of the assignment. This worked if the LHS of the assignment was
simple,
OK, the 8.0.0 version is at ftp://ftp.freedesktop.org/pub/mesa/glw/
-Brian
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 05/13/2012 12:48 AM, Vinson Lee wrote:
Fix uninitialized scalar field defect reported by Coverity.
Signed-off-by: Vinson Leev...@freedesktop.org
---
src/glsl/lower_vector.cpp |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/lower_vector.cpp
https://bugs.freedesktop.org/show_bug.cgi?id=49830
Robert Hooker (Sarvatt) sarv...@gmail.com changed:
What|Removed |Added
CC|
On Tue, 22 May 2012 10:55:36 +0300, Oliver McFadden
oliver.mcfad...@linux.intel.com wrote:
Currently not supported by any driver implementation; this only adds the
API framework.
I'd like to see a driver implementation and some tests with this series.
pgpctMnW384wp.pgp
Description: PGP
On 22 May 2012 12:12, Eric Anholt e...@anholt.net wrote:
On Fri, 11 May 2012 11:03:44 -0700, Paul Berry stereotype...@gmail.com
wrote:
Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when
On 22 May 2012 11:31, Kenneth Graunke kenn...@whitecape.org wrote:
On 05/11/2012 11:03 AM, Paul Berry wrote:
This patch modifies the blorp WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means that every single sample of a
multisampled render target is dispatched to the WM
On Mon, 14 May 2012 15:47:35 -0700, Paul Berry stereotype...@gmail.com wrote:
This patch implements clipping and scissoring of the destination rect
for blits that use the blorp engine (e.g. MSAA blits).
There's _mesa_clip_blit() used in swrast and state_tracker, which looks
like we should be
91 matches
Mail list logo
