[Mesa-dev] [PATCH 04/10] i965: Port tessellation evaluation shaders to vec4 mode.

This can be used on Broadwell by setting INTEL_SCALAR_TES=0. More importantly, it will be used for Ivybridge and Haswell. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_defines.h|

[Mesa-dev] [PATCH 0/10] Tessellation shaders for Gen7/7.5.

This morning, I woke up and somehow "knew" what was causing my HS GPU hangs on Gen7/7.5. It turns out I was (completely) wrong, but through some miraculous series of illogical leaps, I arrived at a solution anyway. I don't honestly know how I got it working on Christmas Eve after failing to

[Mesa-dev] [PATCH 08/10] i965: Don't set interleave or complete on TCS EOT message.

Setting interleave on the TCS EOT message causes Ivybridge hardware to GPU hang like crazy. Individual tests would pass, but running even a simple test like nop.shader_test in a loop would hang within 1-3 runs. Adding sleep delays worked around the problem, somehow. Interleave doesn't make much

[Mesa-dev] [PATCH 09/10] i965: Enable ARB_tessellation_shader on Gen7-7.5.

We've resolved all the GPU hangs, and everything seems to be working. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.c | 4 ++-- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff

[Mesa-dev] [PATCH 06/10] i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.

Gen7 uses bits 15:12 while Gen7+ uses bits 16:13. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp

[Mesa-dev] [PATCH 10/10] docs: Mark ARB_tessellation_shader as done on all i965 platforms.

We now support all Intel GPUs which can do tessellation. --- docs/GL3.txt | 2 +- docs/relnotes/11.2.0.html | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 58aace9..f12e0ba 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -112,7

[Mesa-dev] [PATCH 07/10] i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.

Pre-Broadwell hardware requires us to manually release the ICP Handles by issuing URB read messages with the "Complete" bit set. We can do this in pairs to use fewer URB read messages. Based heavily on work from Chris Forbes. Signed-off-by: Kenneth Graunke ---

[Mesa-dev] [PATCH 03/10] i965: Emit a real 3DSTATE_DS on Gen7.

--- src/mesa/drivers/dri/i965/gen7_ds_state.c | 65 +-- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c index 2b743f6..30deabb 100644 ---

[Mesa-dev] [PATCH 05/10] i965: Use proper TCS Instance ID bits for Ivybridge/Baytrail.

Gen7 uses 22:16 while Gen7.5+ uses 23:17. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp

[Mesa-dev] [PATCH 01/10] i965: Add the TCS/TES state upload atoms to the gen7_atoms list.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state_upload.c | 14 ++ src/mesa/drivers/dri/i965/gen7_ds_state.c| 15 --- src/mesa/drivers/dri/i965/gen7_hs_state.c| 15 --- 3 files changed, 14 insertions(+), 30

[Mesa-dev] [PATCH 02/10] i965: Emit a real 3DSTATE_HS on Gen7.

--- src/mesa/drivers/dri/i965/gen7_hs_state.c | 58 +-- 1 file changed, 47 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_hs_state.c b/src/mesa/drivers/dri/i965/gen7_hs_state.c index d23a4f8..0e2b3b2 100644 ---

[Mesa-dev] [PATCH] meta: Fix the pbo usage in meta for GLES{1, 2} contexts

OpenGL ES 1.0 doesn't support using GL_STREAM_DRAW and both ES 1.0 and 2.0 don't support GL_STREAM_READ in glBufferData(). So, handle it correctly by calling the _mesa_meta_begin() before create_texture_for_pbo(). Cc: "11.1" Signed-off-by: Anuj Phogat

Re: [Mesa-dev] [PATCH 0/10] Tessellation shaders for Gen7/7.5.

On Thu, Dec 24, 2015 at 8:34 PM, Kenneth Graunke wrote: > This morning, I woke up and somehow "knew" what was causing my HS GPU hangs > on Gen7/7.5. It turns out I was (completely) wrong, but through some > miraculous series of illogical leaps, I arrived at a solution

Re: [Mesa-dev] [PATCH 0/10] Tessellation shaders for Gen7/7.5.

Ken, That's great news, that hang was quite the head scratcher. - Chris On 25 Dec 2015 14:34, "Kenneth Graunke" wrote: > This morning, I woke up and somehow "knew" what was causing my HS GPU hangs > on Gen7/7.5. It turns out I was (completely) wrong, but through some >

Re: [Mesa-dev] [PATCH 0/10] Tessellation shaders for Gen7/7.5.

Reviewed-by: Edward O'Callaghan Congrats on getting this working, also thanks! On 2015-12-25 12:34, Kenneth Graunke wrote: This morning, I woke up and somehow "knew" what was causing my HS GPU hangs on Gen7/7.5. It turns out I was (completely) wrong, but

[Mesa-dev] [PATCH] gallium/dri2: Avoid uneeded stride to pitch conversion

In order to convert from stride to pitch, few functions were diving by 4 the stride. This is not valid for RGB565 and this conversion was not needed anyway in this context. Signed-off-by: Nicolas Dufresne --- src/gallium/state_trackers/dri/dri2.c | 33

Re: [Mesa-dev] [PATCH] gallium/radeon: add a flag that forces VRAM placement for everything

On 22.12.2015 20:38, Marek Olšák wrote: > On Tue, Dec 22, 2015 at 4:57 AM, Michel Dänzer wrote: >> On 22.12.2015 07:36, Marek Olšák wrote: >>> >>> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c >>> b/src/gallium/drivers/radeon/r600_buffer_common.c >>> index

Re: [Mesa-dev] [PATCH] st/va: count number of slices

On 23 December 2015 at 09:42, Christian König wrote: > On 23.12.2015 10:28, Julien Isorce wrote: > >> The counter was not set but used by the driver. >> It is required otherwise visual output is garbage. >> >> Signed-off-by: Julien Isorce >> > >