Re: [Mesa-dev] [PATCH 08/10] i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.

On Thursday, May 3, 2018 11:49:51 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:38) > > We'd like to start using soft-pin to assign BO addresses up front, and > > never move them again. Our previous plan for dealing with 48-bit VF > > cache bugs was to relocate vertex

Re: [Mesa-dev] [PATCH 08/10] i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.

Quoting Kenneth Graunke (2018-05-04 09:06:49) > On Thursday, May 3, 2018 11:49:51 PM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-05-04 02:12:38) > > > We'd like to start using soft-pin to assign BO addresses up front, and > > > never move them again. Our previous plan for dealing

[Mesa-dev] [Bug 106400] [CI][SNB] glsl-1.40 and 1.50 texturesize / geometry tests failing

https://bugs.freedesktop.org/show_bug.cgi?id=106400 Bug ID: 106400 Summary: [CI][SNB] glsl-1.40 and 1.50 texturesize / geometry tests failing Product: Mesa Version: 18.0 Hardware: x86-64 (AMD64) OS: Linux

[Mesa-dev] [Bug 106400] [CI][SNB] glsl-1.40 and 1.50 texturesize / geometry tests failing

https://bugs.freedesktop.org/show_bug.cgi?id=106400 --- Comment #1 from Kenneth Graunke --- Yes, those are known failures on Sandybridge. We mark those as expected failures in the Mesa CI: https://github.com/janesma/mesa_jenkins/blob/master/piglit-test/snb.conf The

Re: [Mesa-dev] [PATCH] radeon/vcn: fix mpeg4 msg buffer settings

Am 03.05.2018 um 23:29 schrieb boyuan.zh...@amd.com: From: Boyuan Zhang Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Cc: 18.0 18.1

[Mesa-dev] [PATCH 05/10] i965: perf: add PMA stall metrics

These are new metrics for Gen8/9 to measure the effect of the PMA stall workaround fix. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 203 +++- src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 113 ++-

[Mesa-dev] [PATCH 02/10] i965: perf: sklgt2: drop special programming for pre-production stepping

Production steppings don't need this anymore. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml

[Mesa-dev] [PATCH 08/10] i965: perf: sklgt2: drop programming of an unused NOA mux

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml b/src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml index

[Mesa-dev] [PATCH 10/10] i965: perf: enable Icelake metrics

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/Makefile.sources| 3 ++- src/mesa/drivers/dri/i965/brw_performance_query.c | 10 -- src/mesa/drivers/dri/i965/meson.build | 1 + 3 files changed, 11 insertions(+), 3

[Mesa-dev] [PATCH 00/10] i965: perf: config updates

Hi, This series add & update a bunch of metrics to measure performance. There are 3 main things : - SKL GT2 had a few special cases for pre-production hardware that we can remove. - We get a new PMA stall metric for Gen8/9 - We add Icelake support And also a few minor cleanups.

[Mesa-dev] [PATCH 04/10] i965: perf: sklgt2: Add FF Bottlenecks metric

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 500 +++- 1 file changed, 499 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml b/src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml

[Mesa-dev] [PATCH 06/10] i965: perf: chv: fixup counters names

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_chv.xml | 50 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_chv.xml b/src/mesa/drivers/dri/i965/brw_oa_chv.xml index

[Mesa-dev] [PATCH 03/10] i965: perf: sklgt2: update memory write config

This is another pre-production stepping case going away. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 56 ++--- 1 file changed, 49 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 01/10] i965: perf: sklgt2: update a priority for register programming

This makes no difference in term of programming, it's just a cleanup. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 07/10] i965: perf: drop register programming not needed on HSW

This register is flagged as IVB only in the documentation. Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_oa_hsw.xml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_hsw.xml

Re: [Mesa-dev] [PATCH v2 08/14] mesa: handle OES_texture_half_float formats in _mesa_base_tex_format()

Hi > On 05/01/2018 05:48 PM, Christian Gmeiner wrote: > > Signed-off-by: Christian Gmeiner > > Reviewed-by: Wladimir J. van der Laan > > --- > > src/mesa/main/glformats.c | 19 +++ > > 1 file changed, 19 insertions(+) > > > >

Re: [Mesa-dev] [PATCH v2 00/18] anv: add shaderInt16 support

On Thu, 2018-05-03 at 11:44 -0700, Clayton Craft wrote: > Quoting Iago Toral Quiroga (2018-04-30 07:18:08) > > This version addresses the feedback received to v1, which includes > > moving the > > bit-size lowering pass from intel to core NIR (patch 8) and a > > separate patch > > to add Intel's

Re: [Mesa-dev] [PATCH 08/10] i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.

Quoting Kenneth Graunke (2018-05-04 02:12:38) > We'd like to start using soft-pin to assign BO addresses up front, and > never move them again. Our previous plan for dealing with 48-bit VF > cache bugs was to relocate vertex buffers to the low 4GB, so we'd never > have addresses that alias in the

Re: [Mesa-dev] [PATCH 0/9] anv: softpin

Quoting Scott D Phillips (2018-05-02 17:01:00) > This series teaches anv how to pick its own virtual graphics addresses > instead of using the relocation facility provided by the kernel. > > Jason Ekstrand (1): > util: Add a virtual memory allocator > > Scott D Phillips (8): > util/set: add

Re: [Mesa-dev] [PATCH 09/10] i965: Softpin all buffers and never use relocations.

Quoting Kenneth Graunke (2018-05-04 02:12:39) > --- > src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > This enables it for Broadwell (with a 64-bit kernel) and Skylake+ (with > any kernel). Unfortunately, it doesn't enable it for Cherryview as

Re: [Mesa-dev] [PATCH 0/9] anv: softpin

On Thu, May 3, 2018 at 11:24 PM, Chris Wilson wrote: > Quoting Scott D Phillips (2018-05-02 17:01:00) > > This series teaches anv how to pick its own virtual graphics addresses > > instead of using the relocation facility provided by the kernel. > > > > Jason Ekstrand

Re: [Mesa-dev] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

Hi Nanley; On 05/03/2018 10:03 PM, Nanley Chery wrote: Before this patch, if we failed to initialize an MCS buffer, we'd end up in a state in which the miptree thinks it has an MCS buffer, but doesn't. We also leaked the clear_color_bo if it existed. With this patch, we now free the miptree

[Mesa-dev] [PATCH 2/2] eg/compute: Drop reference on code_bo in destructor.

Signed-off-by: Jan Vesely --- src/gallium/drivers/r600/evergreen_compute.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 58626a3114..027930b586

[Mesa-dev] [PATCH 1/2] eg/compute: Use reference counting to handle compute memory pool.

The original bug/corruption was by util_unreference_framebuffer_state, trying to drop reference on cbuf[0] (global AS for OCL). Adding reference counting to set_rat uncovered problems with acessing the pool->bo. Also drops leaked memory from 7,4kB to 1,7Kb in single run of

[Mesa-dev] [Bug 106377] eglWaitClient() doesn't work for surfaceless contexts

https://bugs.freedesktop.org/show_bug.cgi?id=106377 --- Comment #1 from Tapani Pälli --- EGL spec says following: "If a surface associated with the calling thread’s current context is no longer valid, an EGL_BAD_CURRENT_SURFACE error is generated." Having zero mention of

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

Quoting Kenneth Graunke (2018-05-04 02:12:40) > This isn't strictly necessary, but anyone running Cannonlake will > already have Kernel 4.5 or later, so there's no reason to support > the relocation model on Gen10+. /o\ gvt. Need I say more? -Chris ___

Re: [Mesa-dev] [PATCH 0/9] anv: softpin

Quoting Jason Ekstrand (2018-05-04 08:05:00) > On Thu, May 3, 2018 at 11:24 PM, Chris Wilson > wrote: > > Quoting Scott D Phillips (2018-05-02 17:01:00) > > This series teaches anv how to pick its own virtual graphics addresses > > instead of using the

[Mesa-dev] [Bug 106394] Black Mesa cannot compile shaders because of missing GL_EXT_gpu_shader4

https://bugs.freedesktop.org/show_bug.cgi?id=106394 --- Comment #3 from b...@besd.de --- I think the biggest problem is that they use DirectX emulation even though they use the source engine of halflife 2 (which runs absolutely fine btw) -- You are receiving this mail because:

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

On Fri, May 4, 2018 at 12:39 AM, Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 08:34:07) > > On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote: > > > Quoting Kenneth Graunke (2018-05-04 02:12:40) > > > > This isn't strictly necessary, but anyone

Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

Quoting Kenneth Graunke (2018-05-04 02:12:36) > This introduces a new fast virtual memory allocator integrated with our > BO cache bucketing. For larger objects, it falls back to the simple > free-list allocator (util_vma). I wouldn't say fast just yet ;) If you want to explain any advantages,

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

Quoting Kenneth Graunke (2018-05-04 08:34:07) > On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-05-04 02:12:40) > > > This isn't strictly necessary, but anyone running Cannonlake will > > > already have Kernel 4.5 or later, so there's no reason to

Re: [Mesa-dev] [PATCH v2 03/14] etnaviv: rs: add support for multi layer formats

Am Dienstag, den 01.05.2018, 16:48 +0200 schrieb Christian Gmeiner: > The binary blob driver supports 'multi layer' formats. For > instance: gcvSURF_A16B16G16R16F_2_A8R8G8B8 >  < format >_n_< base format > Sort of high-level comment, but to me the usage of the term layer for

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