Re: [Mesa-dev] [PATCH 1/2] i965/gen7: Prefer vertical alignment of 4 when possible.

2013-11-16 Thread Paul Berry 
On 15 November 2013 19:26, Kenneth Graunke kenn...@whitecape.org wrote:

 On 11/15/2013 01:18 PM, Paul Berry wrote:
  Gen6+ allows for color buffers to use a vertical alignment of either 4
  or 2.  Previously we defaulted to 2.  This may have caused problems on
  Gen7 because Y-tiled render targets are not allowed to use a vertical
  alignment of 2.
 
  This patch changes the vertical alignment to 4 on Gen7, except for the
  few formats where a vertical alignment of 2 is required.
  ---
   src/mesa/drivers/dri/i965/brw_tex_layout.c | 25
 ++---
   1 file changed, 22 insertions(+), 3 deletions(-)
 
  diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
 b/src/mesa/drivers/dri/i965/brw_tex_layout.c
  index d05dbeb..2c81eed 100644
  --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
  +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
  @@ -105,11 +105,11 @@ intel_vertical_texture_alignment_unit(struct
 brw_context *brw,
   * | Depth Buffer   |  2  |  2  |  2  |  4
  |  4  |
   * | Separate Stencil Buffer| N/A | N/A | N/A |  4
  |  8  |
   * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4
  |  4  |
  -* | All Others |  2  |  2  |  2  |  2
  |  2  |
  +* | All Others |  2  |  2  |  2  |  *
  |  *  |
   *
 +--+
   *
  -* On SNB+, non-special cases can be overridden by setting the
 SURFACE_STATE
  -* Surface Vertical Alignment field to VALIGN_2 or VALIGN_4.
  +* Where * means either VALIGN_2 or VALIGN_4 depending on the
 setting of
  +* the SURFACE_STATE Surface Vertical Alignment field.
   */
  if (_mesa_is_format_compressed(format))
 return 4;
  @@ -128,6 +128,25 @@ intel_vertical_texture_alignment_unit(struct
 brw_context *brw,
 return 4;
  }
 
  +   if (brw-gen == 7) {
  +  /* On Gen7, we prefer a vertical alignment of 4 when possible,
 because
  +   * that allows Y tiled render targets.
  +   *
  +   * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE
 for most
  +   * messages), on p64, under the heading Surface Vertical
 Alignment:
  +   *
  +   * Value of 1 [VALIGN_4] is not supported for format
 YCRCB_NORMAL
  +   * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f),
 YCRCB_SWAPY
  +   * (0x190)
  +   *
  +   * VALIGN_4 is not supported for surface format
 R32G32B32_FLOAT.
  +   */
  +  if (base_format == GL_YCBCR_MESA || format ==
 MESA_FORMAT_RGB_FLOAT32)
  + return 2;
  +
  +  return 4;
  +   }
  +
  return 2;
   }

 We use Y-tiling on Gen6 as well.


Yes, but the restriction that Y-tiled render targets must use a vertical
alignment of 4 is not present on Gen6, so there would be no benefit to
applying this logic to Gen6.
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[Mesa-dev] [Bug 71665] glu.pc.in missing -I for glu itself

2013-11-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=71665

Matt Turner matts...@gmail.com changed:

   What|Removed |Added

 CC||matts...@gmail.com

-- 
You are receiving this mail because:
You are the assignee for the bug.
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[Mesa-dev] [PATCH] svga: dynamically allocate svga_texture::rendered_to array

2013-11-16 Thread Brian Paul 
Needs to be larger than 6 to accomodate 3D textures and array textures.
Fixes a few piglit tests (fbo-3d, copyteximage 3D).
---
 src/gallium/drivers/svga/svga_resource_texture.c |9 +
 src/gallium/drivers/svga/svga_resource_texture.h |   41 --
 2 files changed, 32 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_resource_texture.c 
b/src/gallium/drivers/svga/svga_resource_texture.c
index 17c87ef..88ab451 100644
--- a/src/gallium/drivers/svga/svga_resource_texture.c
+++ b/src/gallium/drivers/svga/svga_resource_texture.c
@@ -238,6 +238,7 @@ svga_texture_destroy(struct pipe_screen *screen,
 
ss-total_resource_bytes -= tex-size;
 
+   FREE(tex-rendered_to);
FREE(tex);
 }
 
@@ -735,9 +736,15 @@ svga_texture_create(struct pipe_screen *screen,
tex-size = util_resource_size(template);
svgascreen-total_resource_bytes += tex-size;
 
+   tex-rendered_to = calloc(template-depth0 * template-array_size,
+ sizeof(tex-rendered_to[0]));
+   if (!tex-rendered_to)
+  goto error2;
+
return tex-b.b;
 
 error2:
+   FREE(tex-rendered_to);
FREE(tex);
 error1:
return NULL;
@@ -796,5 +803,7 @@ svga_texture_from_handle(struct pipe_screen *screen,
tex-key.cachable = 0;
tex-handle = srf;
 
+   tex-rendered_to = malloc(sizeof(tex-rendered_to[0]));
+
return tex-b.b;
 }
diff --git a/src/gallium/drivers/svga/svga_resource_texture.h 
b/src/gallium/drivers/svga/svga_resource_texture.h
index 6c7a754..1ff42fa 100644
--- a/src/gallium/drivers/svga/svga_resource_texture.h
+++ b/src/gallium/drivers/svga/svga_resource_texture.h
@@ -79,7 +79,8 @@ struct svga_texture
 
unsigned size;  /** Approximate size in bytes */
 
-   unsigned rendered_to[6];  /** six cube faces, one bit per mipmap level */
+   /** array indexed by cube face or 3D/array slice, one bit per mipmap level 
*/
+   ushort *rendered_to;
 };
 
 
@@ -157,16 +158,30 @@ svga_is_texture_level_defined(const struct svga_texture 
*tex,
 }
 
 
-static INLINE void
-svga_set_texture_rendered_to(struct svga_texture *tex,
- unsigned face, unsigned level)
+/** For debugging, check that face and level are legal */
+static inline void
+check_face_level(const struct svga_texture *tex,
+ unsigned face, unsigned level)
 {
if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
-  assert(face  Elements(tex-rendered_to));
+  assert(face  6);
+   }
+   else if (tex-b.b.target == PIPE_TEXTURE_3D) {
+  assert(face  tex-b.b.depth0);
}
else {
-  assert(face == 0);
+  assert(face  tex-b.b.array_size);
}
+
+   assert(level  8 * sizeof(tex-rendered_to[0]));
+}
+
+
+static INLINE void
+svga_set_texture_rendered_to(struct svga_texture *tex,
+ unsigned face, unsigned level)
+{
+   check_face_level(tex, face, level);
tex-rendered_to[face] |= 1  level;
 }
 
@@ -175,12 +190,7 @@ static INLINE void
 svga_clear_texture_rendered_to(struct svga_texture *tex,
unsigned face, unsigned level)
 {
-   if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
-  assert(face  Elements(tex-rendered_to));
-   }
-   else {
-  assert(face == 0);
-   }
+   check_face_level(tex, face, level);
tex-rendered_to[face] = ~(1  level);
 }
 
@@ -189,12 +199,7 @@ static INLINE boolean
 svga_was_texture_rendered_to(const struct svga_texture *tex,
  unsigned face, unsigned level)
 {
-   if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
-  assert(face  Elements(tex-rendered_to));
-   }
-   else {
-  assert(face == 0);
-   }
+   check_face_level(tex, face, level);
return !!(tex-rendered_to[face]  (1  level));
 }
 
-- 
1.7.10.4

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Re: [Mesa-dev] Automake subdir-objects v2

2013-11-16 Thread Emil Velikov 
On 11/11/13 18:53, Emil Velikov wrote:
 Hello list,
 
 Here is an updated version of the subdir-objects series sent earlier.
 
 As a reminder the series aims to
 * make mesa build system subdir-objects compliant
 * minimise flags duplication across gallium
 
 Changes since previous version:
 * Resolved git-rebase mess in patch 5.
 * Dropped patches 6, 8 per Matt's request.
 * Dropped patch 10, 11 - libprogram is gone.
 * Dropped patches 17, 18 per Christian's request.
 * Dropped patch 22 - x86{,-64} is handled alot better now.
 * Dropped patches 33, 34, 35 - st/xorg no longer exists.
 * Resolved minor git rebase conflicts.
 
 The branch can be found over at subdir-objects-v3
 https://github.com/evelikov/Mesa.git
 
 
 As always comments and review is greatly appreciated :)
 
 Cheers,
 Emil
 
Hello list,

Just pushed the series after giving it a few automake compile and scons
runs. As previously mentioned only nouveau and swrast are runtime tested.

If you've notice any build or runtime issues let me know and I'll
address them ASAP.

Cheers,
Emil
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[Mesa-dev] [PATCH 1/6] postprocess: simplify pp_free() code

2013-11-16 Thread Brian Paul 
---
 src/gallium/auxiliary/postprocess/pp_init.c |   27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/src/gallium/auxiliary/postprocess/pp_init.c 
b/src/gallium/auxiliary/postprocess/pp_init.c
index a49a23d..bbebb5c 100644
--- a/src/gallium/auxiliary/postprocess/pp_init.c
+++ b/src/gallium/auxiliary/postprocess/pp_init.c
@@ -169,11 +169,12 @@ pp_free(struct pp_queue_t *ppq)
 {
unsigned int i, j;
 
-   if (ppq) {
-  pp_free_fbos(ppq);
-   }
+   if (!ppq)
+  return;
 
-   if (ppq  ppq-p) {
+   pp_free_fbos(ppq);
+
+   if (ppq-p) {
   if (ppq-p-pipe  ppq-filters  ppq-shaders) {
  for (i = 0; i  ppq-n_filters; i++) {
 unsigned int filter = ppq-filters[i];
@@ -221,17 +222,15 @@ pp_free(struct pp_queue_t *ppq)
   FREE(ppq-p);
}
 
-   if (ppq) {
-  /*
-   * Handle partial initialization for common resource destruction
-   * in the create path.
-   */
-  FREE(ppq-filters);
-  FREE(ppq-shaders);
-  FREE(ppq-pp_queue);
+   /*
+* Handle partial initialization for common resource destruction
+* in the create path.
+*/
+   FREE(ppq-filters);
+   FREE(ppq-shaders);
+   FREE(ppq-pp_queue);
   
-  FREE(ppq);
-   }
+   FREE(ppq);
 
pp_debug(Queue taken down.\n);
 }
-- 
1.7.10.4

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[Mesa-dev] [PATCH 3/6] postprocess: refactor header files, etc

2013-11-16 Thread Brian Paul 
Move private data structures and function prototypes out of the
public postprocess.h header file.
Create a pp_private.h for the shared, private data structures, functions.
Remove pp_program.h header.
---
 src/gallium/auxiliary/postprocess/postprocess.h |   45 ++
 src/gallium/auxiliary/postprocess/pp_celshade.c |1 +
 src/gallium/auxiliary/postprocess/pp_colors.c   |1 +
 src/gallium/auxiliary/postprocess/pp_init.c |1 +
 src/gallium/auxiliary/postprocess/pp_mlaa.c |2 +
 src/gallium/auxiliary/postprocess/pp_private.h  |  109 +++
 src/gallium/auxiliary/postprocess/pp_program.c  |2 +
 src/gallium/auxiliary/postprocess/pp_program.h  |   62 -
 src/gallium/auxiliary/postprocess/pp_run.c  |4 +-
 9 files changed, 125 insertions(+), 102 deletions(-)
 create mode 100644 src/gallium/auxiliary/postprocess/pp_private.h
 delete mode 100644 src/gallium/auxiliary/postprocess/pp_program.h

diff --git a/src/gallium/auxiliary/postprocess/postprocess.h 
b/src/gallium/auxiliary/postprocess/postprocess.h
index e0ab43e..c4b2030 100644
--- a/src/gallium/auxiliary/postprocess/postprocess.h
+++ b/src/gallium/auxiliary/postprocess/postprocess.h
@@ -28,42 +28,19 @@
 #ifndef POSTPROCESS_H
 #define POSTPROCESS_H
 
-#include postprocess/pp_program.h
+#include pipe/p_state.h
 
 #define PP_FILTERS 6/* Increment this if you add filters */
 #define PP_MAX_PASSES 6
 
+struct cso_context;
+
 struct pp_queue_t;  /* Forward definition */
+struct pp_program;
 
 /* Less typing later on */
 typedef void (*pp_func) (struct pp_queue_t *, struct pipe_resource *,
  struct pipe_resource *, unsigned int);
-/**
-*  The main post-processing queue.
-*/
-struct pp_queue_t
-{
-   pp_func *pp_queue;   /* An array of pp_funcs */
-   unsigned int n_filters;  /* Number of enabled filters */
-
-   struct pipe_resource *tmp[2];/* Two temp FBOs for the queue */
-   struct pipe_resource *inner_tmp[3];  /* Three for filter use */
-
-   unsigned int n_tmp, n_inner_tmp;
-
-   struct pipe_resource *depth; /* depth of original input */
-   struct pipe_resource *stencil;   /* stencil shared by inner_tmps */
-   struct pipe_resource *constbuf;  /* MLAA constant buffer */
-   struct pipe_resource *areamaptex;/* MLAA area map texture */
-
-   struct pipe_surface *tmps[2], *inner_tmps[3], *stencils;
-
-   void ***shaders; /* Shaders in TGSI form */
-   unsigned int *filters;   /* Active filter to filters.h mapping. */
-   struct pp_program *p;
-
-   bool fbos_init;
-};
 
 /* Main functions */
 
@@ -72,19 +49,9 @@ struct pp_queue_t *pp_init(struct pipe_context *pipe, const 
unsigned int *,
 void pp_run(struct pp_queue_t *, struct pipe_resource *,
 struct pipe_resource *, struct pipe_resource *);
 void pp_free(struct pp_queue_t *);
-void pp_free_fbos(struct pp_queue_t *);
-void pp_debug(const char *, ...);
-struct pp_program *pp_init_prog(struct pp_queue_t *, struct pipe_context *pipe,
- struct cso_context *);
+
 void pp_init_fbos(struct pp_queue_t *, unsigned int, unsigned int);
-void pp_blit(struct pipe_context *pipe,
- struct pipe_resource *src_tex,
- int srcX0, int srcY0,
- int srcX1, int srcY1,
- int srcZ0,
- struct pipe_surface *dst,
- int dstX0, int dstY0,
- int dstX1, int dstY1);
+
 
 /* The filters */
 
diff --git a/src/gallium/auxiliary/postprocess/pp_celshade.c 
b/src/gallium/auxiliary/postprocess/pp_celshade.c
index 471ec38..9b19fdd 100644
--- a/src/gallium/auxiliary/postprocess/pp_celshade.c
+++ b/src/gallium/auxiliary/postprocess/pp_celshade.c
@@ -28,6 +28,7 @@
 #include postprocess/postprocess.h
 #include postprocess/pp_celshade.h
 #include postprocess/pp_filters.h
+#include postprocess/pp_private.h
 
 /** Init function */
 bool
diff --git a/src/gallium/auxiliary/postprocess/pp_colors.c 
b/src/gallium/auxiliary/postprocess/pp_colors.c
index a0b9d28..247e4df 100644
--- a/src/gallium/auxiliary/postprocess/pp_colors.c
+++ b/src/gallium/auxiliary/postprocess/pp_colors.c
@@ -28,6 +28,7 @@
 #include postprocess/postprocess.h
 #include postprocess/pp_colors.h
 #include postprocess/pp_filters.h
+#include postprocess/pp_private.h
 
 /** The run function of the color filters */
 void
diff --git a/src/gallium/auxiliary/postprocess/pp_init.c 
b/src/gallium/auxiliary/postprocess/pp_init.c
index edd54ce..05a0830 100644
--- a/src/gallium/auxiliary/postprocess/pp_init.c
+++ b/src/gallium/auxiliary/postprocess/pp_init.c
@@ -28,6 +28,7 @@
 #include pipe/p_compiler.h
 
 #include postprocess/filters.h
+#include postprocess/pp_private.h
 
 #include pipe/p_screen.h
 #include util/u_inlines.h
diff --git a/src/gallium/auxiliary/postprocess/pp_mlaa.c 
b/src/gallium/auxiliary/postprocess/pp_mlaa.c
index 656283f..92bd11c 100644
--- a/src/gallium/auxiliary/postprocess/pp_mlaa.c
+++

[Mesa-dev] [PATCH 4/6] postprocess: move #defines to filters.h

2013-11-16 Thread Brian Paul 
They're not needed in postprocess.h
---
 src/gallium/auxiliary/postprocess/filters.h |4 
 src/gallium/auxiliary/postprocess/postprocess.h |3 ---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/postprocess/filters.h 
b/src/gallium/auxiliary/postprocess/filters.h
index 1aa1e3a..321f333 100644
--- a/src/gallium/auxiliary/postprocess/filters.h
+++ b/src/gallium/auxiliary/postprocess/filters.h
@@ -30,6 +30,10 @@
 
 #include postprocess/postprocess.h
 
+#define PP_FILTERS 6/* Increment this if you add filters */
+#define PP_MAX_PASSES 6
+
+
 typedef bool (*pp_init_func) (struct pp_queue_t *, unsigned int,
   unsigned int);
 typedef void (*pp_free_func) (struct pp_queue_t *, unsigned int);
diff --git a/src/gallium/auxiliary/postprocess/postprocess.h 
b/src/gallium/auxiliary/postprocess/postprocess.h
index c4b2030..1db581c 100644
--- a/src/gallium/auxiliary/postprocess/postprocess.h
+++ b/src/gallium/auxiliary/postprocess/postprocess.h
@@ -30,9 +30,6 @@
 
 #include pipe/p_state.h
 
-#define PP_FILTERS 6/* Increment this if you add filters */
-#define PP_MAX_PASSES 6
-
 struct cso_context;
 
 struct pp_queue_t;  /* Forward definition */
-- 
1.7.10.4

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[Mesa-dev] [PATCH 2/6] postprocess: rename program to pp_program

2013-11-16 Thread Brian Paul 
To match the pp_ namespace convention.
---
 src/gallium/auxiliary/postprocess/postprocess.h |4 ++--
 src/gallium/auxiliary/postprocess/pp_colors.c   |2 +-
 src/gallium/auxiliary/postprocess/pp_filters.h  |   14 +++---
 src/gallium/auxiliary/postprocess/pp_init.c |2 +-
 src/gallium/auxiliary/postprocess/pp_mlaa.c |2 +-
 src/gallium/auxiliary/postprocess/pp_program.c  |6 +++---
 src/gallium/auxiliary/postprocess/pp_program.h  |2 +-
 src/gallium/auxiliary/postprocess/pp_run.c  |   14 +++---
 8 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/gallium/auxiliary/postprocess/postprocess.h 
b/src/gallium/auxiliary/postprocess/postprocess.h
index 04b6c75..e0ab43e 100644
--- a/src/gallium/auxiliary/postprocess/postprocess.h
+++ b/src/gallium/auxiliary/postprocess/postprocess.h
@@ -60,7 +60,7 @@ struct pp_queue_t
 
void ***shaders; /* Shaders in TGSI form */
unsigned int *filters;   /* Active filter to filters.h mapping. */
-   struct program *p;
+   struct pp_program *p;
 
bool fbos_init;
 };
@@ -74,7 +74,7 @@ void pp_run(struct pp_queue_t *, struct pipe_resource *,
 void pp_free(struct pp_queue_t *);
 void pp_free_fbos(struct pp_queue_t *);
 void pp_debug(const char *, ...);
-struct program *pp_init_prog(struct pp_queue_t *, struct pipe_context *pipe,
+struct pp_program *pp_init_prog(struct pp_queue_t *, struct pipe_context *pipe,
  struct cso_context *);
 void pp_init_fbos(struct pp_queue_t *, unsigned int, unsigned int);
 void pp_blit(struct pipe_context *pipe,
diff --git a/src/gallium/auxiliary/postprocess/pp_colors.c 
b/src/gallium/auxiliary/postprocess/pp_colors.c
index c30e92e..a0b9d28 100644
--- a/src/gallium/auxiliary/postprocess/pp_colors.c
+++ b/src/gallium/auxiliary/postprocess/pp_colors.c
@@ -35,7 +35,7 @@ pp_nocolor(struct pp_queue_t *ppq, struct pipe_resource *in,
struct pipe_resource *out, unsigned int n)
 {
 
-   struct program *p = ppq-p;
+   struct pp_program *p = ppq-p;
 
pp_filter_setup_in(p, in);
pp_filter_setup_out(p, out);
diff --git a/src/gallium/auxiliary/postprocess/pp_filters.h 
b/src/gallium/auxiliary/postprocess/pp_filters.h
index ada21cc..eaebe4c 100644
--- a/src/gallium/auxiliary/postprocess/pp_filters.h
+++ b/src/gallium/auxiliary/postprocess/pp_filters.h
@@ -43,15 +43,15 @@
 
 /* Helper functions for the filters */
 
-void pp_filter_setup_in(struct program *, struct pipe_resource *);
-void pp_filter_setup_out(struct program *, struct pipe_resource *);
-void pp_filter_end_pass(struct program *);
+void pp_filter_setup_in(struct pp_program *, struct pipe_resource *);
+void pp_filter_setup_out(struct pp_program *, struct pipe_resource *);
+void pp_filter_end_pass(struct pp_program *);
 void *pp_tgsi_to_state(struct pipe_context *, const char *, bool,
const char *);
-void pp_filter_misc_state(struct program *);
-void pp_filter_draw(struct program *);
-void pp_filter_set_fb(struct program *);
-void pp_filter_set_clear_fb(struct program *);
+void pp_filter_misc_state(struct pp_program *);
+void pp_filter_draw(struct pp_program *);
+void pp_filter_set_fb(struct pp_program *);
+void pp_filter_set_clear_fb(struct pp_program *);
 
 
 #endif
diff --git a/src/gallium/auxiliary/postprocess/pp_init.c 
b/src/gallium/auxiliary/postprocess/pp_init.c
index bbebb5c..edd54ce 100644
--- a/src/gallium/auxiliary/postprocess/pp_init.c
+++ b/src/gallium/auxiliary/postprocess/pp_init.c
@@ -255,7 +255,7 @@ pp_init_fbos(struct pp_queue_t *ppq, unsigned int w,
  unsigned int h)
 {
 
-   struct program *p = ppq-p;  /* The lazy will inherit the earth */
+   struct pp_program *p = ppq-p;  /* The lazy will inherit the earth */
 
unsigned int i;
struct pipe_resource tmp_res;
diff --git a/src/gallium/auxiliary/postprocess/pp_mlaa.c 
b/src/gallium/auxiliary/postprocess/pp_mlaa.c
index b299c66..656283f 100644
--- a/src/gallium/auxiliary/postprocess/pp_mlaa.c
+++ b/src/gallium/auxiliary/postprocess/pp_mlaa.c
@@ -75,7 +75,7 @@ pp_jimenezmlaa_run(struct pp_queue_t *ppq, struct 
pipe_resource *in,
struct pipe_resource *out, unsigned int n, bool iscolor)
 {
 
-   struct program *p = ppq-p;
+   struct pp_program *p = ppq-p;
 
struct pipe_depth_stencil_alpha_state mstencil;
struct pipe_sampler_view v_tmp, *arr[3];
diff --git a/src/gallium/auxiliary/postprocess/pp_program.c 
b/src/gallium/auxiliary/postprocess/pp_program.c
index 61a0323..916d6fc 100644
--- a/src/gallium/auxiliary/postprocess/pp_program.c
+++ b/src/gallium/auxiliary/postprocess/pp_program.c
@@ -37,17 +37,17 @@
 #include util/u_memory.h
 
 /** Initialize the internal details */
-struct program *
+struct pp_program *
 pp_init_prog(struct pp_queue_t *ppq, struct pipe_context *pipe,
  struct cso_context *cso)
 {
-   struct program *p;
+   struct pp_program *p;
 
pp_debug(Initializing program\n);
if (!pipe)
   return NULL;
 
-

[Mesa-dev] [PATCH 5/6] postprocess: document the pp_init() function.

2013-11-16 Thread Brian Paul 
---
 src/gallium/auxiliary/postprocess/postprocess.h |9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/postprocess/postprocess.h 
b/src/gallium/auxiliary/postprocess/postprocess.h
index 1db581c..c72f2c4 100644
--- a/src/gallium/auxiliary/postprocess/postprocess.h
+++ b/src/gallium/auxiliary/postprocess/postprocess.h
@@ -41,8 +41,15 @@ typedef void (*pp_func) (struct pp_queue_t *, struct 
pipe_resource *,
 
 /* Main functions */
 
-struct pp_queue_t *pp_init(struct pipe_context *pipe, const unsigned int *,
+/**
+ * Note enabled is an array of values, one per filter stage.
+ * Zero indicates the stage is disabled.  Non-zero indicates the
+ * stage is enabled.  For some stages, the value controls quality.
+ */
+struct pp_queue_t *pp_init(struct pipe_context *pipe,
+   const unsigned int *enabled,
struct cso_context *);
+
 void pp_run(struct pp_queue_t *, struct pipe_resource *,
 struct pipe_resource *, struct pipe_resource *);
 void pp_free(struct pp_queue_t *);
-- 
1.7.10.4

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[Mesa-dev] [PATCH 6/6] osmesa: add support for postprocess filters

2013-11-16 Thread Brian Paul 
Add new OSMesaPostprocess() function to allow using the gallium
postprocessing filters.  This only works for OSMesa with gallium
drivers, not the legacy swrast OSMesa.

Bump OSMESA_MAJOR/MINOR_VERSION numbers to 10.0
---
 include/GL/osmesa.h|   19 +-
 src/gallium/state_trackers/osmesa/osmesa.c |   87 
 src/mesa/drivers/osmesa/osmesa.c   |   11 
 3 files changed, 115 insertions(+), 2 deletions(-)

diff --git a/include/GL/osmesa.h b/include/GL/osmesa.h
index 10c472d..16ee89a 100644
--- a/include/GL/osmesa.h
+++ b/include/GL/osmesa.h
@@ -60,8 +60,8 @@ extern C {
 #include GL/gl.h
 
 
-#define OSMESA_MAJOR_VERSION 6
-#define OSMESA_MINOR_VERSION 5
+#define OSMESA_MAJOR_VERSION 10
+#define OSMESA_MINOR_VERSION 0
 #define OSMESA_PATCH_VERSION 0
 
 
@@ -270,6 +270,21 @@ OSMesaGetProcAddress( const char *funcName );
 GLAPI void GLAPIENTRY
 OSMesaColorClamp(GLboolean enable);
 
+
+/**
+ * Enable/disable Gallium post-process filters.
+ * This should be called after a context is created, but before it is
+ * made current for the first time.  After a context has been made
+ * current, this function has no effect.
+ * If the enable_value param is zero, the filter is disabled.  Otherwise
+ * the filter is enabled, and the value may control the filter's quality.
+ * New in Mesa 10.0
+ */
+GLAPI void GLAPIENTRY
+OSMesaPostprocess(OSMesaContext osmesa, const char *filter,
+  unsigned enable_value);
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c 
b/src/gallium/state_trackers/osmesa/osmesa.c
index 3546183..8b30025 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -59,9 +59,13 @@
 
 #include util/u_atomic.h
 #include util/u_box.h
+#include util/u_debug.h
 #include util/u_format.h
 #include util/u_memory.h
 
+#include postprocess/filters.h
+#include postprocess/postprocess.h
+
 #include state_tracker/st_api.h
 #include state_tracker/st_gl_api.h
 
@@ -90,6 +94,8 @@ struct osmesa_context
 {
struct st_context_iface *stctx;
 
+   boolean ever_used; /* Has this context ever been current? */
+
struct osmesa_buffer *current_buffer;
 
enum pipe_format depth_stencil_format, accum_format;
@@ -99,6 +105,10 @@ struct osmesa_context
GLint user_row_length; /* user-specified number of pixels per row */
GLboolean y_up;/* TRUE  - Y increases upward */
   /* FALSE - Y increases downward */
+
+   /** Which postprocessing filters are enabled. */
+   unsigned pp_enabled[PP_FILTERS];
+   struct pp_queue_t *pp;
 };
 
 
@@ -264,6 +274,12 @@ osmesa_init_st_visual(struct st_visual *vis,
   enum pipe_format accum_format)
 {
vis-buffer_mask = ST_ATTACHMENT_FRONT_LEFT_MASK;
+
+   if (ds_format != PIPE_FORMAT_NONE)
+  vis-buffer_mask |= ST_ATTACHMENT_DEPTH_STENCIL_MASK;
+   if (accum_format != PIPE_FORMAT_NONE)
+  vis-buffer_mask |= ST_ATTACHMENT_ACCUM;
+
vis-color_format = color_format;
vis-depth_stencil_format = ds_format;
vis-accum_format = accum_format;
@@ -302,6 +318,28 @@ osmesa_st_framebuffer_flush_front(struct st_context_iface 
*stctx,
unsigned y, bytes, bpp;
int dst_stride;
 
+   if (osmesa-pp) {
+  struct pipe_resource *zsbuf = NULL;
+  unsigned i;
+
+  /* Find the z/stencil buffer if there is one */
+  for (i = 0; i  Elements(osbuffer-textures); i++) {
+ struct pipe_resource *res = osbuffer-textures[i];
+ if (res) {
+const struct util_format_description *desc =
+   util_format_description(res-format);
+
+if (util_format_has_depth(desc)) {
+   zsbuf = res;
+   break;
+}
+ }
+  }
+
+  /* run the postprocess stage(s) */
+  pp_run(osmesa-pp, res, res, zsbuf);
+   }
+
u_box_2d(0, 0, res-width0, res-height0, box);
 
map = pipe-transfer_map(pipe, res, 0, PIPE_TRANSFER_READ, box,
@@ -581,6 +619,7 @@ GLAPI void GLAPIENTRY
 OSMesaDestroyContext(OSMesaContext osmesa)
 {
if (osmesa) {
+  pp_free(osmesa-pp);
   osmesa-stctx-destroy(osmesa-stctx);
   FREE(osmesa);
}
@@ -654,6 +693,29 @@ OSMesaMakeCurrent(OSMesaContext osmesa, void *buffer, 
GLenum type,
 
stapi-make_current(stapi, osmesa-stctx, osbuffer-stfb, osbuffer-stfb);
 
+   if (!osmesa-ever_used) {
+  /* one-time init, just postprocessing for now */
+  boolean any_pp_enabled = FALSE;
+  unsigned i;
+
+  for (i = 0; i  Elements(osmesa-pp_enabled); i++) {
+ if (osmesa-pp_enabled[i]) {
+any_pp_enabled = TRUE;
+break;
+ }
+  }
+
+  if (any_pp_enabled) {
+ osmesa-pp = pp_init(osmesa-stctx-pipe,
+  osmesa-pp_enabled,
+  osmesa-stctx-cso_context);
+
+ pp_init_fbos(osmesa-pp, width, height);
+  }
+
+  osmesa-ever_used = TRUE;

[Mesa-dev] [PATCH 1/2] drivers/radeon: remove unused CXXFLAGS, LLVM_CPP_FILES

2013-11-16 Thread Emil Velikov 
The above two variables are unused as of commit

  commit 024fe6852a76f33d7e2afc5621340e387c381bb0
  Author: Tom Stellard thomas.stell...@amd.com
  Date:   Tue Apr 2 10:42:50 2013 -0700

  radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2

which removed the only cpp file from drivers/radeon, but missed to
remove the CXXFLAGS. The sequential commit reintroduced and empty
LLVM_CPP_FILES.

Lets cleanup and remove both.

Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 src/gallium/drivers/radeon/Makefile.am | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/Makefile.am 
b/src/gallium/drivers/radeon/Makefile.am
index 457fee9..7971191 100644
--- a/src/gallium/drivers/radeon/Makefile.am
+++ b/src/gallium/drivers/radeon/Makefile.am
@@ -15,15 +15,11 @@ if NEED_RADEON_LLVM
 
 noinst_LTLIBRARIES += libllvmradeon.la
 
-libllvmradeon_la_CXXFLAGS = \
-   $(GALLIUM_DRIVER_CXXFLAGS)
-
 libllvmradeon_la_CFLAGS = \
$(GALLIUM_DRIVER_CFLAGS) \
$(LLVM_CFLAGS)
 
 libllvmradeon_la_SOURCES = \
-   $(LLVM_CPP_FILES) \
$(LLVM_C_FILES)
 
 libllvmradeon_la_LIBADD = \
-- 
1.8.4.2

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[Mesa-dev] [PATCH 2/2] targets/xvmc: export only necessary symbols

2013-11-16 Thread Emil Velikov 
Export only XvMC* symbols for the xvmc targets.

Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 src/gallium/Automake.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/Automake.inc b/src/gallium/Automake.inc
index b6b9b36..1e4a34f 100644
--- a/src/gallium/Automake.inc
+++ b/src/gallium/Automake.inc
@@ -65,11 +65,11 @@ GALLIUM_VDPAU_LINKER_FLAGS = \
-shared \
-no-undefined
 
-# TODO: add -export-symbols-regex
 GALLIUM_XVMC_LINKER_FLAGS = \
-module \
-version-number $(XVMC_MAJOR):$(XVMC_MINOR) \
-shared \
+   -export-symbols-regex '^XvMC' \
-no-undefined
 
 GALLIUM_VDPAU_LIB_DEPS = \
-- 
1.8.4.2

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Re: [Mesa-dev] [PATCH 2/2] targets/xvmc: export only necessary symbols

2013-11-16 Thread Ilia Mirkin 
On Sat, Nov 16, 2013 at 4:39 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
 Export only XvMC* symbols for the xvmc targets.

 Signed-off-by: Emil Velikov emil.l.veli...@gmail.com

Tested-by: Ilia Mirkin imir...@alum.mit.edu

Works fine on my NV42, the vl_screen* and nouveau_drm_screen_create
symbols are indeed gone.

 ---
  src/gallium/Automake.inc | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/src/gallium/Automake.inc b/src/gallium/Automake.inc
 index b6b9b36..1e4a34f 100644
 --- a/src/gallium/Automake.inc
 +++ b/src/gallium/Automake.inc
 @@ -65,11 +65,11 @@ GALLIUM_VDPAU_LINKER_FLAGS = \
 -shared \
 -no-undefined

 -# TODO: add -export-symbols-regex
  GALLIUM_XVMC_LINKER_FLAGS = \
 -module \
 -version-number $(XVMC_MAJOR):$(XVMC_MINOR) \
 -shared \
 +   -export-symbols-regex '^XvMC' \
 -no-undefined

  GALLIUM_VDPAU_LIB_DEPS = \
 --
 1.8.4.2

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Re: [Mesa-dev] [PATCH] svga: dynamically allocate svga_texture::rendered_to array

2013-11-16 Thread Jakob Bornecrantz 
Reviewed-by: Jakob Bornecrantz ja...@vmware.com

On Sat, Nov 16, 2013 at 4:49 PM, Brian Paul bri...@vmware.com wrote:
 Needs to be larger than 6 to accomodate 3D textures and array textures.
 Fixes a few piglit tests (fbo-3d, copyteximage 3D).
 ---
  src/gallium/drivers/svga/svga_resource_texture.c |9 +
  src/gallium/drivers/svga/svga_resource_texture.h |   41 
 --
  2 files changed, 32 insertions(+), 18 deletions(-)

 diff --git a/src/gallium/drivers/svga/svga_resource_texture.c 
 b/src/gallium/drivers/svga/svga_resource_texture.c
 index 17c87ef..88ab451 100644
 --- a/src/gallium/drivers/svga/svga_resource_texture.c
 +++ b/src/gallium/drivers/svga/svga_resource_texture.c
 @@ -238,6 +238,7 @@ svga_texture_destroy(struct pipe_screen *screen,

 ss-total_resource_bytes -= tex-size;

 +   FREE(tex-rendered_to);
 FREE(tex);
  }

 @@ -735,9 +736,15 @@ svga_texture_create(struct pipe_screen *screen,
 tex-size = util_resource_size(template);
 svgascreen-total_resource_bytes += tex-size;

 +   tex-rendered_to = calloc(template-depth0 * template-array_size,
 + sizeof(tex-rendered_to[0]));
 +   if (!tex-rendered_to)
 +  goto error2;
 +
 return tex-b.b;

  error2:
 +   FREE(tex-rendered_to);
 FREE(tex);
  error1:
 return NULL;
 @@ -796,5 +803,7 @@ svga_texture_from_handle(struct pipe_screen *screen,
 tex-key.cachable = 0;
 tex-handle = srf;

 +   tex-rendered_to = malloc(sizeof(tex-rendered_to[0]));
 +
 return tex-b.b;
  }
 diff --git a/src/gallium/drivers/svga/svga_resource_texture.h 
 b/src/gallium/drivers/svga/svga_resource_texture.h
 index 6c7a754..1ff42fa 100644
 --- a/src/gallium/drivers/svga/svga_resource_texture.h
 +++ b/src/gallium/drivers/svga/svga_resource_texture.h
 @@ -79,7 +79,8 @@ struct svga_texture

 unsigned size;  /** Approximate size in bytes */

 -   unsigned rendered_to[6];  /** six cube faces, one bit per mipmap level */
 +   /** array indexed by cube face or 3D/array slice, one bit per mipmap 
 level */
 +   ushort *rendered_to;
  };


 @@ -157,16 +158,30 @@ svga_is_texture_level_defined(const struct svga_texture 
 *tex,
  }


 -static INLINE void
 -svga_set_texture_rendered_to(struct svga_texture *tex,
 - unsigned face, unsigned level)
 +/** For debugging, check that face and level are legal */
 +static inline void
 +check_face_level(const struct svga_texture *tex,
 + unsigned face, unsigned level)
  {
 if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
 -  assert(face  Elements(tex-rendered_to));
 +  assert(face  6);
 +   }
 +   else if (tex-b.b.target == PIPE_TEXTURE_3D) {
 +  assert(face  tex-b.b.depth0);
 }
 else {
 -  assert(face == 0);
 +  assert(face  tex-b.b.array_size);
 }
 +
 +   assert(level  8 * sizeof(tex-rendered_to[0]));
 +}
 +
 +
 +static INLINE void
 +svga_set_texture_rendered_to(struct svga_texture *tex,
 + unsigned face, unsigned level)
 +{
 +   check_face_level(tex, face, level);
 tex-rendered_to[face] |= 1  level;
  }

 @@ -175,12 +190,7 @@ static INLINE void
  svga_clear_texture_rendered_to(struct svga_texture *tex,
 unsigned face, unsigned level)
  {
 -   if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
 -  assert(face  Elements(tex-rendered_to));
 -   }
 -   else {
 -  assert(face == 0);
 -   }
 +   check_face_level(tex, face, level);
 tex-rendered_to[face] = ~(1  level);
  }

 @@ -189,12 +199,7 @@ static INLINE boolean
  svga_was_texture_rendered_to(const struct svga_texture *tex,
   unsigned face, unsigned level)
  {
 -   if (tex-b.b.target == PIPE_TEXTURE_CUBE) {
 -  assert(face  Elements(tex-rendered_to));
 -   }
 -   else {
 -  assert(face == 0);
 -   }
 +   check_face_level(tex, face, level);
 return !!(tex-rendered_to[face]  (1  level));
  }

 --
 1.7.10.4

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[Mesa-dev] [PATCH 2/3] i965: Make invalidate_live_intervals() a virtual method of backend_visitor.

2013-11-16 Thread Matt Turner 
Reviewed-by: Paul Berry stereotype...@gmail.com
---
 src/mesa/drivers/dri/i965/brw_shader.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index aba24c5..ae7823e 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -88,6 +88,8 @@ public:
void dump_instructions();
 
void assign_common_binding_table_offsets(uint32_t 
next_binding_table_offset);
+
+   virtual void invalidate_live_intervals() = 0;
 };
 
 uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
-- 
1.8.3.2

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[Mesa-dev] [PATCH 1/3] i965/vec4: Add invalidate_live_intervals method.

2013-11-16 Thread Matt Turner 
Reviewed-by: Paul Berry stereotype...@gmail.com
---
 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4.cpp  | 8 
 src/mesa/drivers/dri/i965/brw_vec4.h| 1 +
 src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp   | 6 ++
 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 2 +-
 6 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index befea0a..66a5ed8 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1443,5 +1443,5 @@ vec4_visitor::opt_schedule_instructions()
   printf(vec4 estimated execution time: %d cycles\n, sched.time);
}
 
-   this-live_intervals_valid = false;
+   invalidate_live_intervals();
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 20fbd45..e7cfab2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -343,7 +343,7 @@ vec4_visitor::dead_code_eliminate()
}
 
if (progress)
-  live_intervals_valid = false;
+  invalidate_live_intervals();
 
return progress;
 }
@@ -554,7 +554,7 @@ vec4_visitor::opt_algebraic()
}
 
if (progress)
-  this-live_intervals_valid = false;
+  invalidate_live_intervals();
 
return progress;
 }
@@ -1017,7 +1017,7 @@ vec4_visitor::opt_register_coalesce()
}
 
if (progress)
-  live_intervals_valid = false;
+  invalidate_live_intervals();
 
return progress;
 }
@@ -1100,7 +1100,7 @@ vec4_visitor::split_virtual_grfs()
  }
   }
}
-   this-live_intervals_valid = false;
+   invalidate_live_intervals();
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 1f29e57..5cec9f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -352,6 +352,7 @@ public:
void split_uniform_registers();
void pack_uniform_registers();
void calculate_live_intervals();
+   void invalidate_live_intervals();
void split_virtual_grfs();
bool dead_code_eliminate();
bool virtual_grf_interferes(int a, int b);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index d009a08..033c642 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -362,7 +362,7 @@ vec4_visitor::opt_copy_propagation()
}
 
if (progress)
-  live_intervals_valid = false;
+  invalidate_live_intervals();
 
return progress;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
index 3adda09..5bc2f9f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
@@ -266,6 +266,12 @@ vec4_visitor::calculate_live_intervals()
this-live_intervals_valid = true;
 }
 
+void
+vec4_visitor::invalidate_live_intervals()
+{
+   live_intervals_valid = false;
+}
+
 bool
 vec4_visitor::virtual_grf_interferes(int a, int b)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 387e3c4..95c8d9f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -359,7 +359,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
   }
}
 
-   this-live_intervals_valid = false;
+   invalidate_live_intervals();
 }
 
 } /* namespace brw */
-- 
1.8.3.2

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[Mesa-dev] [PATCH] i965/fs: Use source's original type in register_coalesce().

2013-11-16 Thread Matt Turner 
Previously, register_coalesce() would modify

   mov   vgrf1:f  vgrf2:f
   cmp   null vgrf3:d  vgrf1:d

to be

   cmp   null vgrf3:d  vgrf2:f

and incorrectly use vgrf2's type in the instruction that the mov was
coalesced into.
---
My in progress value-numbering pass exposes this bug, but without it I
didn't find anything fixed by the patch in piglit.

 src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 795e01e..800a7b4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2442,6 +2442,7 @@ fs_visitor::register_coalesce()
scan_inst-src[i].reg == inst-dst.reg 
scan_inst-src[i].reg_offset == inst-dst.reg_offset) {
   fs_reg new_src = inst-src[0];
+   new_src.type = scan_inst-src[i].type;
if (scan_inst-src[i].abs) {
   new_src.negate = 0;
   new_src.abs = 1;
-- 
1.8.3.2

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[Mesa-dev] [PATCH 3/3] i965: Add a pass to remove dead control flow.

2013-11-16 Thread Matt Turner 
Removes IF/ENDIF and IF/ELSE/ENDIF with no intervening instructions.

total instructions in shared programs: 1360393 - 1360387 (-0.00%)
instructions in affected programs: 157 - 151 (-3.82%)

(no change in vertex shaders)

Reviewed-by: Paul Berry stereotype...@gmail.com
Reviewed-by: Eric Anholt e...@anholt.net
---
 src/mesa/drivers/dri/i965/Makefile.sources |  1 +
 .../drivers/dri/i965/brw_dead_control_flow.cpp | 83 ++
 src/mesa/drivers/dri/i965/brw_dead_control_flow.h  | 26 +++
 src/mesa/drivers/dri/i965/brw_fs.cpp   |  2 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp |  2 +
 5 files changed, 114 insertions(+)
 create mode 100644 src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
 create mode 100644 src/mesa/drivers/dri/i965/brw_dead_control_flow.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 5724458..ac1363c 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -44,6 +44,7 @@ i965_FILES = \
brw_context.c \
brw_cubemap_normalize.cpp \
brw_curbe.c \
+   brw_dead_control_flow.cpp \
brw_device_info.c \
brw_disasm.c \
brw_draw.c \
diff --git a/src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp 
b/src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
new file mode 100644
index 000..8bdf094
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
@@ -0,0 +1,83 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file brw_dead_control_flow.cpp
+ *
+ * This file implements the dead control flow elimination optimization pass.
+ */
+
+#include brw_shader.h
+#include brw_cfg.h
+
+/* Look for and eliminate dead control flow:
+ *
+ *   - if/endif
+ *   - if/else/endif
+ */
+bool
+dead_control_flow_eliminate(backend_visitor *v)
+{
+   bool progress = false;
+
+   cfg_t cfg(v);
+
+   for (int b = 0; b  cfg.num_blocks; b++) {
+  bblock_t *block = cfg.blocks[b];
+  bool found = false;
+
+  /* ENDIF instructions, by definition, can only be found at the ends of
+   * basic blocks.
+   */
+  backend_instruction *endif_inst = block-end;
+  if (endif_inst-opcode != BRW_OPCODE_ENDIF)
+ continue;
+
+  backend_instruction *if_inst = NULL, *else_inst = NULL;
+  backend_instruction *prev_inst = (backend_instruction *) 
endif_inst-prev;
+  if (prev_inst-opcode == BRW_OPCODE_IF) {
+ if_inst = prev_inst;
+ found = true;
+  } else if (prev_inst-opcode == BRW_OPCODE_ELSE) {
+ else_inst = prev_inst;
+
+ prev_inst = (backend_instruction *) prev_inst-prev;
+ if (prev_inst-opcode == BRW_OPCODE_IF) {
+if_inst = prev_inst;
+found = true;
+ }
+  }
+
+  if (found) {
+ if_inst-remove();
+ if (else_inst)
+else_inst-remove();
+ endif_inst-remove();
+ progress = true;
+  }
+   }
+
+   if (progress)
+  v-invalidate_live_intervals();
+
+   return progress;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_dead_control_flow.h 
b/src/mesa/drivers/dri/i965/brw_dead_control_flow.h
new file mode 100644
index 000..57a4dab
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_dead_control_flow.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above

[Mesa-dev] [PATCH 2/3] i965/fs: Emit compressed 3-source instructions on Haswell.

2013-11-16 Thread Matt Turner 
For commit 4df56177 Paul discovered that the hardware restriction that
Align16 instructions cannot be compressed was lifted on Haswell. This
has prevented us from emitting compressed three-source instructions.

For added confirmation, the bspec lists a work around called
WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
since very early Haswell silicon.
---
Don't do it for BFI2 (see next patch).

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 63ac530..1e5422c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_MAD:
  assert(brw-gen = 6);
 brw_set_access_mode(p, BRW_ALIGN_16);
-if (dispatch_width == 16) {
+ if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_LRP:
  assert(brw-gen = 6);
 brw_set_access_mode(p, BRW_ALIGN_16);
-if (dispatch_width == 16) {
+ if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_LRP(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_BFE:
  assert(brw-gen = 7);
  brw_set_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16) {
+ if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 brw_BFE(p, dst, src[0], src[1], src[2]);
 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
-- 
1.7.12.4

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[Mesa-dev] [PATCH 1/3] i965: Fix disassembled names of BFI1 and BFI2 instructions.

2013-11-16 Thread Matt Turner 
---
 src/mesa/drivers/dri/i965/brw_disasm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 22b37d7..128e717 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -75,8 +75,8 @@ const struct opcode_desc opcode_descs[128] = {
 [BRW_OPCODE_CMP] = { .name = cmp, .nsrc = 2, .ndst = 1 },
 [BRW_OPCODE_CMPN] = { .name = cmpn, .nsrc = 2, .ndst = 1 },
 [BRW_OPCODE_BFE] = { .name = bfe, .nsrc = 3, .ndst = 1},
-[BRW_OPCODE_BFI1] = { .name = bfe1, .nsrc = 2, .ndst = 1},
-[BRW_OPCODE_BFI2] = { .name = bfe2, .nsrc = 3, .ndst = 1},
+[BRW_OPCODE_BFI1] = { .name = bfi1, .nsrc = 2, .ndst = 1},
+[BRW_OPCODE_BFI2] = { .name = bfi2, .nsrc = 3, .ndst = 1},
 [BRW_OPCODE_ADDC] = { .name = addc, .nsrc = 2, .ndst = 1},
 [BRW_OPCODE_SUBB] = { .name = subb, .nsrc = 2, .ndst = 1},
 
-- 
1.7.12.4

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[Mesa-dev] [PATCH 3/3] i965/fs: Don't emit SIMD16 BFI instructions.

2013-11-16 Thread Matt Turner 
---
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 1e5422c..bf38db6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1530,11 +1530,32 @@ fs_generator::generate_code(exec_list *instructions)
 
   case BRW_OPCODE_BFI1:
  assert(brw-gen = 7);
- brw_BFI1(p, dst, src[0], src[1]);
+ /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
+  * should
+  *
+  *Force BFI instructions to be executed always in SIMD8.
+  */
+ if (dispatch_width == 16  brw-is_haswell) {
+brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+brw_BFI1(p, dst, src[0], src[1]);
+brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
+brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
+brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ } else {
+brw_BFI1(p, dst, src[0], src[1]);
+ }
  break;
   case BRW_OPCODE_BFI2:
  assert(brw-gen = 7);
  brw_set_access_mode(p, BRW_ALIGN_16);
+ /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
+  * should
+  *
+  *Force BFI instructions to be executed always in SIMD8.
+  *
+  * Otherwise we would be able to emit compressed instructions like we
+  * do for the other three-source instructions.
+  */
  if (dispatch_width == 16) {
 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 brw_BFI2(p, dst, src[0], src[1], src[2]);
-- 
1.7.12.4

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[Mesa-dev] [PATCH 3/4] docs: update nv50, nvc0 current status

2013-11-16 Thread Emil Velikov 
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 docs/GL3.txt | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 9b9d38b..5f6fa7e 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -18,7 +18,7 @@ are exposed in the 3.0 context as extensions.
 Feature   Status
 - 
 
-GL 3.0 --- all DONE: i965, r600, radeonsi
+GL 3.0 --- all DONE: i965, nv50, nvc0, r600, radeonsi
 
   GLSL 1.30 DONE ()
   glBindFragDataLocation, glGetFragDataLocation DONE
@@ -47,7 +47,7 @@ GL 3.0 --- all DONE: i965, r600, radeonsi
   GLX_ARB_create_context (GLX 1.4 is required)  DONE
 
 
-GL 3.1 --- all DONE: i965, r600, radeonsi
+GL 3.1 --- all DONE: i965, nv50, nvc0, r600, radeonsi
 
   GLSL 1.40 DONE ()
   Forward compatible context support/deprecations   DONE ()
@@ -66,29 +66,29 @@ GL 3.2 --- all DONE: i965
   Core/compatibility profiles   DONE
   GLSL 1.50 DONE ()
   Geometry shaders  DONE ()
-  BGRA vertex order (GL_ARB_vertex_array_bgra)  DONE (r300, r600, 
radeonsi, swrast)
-  Base vertex offset(GL_ARB_draw_elements_base_vertex)  DONE (r300, r600, 
radeonsi, swrast)
-  Frag shader coord (GL_ARB_fragment_coord_conventions) DONE (r300, r600, 
radeonsi, swrast)
-  Provoking vertex (GL_ARB_provoking_vertex)DONE (r300, r600, 
radeonsi, swrast)
-  Seamless cubemaps (GL_ARB_seamless_cube_map)  DONE (r600, radeonsi)
-  Multisample textures (GL_ARB_texture_multisample) DONE (r600, radeonsi)
-  Frag depth clamp (GL_ARB_depth_clamp) DONE (r600, swrast, 
radeonsi)
-  Fence objects (GL_ARB_sync)   DONE (r300, r600, 
radeonsi, swrast)
+  BGRA vertex order (GL_ARB_vertex_array_bgra)  DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  Base vertex offset(GL_ARB_draw_elements_base_vertex)  DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  Frag shader coord (GL_ARB_fragment_coord_conventions) DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  Provoking vertex (GL_ARB_provoking_vertex)DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  Seamless cubemaps (GL_ARB_seamless_cube_map)  DONE (nvc0, r600, 
radeonsi)
+  Multisample textures (GL_ARB_texture_multisample) DONE (nvc0, r600, 
radeonsi)
+  Frag depth clamp (GL_ARB_depth_clamp) DONE (nv50, nvc0, 
r600, swrast, radeonsi)
+  Fence objects (GL_ARB_sync)   DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
   GLX_ARB_create_context_profileDONE
 
 
 GL 3.3 --- all DONE: i965
 
   GLSL 3.30 DONE ()
-  GL_ARB_blend_func_extendedDONE (r600, radeonsi, 
softpipe)
-  GL_ARB_explicit_attrib_location   DONE (i915, r300, 
r600, radeonsi, swrast)
-  GL_ARB_occlusion_query2   DONE (r300, r600, 
radeonsi, swrast)
-  GL_ARB_sampler_objectsDONE (r300, r600, 
radeonsi)
-  GL_ARB_shader_bit_encodingDONE (r600, radeonsi)
+  GL_ARB_blend_func_extendedDONE (nv50, nvc0, 
r600, radeonsi, softpipe)
+  GL_ARB_explicit_attrib_location   DONE (i915, nv50, 
nvc0, r300, r600, radeonsi, swrast)
+  GL_ARB_occlusion_query2   DONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  GL_ARB_sampler_objectsDONE (nv50, nvc0, 
r300, r600, radeonsi)
+  GL_ARB_shader_bit_encodingDONE (nv50, nvc0, 
r600, radeonsi)
   GL_ARB_texture_rgb10_a2ui DONE (r600, radeonsi)
-  GL_ARB_texture_swizzleDONE (r300, r600, 
radeonsi, swrast)
-  GL_ARB_timer_queryDONE (r600, radeonsi)
-  GL_ARB_instanced_arrays   DONE (r300, r600, 
radeonsi)
+  GL_ARB_texture_swizzleDONE (nv50, nvc0, 
r300, r600, radeonsi, swrast)
+  GL_ARB_timer_queryDONE (nv50, nvc0, 
r600, radeonsi)
+  GL_ARB_instanced_arrays   DONE (nv50, nvc0, 
r300, r600, radeonsi)
   GL_ARB_vertex_type_2_10_10_10_rev DONE (r600, radeonsi)
 
 
-- 
1.8.4.2

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[Mesa-dev] [PATCH 2/4] - Indent items under a GL version to allow context diffs to do their work. - Move complete drivers into the GL version line - this should make the stuff a little bit easier to r

2013-11-16 Thread Emil Velikov 
From: Joerg Mayer jma...@loplof.de

v2: keep the fd.o link (Emil Velikov)

Signed-off-by: Joerg Mayer jma...@loplof.de
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 docs/GL3.txt | 276 +--
 1 file changed, 138 insertions(+), 138 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index a8cffab..9b9d38b 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -18,164 +18,164 @@ are exposed in the 3.0 context as extensions.
 Feature   Status
 - 
 
-GL 3.0:
-
-GLSL 1.30 DONE (i965, r600, 
radeonsi)
-glBindFragDataLocation, glGetFragDataLocation DONE
-Conditional rendering (GL_NV_conditional_render)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Map buffer subranges (GL_ARB_map_buffer_range)DONE (i965, r300, r600, 
radeonsi, swrast)
-Clamping controls (GL_ARB_color_buffer_float) DONE (i965, r300, r600, 
radeonsi)
-Float textures, renderbuffers (GL_ARB_texture_float)  DONE (i965, r300, r600, 
radeonsi)
-GL_EXT_packed_float   DONE (i965, r600, 
radeonsi)
-GL_EXT_texture_shared_exponentDONE (i965, r600, 
radeonsi, swrast)
-Float depth buffers (GL_ARB_depth_buffer_float)   DONE (i965, r600, 
radeonsi)
-Framebuffer objects (GL_ARB_framebuffer_object)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Half-floatDONE (i965, r300, r600, 
radeonsi, swrast)
-Non-normalized Integer texture/framebuffer formatsDONE (i965, r600, 
radeonsi)
-1D/2D Texture arrays  DONE (i965, r600, 
radeonsi)
-Per-buffer blend and masks (GL_EXT_draw_buffers2) DONE (i965, r600, 
radeonsi, swrast)
-GL_EXT_texture_compression_rgtc   DONE (i965, r300, r600, 
radeonsi, swrast)
-Red and red/green texture formats DONE (i965, r300, r600, 
radeonsi, swrast)
-Transform feedback (GL_EXT_transform_feedback)DONE (i965, r600, 
radeonsi)
-Vertex array objects (GL_APPLE_vertex_array_object)   DONE (all drivers)
-sRGB framebuffer format (GL_EXT_framebuffer_sRGB) DONE (i965, r600, 
radeonsi)
-glClearBuffer commandsDONE
-glGetStringi command  DONE
-glTexParameterI, glGetTexParameterI commands  DONE
-glVertexAttribI commands  DONE
-Depth format cube texturesDONE (i965, r600, 
radeonsi)
-GLX_ARB_create_context (GLX 1.4 is required)  DONE
-
-
-GL 3.1:
-
-GLSL 1.40 DONE (i965, r600, 
radeonsi)
-Forward compatible context support/deprecations   DONE (i965, r600, 
radeonsi)
-Instanced drawing (GL_ARB_draw_instanced) DONE (i965, r600, 
radeonsi, swrast)
-Buffer copying (GL_ARB_copy_buffer)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Primitive restart (GL_NV_primitive_restart)   DONE (i965, r300, r600, 
radeonsi)
-16 vertex texture image units DONE (i965, r600, 
radeonsi)
-Texture buffer objs (GL_ARB_texture_buffer_object)DONE for OpenGL 3.1 
contexts (i965, r600, radeonsi)
-Rectangular textures (GL_ARB_texture_rectangle)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Uniform buffer objs (GL_ARB_uniform_buffer_object)DONE (i965, r600, 
radeonsi, swrast)
-Signed normalized textures (GL_EXT_texture_snorm) DONE (i965, r300, r600, 
radeonsi)
-
-
-GL 3.2:
-
-Core/compatibility profiles   DONE
-GLSL 1.50 DONE (i965)
-Geometry shaders  DONE (i965)
-BGRA vertex order (GL_ARB_vertex_array_bgra)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Base vertex offset(GL_ARB_draw_elements_base_vertex)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Frag shader coord (GL_ARB_fragment_coord_conventions) DONE (i965, r300, r600, 
radeonsi, swrast)
-Provoking vertex (GL_ARB_provoking_vertex)DONE (i965, r300, r600, 
radeonsi, swrast)
-Seamless cubemaps (GL_ARB_seamless_cube_map)  DONE (i965, r600, 
radeonsi)
-Multisample textures (GL_ARB_texture_multisample) DONE (i965, r600, 
radeonsi)
-Frag depth clamp (GL_ARB_depth_clamp) DONE (i965, r600, 
swrast, radeonsi)
-Fence objects (GL_ARB_sync)   DONE (i965, r300, r600, 
radeonsi, swrast)
-GLX_ARB_create_context_profileDONE
-
-
-GL 3.3:
-
-GLSL 3.30 DONE (i965)
-GL_ARB_blend_func_extendedDONE (i965, r600, 
radeonsi, softpipe)
-GL_ARB_explicit_attrib_location   DONE (i915, i965, r300, 
r600, radeonsi, swrast)
-GL_ARB_occlusion_query2   DONE

[Mesa-dev] [PATCH 1/4] docs: add a note about removed state tracker/targets

2013-11-16 Thread Emil Velikov 
The X.Org state tracker is gone, as well as the xvmc/vdpau
r300 and softpipe targets.

Cc: 10.0 mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 docs/relnotes/10.0.html | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/10.0.html b/docs/relnotes/10.0.html
index eabe77f..f06d068 100644
--- a/docs/relnotes/10.0.html
+++ b/docs/relnotes/10.0.html
@@ -64,7 +64,11 @@ TBD.
 
 h2Changes/h2
 
-TBD.
+ul
+liRemoved X.Org state tracker (unmaintained and broken)/li
+liRemoved the video-accel r300 targets/li
+liRemoved the video-accel softpipe targets/li
+/ul
 
 /div
 /body
-- 
1.8.4.2

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[Mesa-dev] [PATCH 4/4] docs: indicate GLX_MESA_query_renderer's completion

2013-11-16 Thread Emil Velikov 
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 docs/relnotes/10.0.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/10.0.html b/docs/relnotes/10.0.html
index f06d068..1e4f771 100644
--- a/docs/relnotes/10.0.html
+++ b/docs/relnotes/10.0.html
@@ -55,6 +55,7 @@ Note: some of the new features are only available with 
certain drivers.
 liGL_ARB_vertex_attrib_binding/li
 liGL_ARB_vertex_type_10f_11f_11f_rev on i965 and r600g/li
 liGL_KHR_debug/li
+liGLX_MESA_query_renderer/li
 /ul
 
 
-- 
1.8.4.2

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[Mesa-dev] [PATCH 2/4] docs: restructure GL3.txt

2013-11-16 Thread Emil Velikov 
From: Joerg Mayer jma...@loplof.de

- Indent items under a GL version to allow context diffs to do their work.
- Move complete drivers into the GL version line - this should make the
  stuff a little bit easier to read.

v2: keep the fd.o link (Emil Velikov)

Signed-off-by: Joerg Mayer jma...@loplof.de
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 docs/GL3.txt | 276 +--
 1 file changed, 138 insertions(+), 138 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index a8cffab..9b9d38b 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -18,164 +18,164 @@ are exposed in the 3.0 context as extensions.
 Feature   Status
 - 
 
-GL 3.0:
-
-GLSL 1.30 DONE (i965, r600, 
radeonsi)
-glBindFragDataLocation, glGetFragDataLocation DONE
-Conditional rendering (GL_NV_conditional_render)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Map buffer subranges (GL_ARB_map_buffer_range)DONE (i965, r300, r600, 
radeonsi, swrast)
-Clamping controls (GL_ARB_color_buffer_float) DONE (i965, r300, r600, 
radeonsi)
-Float textures, renderbuffers (GL_ARB_texture_float)  DONE (i965, r300, r600, 
radeonsi)
-GL_EXT_packed_float   DONE (i965, r600, 
radeonsi)
-GL_EXT_texture_shared_exponentDONE (i965, r600, 
radeonsi, swrast)
-Float depth buffers (GL_ARB_depth_buffer_float)   DONE (i965, r600, 
radeonsi)
-Framebuffer objects (GL_ARB_framebuffer_object)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Half-floatDONE (i965, r300, r600, 
radeonsi, swrast)
-Non-normalized Integer texture/framebuffer formatsDONE (i965, r600, 
radeonsi)
-1D/2D Texture arrays  DONE (i965, r600, 
radeonsi)
-Per-buffer blend and masks (GL_EXT_draw_buffers2) DONE (i965, r600, 
radeonsi, swrast)
-GL_EXT_texture_compression_rgtc   DONE (i965, r300, r600, 
radeonsi, swrast)
-Red and red/green texture formats DONE (i965, r300, r600, 
radeonsi, swrast)
-Transform feedback (GL_EXT_transform_feedback)DONE (i965, r600, 
radeonsi)
-Vertex array objects (GL_APPLE_vertex_array_object)   DONE (all drivers)
-sRGB framebuffer format (GL_EXT_framebuffer_sRGB) DONE (i965, r600, 
radeonsi)
-glClearBuffer commandsDONE
-glGetStringi command  DONE
-glTexParameterI, glGetTexParameterI commands  DONE
-glVertexAttribI commands  DONE
-Depth format cube texturesDONE (i965, r600, 
radeonsi)
-GLX_ARB_create_context (GLX 1.4 is required)  DONE
-
-
-GL 3.1:
-
-GLSL 1.40 DONE (i965, r600, 
radeonsi)
-Forward compatible context support/deprecations   DONE (i965, r600, 
radeonsi)
-Instanced drawing (GL_ARB_draw_instanced) DONE (i965, r600, 
radeonsi, swrast)
-Buffer copying (GL_ARB_copy_buffer)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Primitive restart (GL_NV_primitive_restart)   DONE (i965, r300, r600, 
radeonsi)
-16 vertex texture image units DONE (i965, r600, 
radeonsi)
-Texture buffer objs (GL_ARB_texture_buffer_object)DONE for OpenGL 3.1 
contexts (i965, r600, radeonsi)
-Rectangular textures (GL_ARB_texture_rectangle)   DONE (i965, r300, r600, 
radeonsi, swrast)
-Uniform buffer objs (GL_ARB_uniform_buffer_object)DONE (i965, r600, 
radeonsi, swrast)
-Signed normalized textures (GL_EXT_texture_snorm) DONE (i965, r300, r600, 
radeonsi)
-
-
-GL 3.2:
-
-Core/compatibility profiles   DONE
-GLSL 1.50 DONE (i965)
-Geometry shaders  DONE (i965)
-BGRA vertex order (GL_ARB_vertex_array_bgra)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Base vertex offset(GL_ARB_draw_elements_base_vertex)  DONE (i965, r300, r600, 
radeonsi, swrast)
-Frag shader coord (GL_ARB_fragment_coord_conventions) DONE (i965, r300, r600, 
radeonsi, swrast)
-Provoking vertex (GL_ARB_provoking_vertex)DONE (i965, r300, r600, 
radeonsi, swrast)
-Seamless cubemaps (GL_ARB_seamless_cube_map)  DONE (i965, r600, 
radeonsi)
-Multisample textures (GL_ARB_texture_multisample) DONE (i965, r600, 
radeonsi)
-Frag depth clamp (GL_ARB_depth_clamp) DONE (i965, r600, 
swrast, radeonsi)
-Fence objects (GL_ARB_sync)   DONE (i965, r300, r600, 
radeonsi, swrast)
-GLX_ARB_create_context_profileDONE
-
-
-GL 3.3:
-
-GLSL 3.30 DONE (i965)
-GL_ARB_blend_func_extendedDONE (i965, r600,

Re: [Mesa-dev] [PATCH 2/3] i965/fs: Emit compressed 3-source instructions on Haswell.

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 03:24 PM, Matt Turner wrote:
 For commit 4df56177 Paul discovered that the hardware restriction that
 Align16 instructions cannot be compressed was lifted on Haswell. This
 has prevented us from emitting compressed three-source instructions.
 
 For added confirmation, the bspec lists a work around called
 WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
 since very early Haswell silicon.
 ---
 Don't do it for BFI2 (see next patch).
 
  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 index 63ac530..1e5422c 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 @@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_MAD:
   assert(brw-gen = 6);
brw_set_access_mode(p, BRW_ALIGN_16);
 -  if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_MAD(p, dst, src[0], src[1], src[2]);
   brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 @@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_LRP:
   assert(brw-gen = 6);
brw_set_access_mode(p, BRW_ALIGN_16);
 -  if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_LRP(p, dst, src[0], src[1], src[2]);
   brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 @@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_BFE:
   assert(brw-gen = 7);
   brw_set_access_mode(p, BRW_ALIGN_16);
 - if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
  brw_set_compression_control(p, BRW_COMPRESSION_NONE);
  brw_BFE(p, dst, src[0], src[1], src[2]);
  brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 

Ehh.  These checks look wrong; won't they make us stop breaking
these into two 8-wide halves on Sandybridge?  MAD and LRP are supported
there.

I think you just want:

if (dispatch_width == 16  !brw-is_haswell) {
   ...break in two...
} else {
   ...emit a single instruction...
}

Then, Sandybridge, Ivybridge, and Baytrail will properly break 16-wide
in two, while Haswell won't.  Broadwell doesn't use this code, so gen 
7 doesn't matter.

--Ken
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Re: [Mesa-dev] [PATCH 1/3] i965: Fix disassembled names of BFI1 and BFI2 instructions.

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 03:24 PM, Matt Turner wrote:
 ---
  src/mesa/drivers/dri/i965/brw_disasm.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
 b/src/mesa/drivers/dri/i965/brw_disasm.c
 index 22b37d7..128e717 100644
 --- a/src/mesa/drivers/dri/i965/brw_disasm.c
 +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
 @@ -75,8 +75,8 @@ const struct opcode_desc opcode_descs[128] = {
  [BRW_OPCODE_CMP] = { .name = cmp, .nsrc = 2, .ndst = 1 },
  [BRW_OPCODE_CMPN] = { .name = cmpn, .nsrc = 2, .ndst = 1 },
  [BRW_OPCODE_BFE] = { .name = bfe, .nsrc = 3, .ndst = 1},
 -[BRW_OPCODE_BFI1] = { .name = bfe1, .nsrc = 2, .ndst = 1},
 -[BRW_OPCODE_BFI2] = { .name = bfe2, .nsrc = 3, .ndst = 1},
 +[BRW_OPCODE_BFI1] = { .name = bfi1, .nsrc = 2, .ndst = 1},
 +[BRW_OPCODE_BFI2] = { .name = bfi2, .nsrc = 3, .ndst = 1},
  [BRW_OPCODE_ADDC] = { .name = addc, .nsrc = 2, .ndst = 1},
  [BRW_OPCODE_SUBB] = { .name = subb, .nsrc = 2, .ndst = 1},
  
 

This patch is:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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Re: [Mesa-dev] [PATCH 3/3] i965/fs: Don't emit SIMD16 BFI instructions.

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 03:24 PM, Matt Turner wrote:
 ---
  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 23 ++-
  1 file changed, 22 insertions(+), 1 deletion(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 index 1e5422c..bf38db6 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 @@ -1530,11 +1530,32 @@ fs_generator::generate_code(exec_list *instructions)
  
case BRW_OPCODE_BFI1:
   assert(brw-gen = 7);
 - brw_BFI1(p, dst, src[0], src[1]);
 + /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
 +  * should
 +  *
 +  *Force BFI instructions to be executed always in SIMD8.
 +  */
 + if (dispatch_width == 16  brw-is_haswell) {
 +brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 +brw_BFI1(p, dst, src[0], src[1]);
 +brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 +brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
 +brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
 + } else {
 +brw_BFI1(p, dst, src[0], src[1]);
 + }
   break;
case BRW_OPCODE_BFI2:
   assert(brw-gen = 7);
   brw_set_access_mode(p, BRW_ALIGN_16);
 + /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
 +  * should
 +  *
 +  *Force BFI instructions to be executed always in SIMD8.
 +  *
 +  * Otherwise we would be able to emit compressed instructions like 
 we
 +  * do for the other three-source instructions.
 +  */
   if (dispatch_width == 16) {
  brw_set_compression_control(p, BRW_COMPRESSION_NONE);
  brw_BFI2(p, dst, src[0], src[1], src[2]);
 

I'm skeptical that BFI needs to be broken in two on Haswell but not on
Ivybridge or Baytrail.  I'd guess it just always needs to be broken down.

Is there some way I can test that for you?
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Re: [Mesa-dev] [PATCH 3/3] i965: Add a pass to remove dead control flow.

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 03:23 PM, Matt Turner wrote:
 Removes IF/ENDIF and IF/ELSE/ENDIF with no intervening instructions.
 
 total instructions in shared programs: 1360393 - 1360387 (-0.00%)
 instructions in affected programs: 157 - 151 (-3.82%)
 
 (no change in vertex shaders)
 
 Reviewed-by: Paul Berry stereotype...@gmail.com
 Reviewed-by: Eric Anholt e...@anholt.net

This series is also:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

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Re: [Mesa-dev] [PATCH 2/3] i965/fs: Emit compressed 3-source instructions on Haswell.

2013-11-16 Thread Matt Turner 
On Sat, Nov 16, 2013 at 3:53 PM, Kenneth Graunke kenn...@whitecape.org wrote:
 On 11/16/2013 03:24 PM, Matt Turner wrote:
 For commit 4df56177 Paul discovered that the hardware restriction that
 Align16 instructions cannot be compressed was lifted on Haswell. This
 has prevented us from emitting compressed three-source instructions.

 For added confirmation, the bspec lists a work around called
 WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
 since very early Haswell silicon.
 ---
 Don't do it for BFI2 (see next patch).

  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

 diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 index 63ac530..1e5422c 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
 @@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_MAD:
   assert(brw-gen = 6);
brw_set_access_mode(p, BRW_ALIGN_16);
 -  if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_MAD(p, dst, src[0], src[1], src[2]);
   brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 @@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_LRP:
   assert(brw-gen = 6);
brw_set_access_mode(p, BRW_ALIGN_16);
 -  if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_LRP(p, dst, src[0], src[1], src[2]);
   brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
 @@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_BFE:
   assert(brw-gen = 7);
   brw_set_access_mode(p, BRW_ALIGN_16);
 - if (dispatch_width == 16) {
 + if (dispatch_width == 16  brw-gen == 7  !brw-is_haswell) {
  brw_set_compression_control(p, BRW_COMPRESSION_NONE);
  brw_BFE(p, dst, src[0], src[1], src[2]);
  brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);


 Ehh.  These checks look wrong; won't they make us stop breaking
 these into two 8-wide halves on Sandybridge?  MAD and LRP are supported
 there.

 I think you just want:

 if (dispatch_width == 16  !brw-is_haswell) {

Yes. Silly mistake.
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[Mesa-dev] [PATCH 2/3] i965/fs: Emit compressed 3-source instructions on Haswell.

2013-11-16 Thread Matt Turner 
For commit 4df56177 Paul discovered that the hardware restriction that
Align16 instructions cannot be compressed was lifted on Haswell. This
has prevented us from emitting compressed three-source instructions.

For added confirmation, the bspec lists a work around called
WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
since very early Haswell silicon.
---
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index cc58ff2..a97a016 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_MAD:
  assert(brw-gen = 6);
 brw_set_access_mode(p, BRW_ALIGN_16);
-if (dispatch_width == 16) {
+ if (dispatch_width == 16  !brw-is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_LRP:
  assert(brw-gen = 6);
 brw_set_access_mode(p, BRW_ALIGN_16);
-if (dispatch_width == 16) {
+ if (dispatch_width == 16  !brw-is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_LRP(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
   case BRW_OPCODE_BFE:
  assert(brw-gen = 7);
  brw_set_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16) {
+ if (dispatch_width == 16  !brw-is_haswell) {
 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 brw_BFE(p, dst, src[0], src[1], src[2]);
 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
-- 
1.8.3.2

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[Mesa-dev] [PATCH 3/3] i965: Fix broken asserts

2013-11-16 Thread Chris Forbes 
These would never fire.

Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
 src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4_vp.cpp| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 5024bed..e154441 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -418,7 +418,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment 
*ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
-  assert(!not reached: expression operates on scalars only);
+  assert(!not reached: expression operates on scalars only);
   break;
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 1f3d75c..d98bad1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -493,7 +493,7 @@ vec4_vs_visitor::get_vp_dst_reg(const prog_dst_register 
dst)
   return dst_null_f();
 
default:
-  assert(vec4_vp: bad destination register file);
+  assert(!vec4_vp: bad destination register file);
   return dst_reg(this, glsl_type::vec4_type);
}
 
-- 
1.8.4.2

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[Mesa-dev] [PATCH 1/3] r600/sb: Fix broken assert

2013-11-16 Thread Chris Forbes 
This would never fire.

Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
 src/gallium/drivers/r600/sb/sb_sched.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp 
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 2792315..1413916 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -527,7 +527,7 @@ bool alu_group_tracker::try_reserve(alu_node* n) {
forced_swz_slots |= (1  i);
a-bc.bank_swizzle = VEC_210;
if (!gpr.try_reserve(a))
-   assert(!internal reservation error);
+   assert(!internal reservation error);
} else {
if (first_nf == ~0)
first_nf = i;
-- 
1.8.4.2

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[Mesa-dev] [PATCH 2/3] st/vega: Fix broken assert

2013-11-16 Thread Chris Forbes 
This would never fire.

Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
 src/gallium/state_trackers/vega/paint.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/vega/paint.c 
b/src/gallium/state_trackers/vega/paint.c
index 79b7a27..fea9fc1 100644
--- a/src/gallium/state_trackers/vega/paint.c
+++ b/src/gallium/state_trackers/vega/paint.c
@@ -516,7 +516,7 @@ void paint_set_pattern_tiling(struct vg_paint *paint,
   paint-pattern.sampler.wrap_t = PIPE_TEX_WRAP_MIRROR_REPEAT;
   break;
default:
-  debug_assert(!Unknown tiling mode);
+  debug_assert(!Unknown tiling mode);
}
 }
 
-- 
1.8.4.2

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Re: [Mesa-dev] [PATCH 3/3] i965: Fix broken asserts

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 06:00 PM, Chris Forbes wrote:
 These would never fire.
 
 Signed-off-by: Chris Forbes chr...@ijw.co.nz
 ---
  src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 2 +-
  src/mesa/drivers/dri/i965/brw_vec4_vp.cpp| 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
 index 5024bed..e154441 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
 @@ -418,7 +418,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment 
 *ir)
 case ir_unop_unpack_half_2x16_split_x:
 case ir_unop_unpack_half_2x16_split_y:
 case ir_binop_pack_half_2x16_split:
 -  assert(!not reached: expression operates on scalars only);
 +  assert(!not reached: expression operates on scalars only);
break;
 }
  
 diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp 
 b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
 index 1f3d75c..d98bad1 100644
 --- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
 @@ -493,7 +493,7 @@ vec4_vs_visitor::get_vp_dst_reg(const prog_dst_register 
 dst)
return dst_null_f();
  
 default:
 -  assert(vec4_vp: bad destination register file);
 +  assert(!vec4_vp: bad destination register file);
return dst_reg(this, glsl_type::vec4_type);
 }
  
 

All three are:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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[Mesa-dev] [PATCH] mesa: bump version to 10.1 (devel)

2013-11-16 Thread Chris Forbes 
Now that branch 10.0 is created, bump the minor version in
master.

Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
 VERSION |  2 +-
 docs/relnotes.html  |  1 +
 docs/relnotes/10.1.html | 60 +
 3 files changed, 62 insertions(+), 1 deletion(-)
 create mode 100644 docs/relnotes/10.1.html

diff --git a/VERSION b/VERSION
index 8e92e83..7432bee 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.0.0-devel
+10.1.0-devel
diff --git a/docs/relnotes.html b/docs/relnotes.html
index c232456..13de49a 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 /p
 
 ul
+lia href=relnotes/10.1.html10.1 release notes/a
 lia href=relnotes/10.0.html10.0 release notes/a
 lia href=relnotes/9.2.3.html9.2.3 release notes/a
 lia href=relnotes/9.2.2.html9.2.2 release notes/a
diff --git a/docs/relnotes/10.1.html b/docs/relnotes/10.1.html
new file mode 100644
index 000..55d810f
--- /dev/null
+++ b/docs/relnotes/10.1.html
@@ -0,0 +1,60 @@
+!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.01 Transitional//EN 
http://www.w3.org/TR/html4/loose.dtd;
+html lang=en
+head
+  meta http-equiv=content-type content=text/html; charset=utf-8
+  titleMesa Release Notes/title
+  link rel=stylesheet type=text/css href=../mesa.css
+/head
+body
+
+div class=header
+  h1The Mesa 3D Graphics Library/h1
+/div
+
+iframe src=../contents.html/iframe
+div class=content
+
+h1Mesa 10.1 Release Notes / TBD/h1
+
+p
+Mesa 10.1 is a new development release.
+People who are concerned with stability and reliability should stick
+with a previous release or wait for Mesa 10.1.1.
+/p
+p
+Mesa 10.1 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is strongonly/strong available if requested at context creation
+because compatibility contexts are not supported.
+/p
+
+
+h2MD5 checksums/h2
+pre
+TBD.
+/pre
+
+
+h2New features/h2
+
+p
+Note: some of the new features are only available with certain drivers.
+/p
+
+ul
+/ul
+
+
+h2Bug fixes/h2
+
+TBD.
+
+h2Changes/h2
+
+TBD.
+
+/div
+/body
+/html
-- 
1.8.4.2

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Re: [Mesa-dev] [PATCH 1/4] docs: add a note about removed state tracker/targets

2013-11-16 Thread Chris Forbes 
For the series:

Acked-by: Chris Forbes chr...@ijw.co.nz

On Sun, Nov 17, 2013 at 12:27 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
 The X.Org state tracker is gone, as well as the xvmc/vdpau
 r300 and softpipe targets.

 Cc: 10.0 mesa-sta...@lists.freedesktop.org
 Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
 ---
  docs/relnotes/10.0.html | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

 diff --git a/docs/relnotes/10.0.html b/docs/relnotes/10.0.html
 index eabe77f..f06d068 100644
 --- a/docs/relnotes/10.0.html
 +++ b/docs/relnotes/10.0.html
 @@ -64,7 +64,11 @@ TBD.

  h2Changes/h2

 -TBD.
 +ul
 +liRemoved X.Org state tracker (unmaintained and broken)/li
 +liRemoved the video-accel r300 targets/li
 +liRemoved the video-accel softpipe targets/li
 +/ul

  /div
  /body
 --
 1.8.4.2

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Re: [Mesa-dev] [PATCH] mesa: bump version to 10.1 (devel)

2013-11-16 Thread Kenneth Graunke 
On 11/16/2013 10:38 PM, Chris Forbes wrote:
 Now that branch 10.0 is created, bump the minor version in
 master.
 
 Signed-off-by: Chris Forbes chr...@ijw.co.nz

We always forget this for some reason...

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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