[Mesa-dev] [PATCH] st/xa: Fix performance regression introduced by commit Cache render target surface

[Thomas Hellstrom]

The mentioned commit has the nasty side-effect of turning off accelerated
copies.

Cc: 10.1 10.2 mesa-sta...@lists.freedekstop.org
Signed-off-by: Thomas Hellstrom thellst...@vmware.com
---
 src/gallium/state_trackers/xa/xa_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/xa/xa_context.c 
b/src/gallium/state_trackers/xa/xa_context.c
index 37de45b..df3043c 100644
--- a/src/gallium/state_trackers/xa/xa_context.c
+++ b/src/gallium/state_trackers/xa/xa_context.c
@@ -223,7 +223,7 @@ XA_EXPORT int
 xa_copy_prepare(struct xa_context *ctx,
struct xa_surface *dst, struct xa_surface *src)
 {
-if (src == dst || ctx-srf != NULL)
+if (src == dst)
return -XA_ERR_INVAL;
 
 if (src-tex-format != dst-tex-format) {
-- 
1.8.3.2
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Re: [Mesa-dev] [PATCH 0/8] Radeon various patches

[Michel Dänzer]

On 07.05.2014 22:53, Marek Olšák wrote:
 This patch set mostly contains cosmetic changes that I made while adding 
 support for sample shading.
 
 Marek Olšák (8):
   r600g: simplify framebuffer state size computation
   radeonsi: use DRAW_PREAMBLE on CIK
   radeonsi: remove unused variable exports_ps in si_pipe_shader_ps
   radeonsi: only count CS space for state atoms if we're going to draw
   radeonsi: add and use a helper function for loading constants
   radeon/llvm: add support for non-scalar system values
   radeonsi: simplify depth/stencil export code
   radeonsi: prepare depth export registers at compile time
 
 Please review.

Nice cleanups. This series is

Reviewed-by: Michel Dänzer michel.daen...@amd.com


-- 
Earthling Michel Dänzer|  http://www.amd.com
Libre software enthusiast  |Mesa and X developer
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Re: [Mesa-dev] [PATCH 2/4] i965/Gen8: Set up layer constraints properly for renderbuffers

[Kenneth Graunke]

On 05/07/2014 10:21 PM, Chris Forbes wrote:
 Fixing the same issues the previous commit does for Gen7.
 
 Note that I can't test this one, since I don't have a Broadwell.
 
 Signed-off-by: Chris Forbes chr...@ijw.co.nz
 ---
  src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 +--
  1 file changed, 5 insertions(+), 10 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c 
 b/src/mesa/drivers/dri/i965/gen8_surface_state.c
 index 564d275..6fd0ad4 100644
 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
 +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
 @@ -275,8 +275,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 uint32_t format = 0;
 uint32_t surf_type;
 bool is_array = false;
 -   int depth = MAX2(rb-Depth, 1);
 -   int min_array_element;
 +   int depth = irb-layer_count;

This causes piles of GPU hangs when running Piglit.  One example is:
bin/copyteximage RECT -samples=4 -auto

The problem seems to be that irb-layer_count (and rb-Depth) are 0.
Since we program Depth and Render Target View Extent as (depth - 1) =
-1, and it's treated as an unsigned value, this results in the maximum
number of slices and a bunch of other random bits set.

I think you still need to use MAX2(irb-layer_count, 1) in all four patches.

With that fixed, this patch also fixes Piglit's
spec/ARB_texture_view/clear-into-view-layered on Broadwell.  Oddly, I
didn't see any depth fixes.

With the MAX2 put back in all four patches, the series would get:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

I haven't tested on pre-Gen8.

 +   int min_array_element = irb-mt_layer / MAX2(mt-num_samples, 1);
  
 GLenum gl_target =
rb-TexImage ? rb-TexImage-TexObject-Target : GL_TEXTURE_2D;
 @@ -296,20 +296,15 @@ gen8_update_renderbuffer_surface(struct brw_context 
 *brw,
is_array = true;
depth *= 6;
break;
 +   case GL_TEXTURE_3D:
 +  depth = rb-Depth;
 +  /* fallthrough */
 default:
surf_type = translate_tex_target(gl_target);
is_array = _mesa_tex_target_is_array(gl_target);
break;
 }
  
 -   if (layered) {
 -  min_array_element = 0;
 -   } else if (mt-num_samples  1) {
 -  min_array_element = irb-mt_layer / mt-num_samples;
 -   } else {
 -  min_array_element = irb-mt_layer;
 -   }
 -
 /* _NEW_BUFFERS */
 mesa_format rb_format = _mesa_get_render_format(ctx, 
 intel_rb_format(irb));
 assert(brw_render_target_supported(brw, rb));




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Re: [Mesa-dev] Mixing of hardware and software renderers

[Erik Faye-Lund]

On Tue, May 6, 2014 at 6:51 AM, Patrick McMunn doctorwho...@gmail.com wrote:
 I'm using some older hardware - an ATI Radeon 9200 - which can only handle
 up to OpenGL 1.2. I was wondering if it's possible to use the hardware
 renderer generally and have the driver hand off the handling of functions
 which my video card can't handle (such as functions from a higher OpenGL
 version) to the software render and then the software render hand control
 back to the hardware renderer once it's finished. If this isn't currently
 possible, is this perhaps a feature which might appear in the future?

To add to what others have said, this is not only currently not
possible, but also incredible difficult to do in a standard-compliant
way, because you need to have a software rasterizer that bitwise
matches the result of the GPU. One example where this is needed is
rasterization. If your software rasterizer doesn't provide the exact
same result as the hardware rasterizer, you'll end up with gaps or
overdraw between two adjecent polygons that ended up being using
hardware and software rasterizing. To add to this, OpenGL allows slack
in the rasterization result, and different GPUs rasterize differently.
Matching these things is far from trivial, and requires knowledge
about the hardware implementation that is usually not documented, even
in the vendors' internal documentation. And do note that rasterization
is just one example from a huge array of features that needs to match.

So no, it's just not a feasible task.
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[Mesa-dev] [PATCH] i965: Avoid redundant call to brw_merge_inputs() in brw_try_draw_prims()

[Iago Toral Quiroga]

We always call brw_merge_inputs() right before looping over the primitives but
this can be called inside the loop for each primitive too. In the case we do it
for the first primitive the call is redundant and can be skipped.
---
 src/mesa/drivers/dri/i965/brw_draw.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index fef1c06..ac21656 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -458,15 +458,14 @@ static bool brw_try_draw_prims( struct gl_context *ctx,
   intel_batchbuffer_require_space(brw, estimated_max_prim_size, 
RENDER_RING);
   intel_batchbuffer_save_state(brw);
 
-  if (brw-num_instances != prims[i].num_instances) {
+  if (brw-num_instances != prims[i].num_instances ||
+  brw-basevertex != prims[i].basevertex) {
  brw-num_instances = prims[i].num_instances;
- brw-state.dirty.brw |= BRW_NEW_VERTICES;
- brw_merge_inputs(brw, arrays);
-  }
-  if (brw-basevertex != prims[i].basevertex) {
  brw-basevertex = prims[i].basevertex;
- brw-state.dirty.brw |= BRW_NEW_VERTICES;
- brw_merge_inputs(brw, arrays);
+ if (i  0) { /* For i == 0 we just did this before the loop */
+brw-state.dirty.brw |= BRW_NEW_VERTICES;
+brw_merge_inputs(brw, arrays);
+ }
   }
   if (brw-gen  6)
 brw_set_prim(brw, prims[i]);
-- 
1.9.1

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[Mesa-dev] [Bug 78393] Black zebra like lines while playing games on open source drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78393

--- Comment #2 from Henri Verbeet hverb...@gmail.com ---
It's pretty hard to say anything useful without logs, but one thing that
regularly seems to cause this kind of thing for people is missing S3TC support.

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You are the assignee for the bug.
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Re: [Mesa-dev] [PATCH] st/xa: Fix performance regression introduced by commit Cache render target surface

[Jakob Bornecrantz]

On Thu, May 8, 2014 at 9:15 AM, Thomas Hellstrom thellst...@vmware.com wrote:
 The mentioned commit has the nasty side-effect of turning off accelerated
 copies.

 Cc: 10.1 10.2 mesa-sta...@lists.freedekstop.org
 Signed-off-by: Thomas Hellstrom thellst...@vmware.com
 ---
  src/gallium/state_trackers/xa/xa_context.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Reviewed-by: Jakob Bornecrantz ja...@vmware.com

 diff --git a/src/gallium/state_trackers/xa/xa_context.c 
 b/src/gallium/state_trackers/xa/xa_context.c
 index 37de45b..df3043c 100644
 --- a/src/gallium/state_trackers/xa/xa_context.c
 +++ b/src/gallium/state_trackers/xa/xa_context.c
 @@ -223,7 +223,7 @@ XA_EXPORT int
  xa_copy_prepare(struct xa_context *ctx,
 struct xa_surface *dst, struct xa_surface *src)
  {
 -if (src == dst || ctx-srf != NULL)
 +if (src == dst)
 return -XA_ERR_INVAL;

  if (src-tex-format != dst-tex-format) {
 --
 1.8.3.2
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Re: [Mesa-dev] [PATCH] st/xa: Fix performance regression introduced by commit Cache render target surface

[Jakob Bornecrantz]

On Thu, May 8, 2014 at 9:15 AM, Thomas Hellstrom thellst...@vmware.com wrote:
 The mentioned commit has the nasty side-effect of turning off accelerated
 copies.

 Cc: 10.1 10.2 mesa-sta...@lists.freedekstop.org
 Signed-off-by: Thomas Hellstrom thellst...@vmware.com
 ---
  src/gallium/state_trackers/xa/xa_context.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Jakob Bornecrantz ja...@vmware.com

 diff --git a/src/gallium/state_trackers/xa/xa_context.c 
 b/src/gallium/state_trackers/xa/xa_context.c
 index 37de45b..df3043c 100644
 --- a/src/gallium/state_trackers/xa/xa_context.c
 +++ b/src/gallium/state_trackers/xa/xa_context.c
 @@ -223,7 +223,7 @@ XA_EXPORT int
  xa_copy_prepare(struct xa_context *ctx,
 struct xa_surface *dst, struct xa_surface *src)
  {
 -if (src == dst || ctx-srf != NULL)
 +if (src == dst)
 return -XA_ERR_INVAL;

  if (src-tex-format != dst-tex-format) {
 --
 1.8.3.2
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[Mesa-dev] [PATCH] mesa/st: provide native integers implementation of ir_unop_any

[Ilia Mirkin]

Previously, ir_unop_any was implemented via a dot-product call, which
uses floating point multiplication and addition. The multiplication was
completely pointless, and the addition can just as well be done with an
or. Since we know that the inputs are booleans, they must already be in
canonical 0/~0 format, and the final SNE can also be avoided.

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---

I need to take this through a full piglit run, but the basic tests seem to
work out as expected. This is the result of a compilation of
fs-op-eq-mat4-mat4:

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0..7]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {0., 1., 0., 0.}
  0: MOV TEMP[0].yzw, IMM[0].
  1: FSNE TEMP[1], CONST[4], CONST[0]
  2: OR TEMP[1].x, TEMP[1]., TEMP[1].
  3: OR TEMP[1].y, TEMP[1]., TEMP[1].
  4: OR TEMP[1].x, TEMP[1]., TEMP[1].
  5: FSNE TEMP[2], CONST[5], CONST[1]
  6: OR TEMP[2].x, TEMP[2]., TEMP[2].
  7: OR TEMP[2].y, TEMP[2]., TEMP[2].
  8: OR TEMP[2].x, TEMP[2]., TEMP[2].
  9: FSNE TEMP[3], CONST[6], CONST[2]
 10: OR TEMP[3].x, TEMP[3]., TEMP[3].
 11: OR TEMP[3].y, TEMP[3]., TEMP[3].
 12: OR TEMP[3].x, TEMP[3]., TEMP[3].
 13: FSNE TEMP[4], CONST[7], CONST[3]
 14: OR TEMP[4].x, TEMP[4]., TEMP[4].
 15: OR TEMP[4].y, TEMP[4]., TEMP[4].
 16: OR TEMP[4].x, TEMP[4]., TEMP[4].
 17: OR TEMP[1].x, TEMP[1]., TEMP[4].   ---
 18: OR TEMP[1].x, TEMP[1], TEMP[3].---
 19: OR TEMP[1].x, TEMP[1], TEMP[2].---
 20: NOT TEMP[1].x, TEMP[1].
 21: AND TEMP[0].x, TEMP[1]., IMM[0].
 22: MOV OUT[0], TEMP[0]
 23: END

The three instructions with arrows are the result of my new logic. I wonder if
it's cause for concern that I'm not setting a swizzle mask on the
src... probably a bit, but it works out here. Is there a writemask -
swizzle converter somewhere? The old instructions would have been

DP4 TEMP[1], TEMP[1], TEMP[1]
SNE TEMP[1], TEMP[1], IMM[0] ( == 0.0)

Or something along those lines. While 1 instruction less in TGSI, at least
nv50/nvc0 are scalar and would have had to implement DP4 as

mul
mul-add
mul-add
mul-add

versus the much more scalar-friendly OR's (in addition to the final SNE being
gone).

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 75 --
 1 file changed, 51 insertions(+), 24 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index bdee1f4..2afd8fb 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1671,30 +1671,57 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
case ir_unop_any: {
   assert(ir-operands[0]-type-is_vector());
 
-  /* After the dot-product, the value will be an integer on the
-   * range [0,4].  Zero stays zero, and positive values become 1.0.
-   */
-  glsl_to_tgsi_instruction *const dp =
- emit_dp(ir, result_dst, op[0], op[0],
- ir-operands[0]-type-vector_elements);
-  if (this-prog-Target == GL_FRAGMENT_PROGRAM_ARB 
-  result_dst.type == GLSL_TYPE_FLOAT) {
- /* The clamping to [0,1] can be done for free in the fragment
-  * shader with a saturate.
-  */
- dp-saturate = true;
-  } else if (result_dst.type == GLSL_TYPE_FLOAT) {
- /* Negating the result of the dot-product gives values on the 
range
-  * [-4, 0].  Zero stays zero, and negative values become 1.0.  
This
-  * is achieved using SLT.
-  */
- st_src_reg slt_src = result_src;
- slt_src.negate = ~slt_src.negate;
- emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, 
st_src_reg_for_float(0.0));
-  }
-  else {
- /* Use SNE 0 if integers are being used as boolean values. */
- emit(ir, TGSI_OPCODE_SNE, result_dst, result_src, 
st_src_reg_for_int(0));
+  if (native_integers) {
+ st_src_reg accum = op[0];
+ accum.swizzle = SWIZZLE_;
+ /* OR all the components together, since they should be either 0 or ~0
+  */
+ assert(ir-operands[0]-type-is_boolean());
+ switch (ir-operands[0]-type-vector_elements) {
+ case 4:
+op[0].swizzle = SWIZZLE_;
+emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+accum = st_src_reg(result_dst);
+/* fallthrough */
+ case 3:
+op[0].swizzle = SWIZZLE_;
+emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+accum = st_src_reg(result_dst);
+/* fallthrough */
+ case 2:
+op[0].swizzle = SWIZZLE_;
+emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+break;
+ default:
+assert(!Unexpected vector size);
+

[Mesa-dev] [PATCH] i965: fix size assert for gen7 in brw_init_compaction_tables()

[Samuel Iglesias Gonsalvez]

It should compare with it's own size.

Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
 src/mesa/drivers/dri/i965/brw_eu_compact.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c 
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 3004843..fbee942 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -637,10 +637,10 @@ brw_init_compaction_tables(struct brw_context *brw)
assert(gen6_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0);
assert(gen6_subreg_table[ARRAY_SIZE(gen6_subreg_table) - 1] != 0);
assert(gen6_src_index_table[ARRAY_SIZE(gen6_src_index_table) - 1] != 0);
-   assert(gen7_control_index_table[ARRAY_SIZE(gen6_control_index_table) - 1] 
!= 0);
-   assert(gen7_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0);
-   assert(gen7_subreg_table[ARRAY_SIZE(gen6_subreg_table) - 1] != 0);
-   assert(gen7_src_index_table[ARRAY_SIZE(gen6_src_index_table) - 1] != 0);
+   assert(gen7_control_index_table[ARRAY_SIZE(gen7_control_index_table) - 1] 
!= 0);
+   assert(gen7_datatype_table[ARRAY_SIZE(gen7_datatype_table) - 1] != 0);
+   assert(gen7_subreg_table[ARRAY_SIZE(gen7_subreg_table) - 1] != 0);
+   assert(gen7_src_index_table[ARRAY_SIZE(gen7_src_index_table) - 1] != 0);
 
switch (brw-gen) {
case 7:
-- 
2.0.0.rc0

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Re: [Mesa-dev] odd translation from glsl to tgsi for ir_unop_any_nequal

[Ilia Mirkin]

On Wed, May 7, 2014 at 10:55 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
 On Wed, May 7, 2014 at 8:38 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
 So... this shader (from
 generated_tests/spec/glsl-1.10/execution/built-in-functions/fs-op-eq-mat2-mat2.shader_test):

 uniform mat2 arg0;
 uniform mat2 arg1;

 void main()
 {
   bool result = (arg0 == arg1);
   gl_FragColor = vec4(result, 0.0, 0.0, 0.0);
 }

 Which becomes the following IR:

 (
 (declare (shader_out ) vec4 gl_FragColor)
 (declare (temporary ) vec4 gl_FragColor)
 (declare (uniform ) mat2 arg0)
 (declare (uniform ) mat2 arg1)
 (function main
   (signature void
 (parameters
 )
 (
   (declare (temporary ) vec4 vec_ctor)
   (assign  (yzw) (var_ref vec_ctor)  (constant vec3 (0.0 0.0 0.0)) )
   (declare (temporary ) bvec2 mat_cmp_bvec)
   (assign  (x) (var_ref mat_cmp_bvec)  (expression bool any_nequal
 (array_ref (var_ref arg1) (constant int (0)) ) (array_ref (var_ref
 arg0) (constant int (0)) ) ) )
   (assign  (y) (var_ref mat_cmp_bvec)  (expression bool any_nequal
 (array_ref (var_ref arg1) (constant int (1)) ) (array_ref (var_ref
 arg0) (constant int (1)) ) ) )
   (assign  (x) (var_ref vec_ctor)  (expression float b2f
 (expression bool ! (expression bool any (var_ref mat_cmp_bvec) ) ) ) )
   (assign  (xyzw) (var_ref gl_FragColor)  (var_ref vec_ctor) )
   (assign  (xyzw) (var_ref gl_FragColor@4)  (var_ref gl_FragColor) )
 ))

 )


 When converted to TGS becomes:

 FRAG
 PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
 DCL OUT[0], COLOR
 DCL CONST[0..3]
 DCL TEMP[0..2], LOCAL
 IMM[0] FLT32 {0., 1., 0., 0.}
 IMM[1] INT32 {0, 0, 0, 0}
   0: MOV TEMP[0].yzw, IMM[0].
   1: FSNE TEMP[1].xy, CONST[2].xyyy, CONST[0].xyyy
   2: OR TEMP[1].x, TEMP[1]., TEMP[1].
   3: FSNE TEMP[2].xy, CONST[3].xyyy, CONST[1].xyyy
   4: OR TEMP[2].x, TEMP[2]., TEMP[2].
   5: MOV TEMP[1].y, TEMP[2].
   6: DP2 TEMP[1].x, TEMP[1].xyyy, TEMP[1].xyyy
   7: USNE TEMP[1].x, TEMP[1]., IMM[1].
   8: NOT TEMP[1].x, TEMP[1].
   9: AND TEMP[0].x, TEMP[1]., IMM[0].
  10: MOV OUT[0], TEMP[0]
  11: END

 Note that FSNE/OR are used, implying that the integer version of these
 is expected. However then it goes on to use DP2, which, as I
 understand, does a floating point multiply + add. Now, this _happens_
 to work out, since the integer representations of float 0 and int 0
 are the same, and those are really the only possilibities we care
 about.

 However this seems really dodgy... wouldn't it be clearer to use
 either SNE + OR (which would still work!) + DP2, or alternatively AND
 them all together instead of SNE/DP2? This seems to come in via
 ir_unop_any_nequal. IMO the latter would be better since it keeps

 Erm, sorry -- the email subject and this sentence isn't _quite_
 accurate. That should be ir_unop_any. ir_binop_any_nequal is what
 generates the FSNE/OR' combos. But everything else still holds :)

 things in integer space, and presumably AND's are cheaper than
 fmul/fadd.

 I noticed this because nouveau's codegen logic isn't able to optimize
 this intelligently and I was trying to figure out why.

 Thoughts?

I sent a patch that implements a native integers version of
ir_unop_any: http://patchwork.freedesktop.org/patch/25569/

From the overall symmetry of things, it seems like this was just
forgotten whenever native integer support was added. All the other
any_equal/etc have if (native_integers) do OR+etc else DP2 + etc.

  -ilia
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[Mesa-dev] [Bug 78393] Black zebra like lines while playing games on open source drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78393

--- Comment #3 from incarnated...@gmail.com ---
I just read your other email this morning Michel. I would love to provide but I
do not know how to do that for mesa or bisecting.

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Re: [Mesa-dev] [PATCH] i965: fix size assert for gen7 in brw_init_compaction_tables()

[Eric Anholt]

Samuel Iglesias Gonsalvez sigles...@igalia.com writes:

 It should compare with it's own size.

 Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com

Reviewed-by: Eric Anholt e...@anholt.net


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[Mesa-dev] [Bug 78393] Black zebra like lines while playing games on open source drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78393

--- Comment #4 from incarnated...@gmail.com ---
Holy cow enabling S3TC made it all work!

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[Mesa-dev] [PATCH] egl_dri2: cleanup memory leak in dri2_create_context()

[Emil Velikov]

Cc: Kristian Høgsberg k...@bitplanet.net
Cc: Chad Versace chad.vers...@linux.intel.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 src/egl/drivers/dri2/egl_dri2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 380bd7b..a5f71ed 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -811,8 +811,9 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLConfig *conf,
  api = __DRI_API_GLES3;
  break;
   default:
-_eglError(EGL_BAD_PARAMETER, eglCreateContext);
-return NULL;
+ _eglError(EGL_BAD_PARAMETER, eglCreateContext);
+ free(dri2_ctx);
+ return NULL;
   }
   break;
case EGL_OPENGL_API:
-- 
1.9.2

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Re: [Mesa-dev] [PATCH] i965: Avoid redundant call to brw_merge_inputs() in brw_try_draw_prims()

[Eric Anholt]

Iago Toral Quiroga ito...@igalia.com writes:

 We always call brw_merge_inputs() right before looping over the primitives but
 this can be called inside the loop for each primitive too. In the case we do 
 it
 for the first primitive the call is redundant and can be skipped.

Reviewed-by: Eric Anholt e...@anholt.net

If we had tracked that everything was in VBOs, we could also skip the
brw_merge_input/BRW_NEW_VERTICES entirely, I bet.


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[Mesa-dev] [Bug 78393] Black zebra like lines while playing games on open source drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78393

Alex Deucher ag...@yahoo.com changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |NOTABUG

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[Mesa-dev] [PATCH 2/2] clover: Destory pipe_screen when device does not support compute

[Tom Stellard]

---
 src/gallium/state_trackers/clover/core/device.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 2f84677..70b5caf 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -42,8 +42,10 @@ namespace {
 device::device(clover::platform platform, pipe_loader_device *ldev) :
platform(platform), ldev(ldev) {
pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
-   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
+   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
+  pipe-destroy(pipe);
   throw error(CL_INVALID_DEVICE);
+   }
 }
 
 device::~device() {
-- 
1.8.1.5

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[Mesa-dev] [PATCH 1/2] pipe-loader: Don't destroy the winsys in the sw loader

[Tom Stellard]

The screen takes ownership of the winsys, and is responsible for
destroying it.  Users of pipe-loader should make sure they destory
and  screens they've created to avoid memory leaks.

This fixes a crash in clover introduced by
ce6c17c0833032e91a2d1b34f9eb80c738a854a2 where the pipe-loader was
destroying the winsys while a screen was still using it.
---
 src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index 08d4353..fa317f2 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -145,9 +145,6 @@ pipe_loader_sw_release(struct pipe_loader_device **dev)
 {
struct pipe_loader_sw_device *sdev = pipe_loader_sw_device(*dev);
 
-   if (sdev-ws  sdev-ws-destroy)
-  sdev-ws-destroy(sdev-ws);
-
if (sdev-lib)
   util_dl_close(sdev-lib);
 
-- 
1.8.1.5

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Re: [Mesa-dev] [PATCH 1/2] pipe-loader: Don't destroy the winsys in the sw loader

[Emil Velikov]

On 09/05/14 02:17, Tom Stellard wrote:
 The screen takes ownership of the winsys, and is responsible for
 destroying it.  Users of pipe-loader should make sure they destory
 and  screens they've created to avoid memory leaks.
 
I was under false impression that our current sw screens do not destroy the
winsys.

Cc: 10.2 mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov emil.l.veli...@gmail.com

 This fixes a crash in clover introduced by
 ce6c17c0833032e91a2d1b34f9eb80c738a854a2 where the pipe-loader was
 destroying the winsys while a screen was still using it.
 ---
  src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ---
  1 file changed, 3 deletions(-)
 
 diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
 b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 index 08d4353..fa317f2 100644
 --- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 +++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 @@ -145,9 +145,6 @@ pipe_loader_sw_release(struct pipe_loader_device **dev)
  {
 struct pipe_loader_sw_device *sdev = pipe_loader_sw_device(*dev);
  
 -   if (sdev-ws  sdev-ws-destroy)
 -  sdev-ws-destroy(sdev-ws);
 -
 if (sdev-lib)
util_dl_close(sdev-lib);
  
 

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Re: [Mesa-dev] [PATCH 2/2] clover: Destory pipe_screen when device does not support compute

[Emil Velikov]

On 09/05/14 02:17, Tom Stellard wrote:
 ---
  src/gallium/state_trackers/clover/core/device.cpp | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
 
 diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
 b/src/gallium/state_trackers/clover/core/device.cpp
 index 2f84677..70b5caf 100644
 --- a/src/gallium/state_trackers/clover/core/device.cpp
 +++ b/src/gallium/state_trackers/clover/core/device.cpp
 @@ -42,8 +42,10 @@ namespace {
  device::device(clover::platform platform, pipe_loader_device *ldev) :
 platform(platform), ldev(ldev) {
 pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
 -   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
 +   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
 +  pipe-destroy(pipe);
throw error(CL_INVALID_DEVICE);
 +   }
  }
  
Hi Tom,

AFAICS this will crash when we fail to create the pipe_screen(pipe is NULL).

-Emil
  device::~device() {
 

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Re: [Mesa-dev] [PATCH] egl_dri2: cleanup memory leak in dri2_create_context()

[Kristian Høgsberg]

On Thu, May 8, 2014 at 8:49 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
 Cc: Kristian Høgsberg k...@bitplanet.net
 Cc: Chad Versace chad.vers...@linux.intel.com
 Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
 ---
  src/egl/drivers/dri2/egl_dri2.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Kristian Høgsberg k...@bitplanet.net

 diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
 index 380bd7b..a5f71ed 100644
 --- a/src/egl/drivers/dri2/egl_dri2.c
 +++ b/src/egl/drivers/dri2/egl_dri2.c
 @@ -811,8 +811,9 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, 
 _EGLConfig *conf,
   api = __DRI_API_GLES3;
   break;
default:
 -_eglError(EGL_BAD_PARAMETER, eglCreateContext);
 -return NULL;
 + _eglError(EGL_BAD_PARAMETER, eglCreateContext);
 + free(dri2_ctx);
 + return NULL;
}
break;
 case EGL_OPENGL_API:
 --
 1.9.2

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[Mesa-dev] [PATCH] ilo: destroy the mutex, if winsys creation fails

[Emil Velikov]

Cc: Chia-I Wu olva...@gmail.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
 src/gallium/winsys/intel/drm/intel_drm_winsys.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c 
b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index d34246a..00c4a46 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -181,6 +181,7 @@ intel_winsys_create_for_fd(int fd)
pipe_mutex_init(winsys-mutex);
 
if (!probe_winsys(winsys)) {
+  pipe_mutex_destroy(winsys-mutex);
   drm_intel_bufmgr_destroy(winsys-bufmgr);
   FREE(winsys);
   return NULL;
-- 
1.9.2

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[Mesa-dev] [PATCH] clover: Destory pipe_screen when device does not support compute v2

[Tom Stellard]

v2:
  - Make sure screen was successfully created before destroying it.
---
 src/gallium/state_trackers/clover/core/device.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 2f84677..bc3e3e6 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -42,8 +42,11 @@ namespace {
 device::device(clover::platform platform, pipe_loader_device *ldev) :
platform(platform), ldev(ldev) {
pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
-   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
+   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
+  if (pipe)
+ pipe-destroy(pipe);
   throw error(CL_INVALID_DEVICE);
+   }
 }
 
 device::~device() {
-- 
1.8.1.5

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[Mesa-dev] [PATCH 1/2] pipe-loader: Don't destroy the winsys in the sw loader

[Tom Stellard]

The screen takes ownership of the winsys, and is responsible for
destroying it.  Users of pipe-loader should make sure they destory
and  screens they've created to avoid memory leaks.

This fixes a crash in clover introduced by
ce6c17c0833032e91a2d1b34f9eb80c738a854a2 where the pipe-loader was
destroying the winsys while a screen was still using it.
---
 src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index 08d4353..fa317f2 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -145,9 +145,6 @@ pipe_loader_sw_release(struct pipe_loader_device **dev)
 {
struct pipe_loader_sw_device *sdev = pipe_loader_sw_device(*dev);
 
-   if (sdev-ws  sdev-ws-destroy)
-  sdev-ws-destroy(sdev-ws);
-
if (sdev-lib)
   util_dl_close(sdev-lib);
 
-- 
1.8.1.5

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[Mesa-dev] [PATCH 2/2] clover: Destory pipe_screen when device does not support compute

[Tom Stellard]

---
 src/gallium/state_trackers/clover/core/device.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 2f84677..70b5caf 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -42,8 +42,10 @@ namespace {
 device::device(clover::platform platform, pipe_loader_device *ldev) :
platform(platform), ldev(ldev) {
pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
-   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
+   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
+  pipe-destroy(pipe);
   throw error(CL_INVALID_DEVICE);
+   }
 }
 
 device::~device() {
-- 
1.8.1.5

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[Mesa-dev] [PATCH] clover: Destory pipe_screen when device does not support compute v2

[Tom Stellard]

v2:
  - Make sure screen was successfully created before destroying it.
---
 src/gallium/state_trackers/clover/core/device.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 2f84677..bc3e3e6 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -42,8 +42,11 @@ namespace {
 device::device(clover::platform platform, pipe_loader_device *ldev) :
platform(platform), ldev(ldev) {
pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
-   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
+   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
+  if (pipe)
+ pipe-destroy(pipe);
   throw error(CL_INVALID_DEVICE);
+   }
 }
 
 device::~device() {
-- 
1.8.1.5

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Re: [Mesa-dev] [PATCH 1/2] pipe-loader: Don't destroy the winsys in the sw loader

[Tom Stellard]

On Thu, May 08, 2014 at 11:38:13PM -0400, Tom Stellard wrote:
 The screen takes ownership of the winsys, and is responsible for
 destroying it.  Users of pipe-loader should make sure they destory
 and  screens they've created to avoid memory leaks.
 

I did not mean to send this whole series again.  Please
disregard this.

-Tom

 This fixes a crash in clover introduced by
 ce6c17c0833032e91a2d1b34f9eb80c738a854a2 where the pipe-loader was
 destroying the winsys while a screen was still using it.
 ---
  src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ---
  1 file changed, 3 deletions(-)
 
 diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c 
 b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 index 08d4353..fa317f2 100644
 --- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 +++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
 @@ -145,9 +145,6 @@ pipe_loader_sw_release(struct pipe_loader_device **dev)
  {
 struct pipe_loader_sw_device *sdev = pipe_loader_sw_device(*dev);
  
 -   if (sdev-ws  sdev-ws-destroy)
 -  sdev-ws-destroy(sdev-ws);
 -
 if (sdev-lib)
util_dl_close(sdev-lib);
  
 -- 
 1.8.1.5
 
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Re: [Mesa-dev] [PATCH] clover: Destory pipe_screen when device does not support compute v2

[Francisco Jerez]

Tom Stellard thomas.stell...@amd.com writes:

 v2:
   - Make sure screen was successfully created before destroying it.

Thanks,
Reviewed-by: Francisco Jerez curroje...@riseup.net

 ---
  src/gallium/state_trackers/clover/core/device.cpp | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

 diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
 b/src/gallium/state_trackers/clover/core/device.cpp
 index 2f84677..bc3e3e6 100644
 --- a/src/gallium/state_trackers/clover/core/device.cpp
 +++ b/src/gallium/state_trackers/clover/core/device.cpp
 @@ -42,8 +42,11 @@ namespace {
  device::device(clover::platform platform, pipe_loader_device *ldev) :
 platform(platform), ldev(ldev) {
 pipe = pipe_loader_create_screen(ldev, PIPE_SEARCH_DIR);
 -   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE))
 +   if (!pipe || !pipe-get_param(pipe, PIPE_CAP_COMPUTE)) {
 +  if (pipe)
 + pipe-destroy(pipe);
throw error(CL_INVALID_DEVICE);
 +   }
  }
  
  device::~device() {
 -- 
 1.8.1.5


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Re: [Mesa-dev] [PATCH] egl_dri2: cleanup memory leak in dri2_create_context()

[Chad Versace]

On Thu, May 08, 2014 at 11:06:01AM -0700, Kristian Høgsberg wrote:
 On Thu, May 8, 2014 at 8:49 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
  Cc: Kristian Høgsberg k...@bitplanet.net
  Cc: Chad Versace chad.vers...@linux.intel.com
  Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
  ---
   src/egl/drivers/dri2/egl_dri2.c | 5 +++--
   1 file changed, 3 insertions(+), 2 deletions(-)
 
 Reviewed-by: Kristian Høgsberg k...@bitplanet.net

Reviewed-by: Chad Versace chad.vers...@linux.intel.com 
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Re: [Mesa-dev] [PATCH] mesa/st: provide native integers implementation of ir_unop_any

[Roland Scheidegger]

Am 08.05.2014 15:18, schrieb Ilia Mirkin:
 Previously, ir_unop_any was implemented via a dot-product call, which
 uses floating point multiplication and addition. The multiplication was
 completely pointless, and the addition can just as well be done with an
 or. Since we know that the inputs are booleans, they must already be in
 canonical 0/~0 format, and the final SNE can also be avoided.
 
 Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
 ---
 
 I need to take this through a full piglit run, but the basic tests seem to
 work out as expected. This is the result of a compilation of
 fs-op-eq-mat4-mat4:
 
 FRAG
 PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
 DCL OUT[0], COLOR
 DCL CONST[0..7]
 DCL TEMP[0..4], LOCAL
 IMM[0] FLT32 {0., 1., 0., 0.}
   0: MOV TEMP[0].yzw, IMM[0].
   1: FSNE TEMP[1], CONST[4], CONST[0]
   2: OR TEMP[1].x, TEMP[1]., TEMP[1].
   3: OR TEMP[1].y, TEMP[1]., TEMP[1].
   4: OR TEMP[1].x, TEMP[1]., TEMP[1].
   5: FSNE TEMP[2], CONST[5], CONST[1]
   6: OR TEMP[2].x, TEMP[2]., TEMP[2].
   7: OR TEMP[2].y, TEMP[2]., TEMP[2].
   8: OR TEMP[2].x, TEMP[2]., TEMP[2].
   9: FSNE TEMP[3], CONST[6], CONST[2]
  10: OR TEMP[3].x, TEMP[3]., TEMP[3].
  11: OR TEMP[3].y, TEMP[3]., TEMP[3].
  12: OR TEMP[3].x, TEMP[3]., TEMP[3].
  13: FSNE TEMP[4], CONST[7], CONST[3]
  14: OR TEMP[4].x, TEMP[4]., TEMP[4].
  15: OR TEMP[4].y, TEMP[4]., TEMP[4].
  16: OR TEMP[4].x, TEMP[4]., TEMP[4].
  17: OR TEMP[1].x, TEMP[1]., TEMP[4].   ---
  18: OR TEMP[1].x, TEMP[1], TEMP[3].---
  19: OR TEMP[1].x, TEMP[1], TEMP[2].---
  20: NOT TEMP[1].x, TEMP[1].
  21: AND TEMP[0].x, TEMP[1]., IMM[0].
  22: MOV OUT[0], TEMP[0]
  23: END
 
 The three instructions with arrows are the result of my new logic. I wonder if
 it's cause for concern that I'm not setting a swizzle mask on the
 src... probably a bit, but it works out here. Is there a writemask -
 swizzle converter somewhere? The old instructions would have been
 
 DP4 TEMP[1], TEMP[1], TEMP[1]
 SNE TEMP[1], TEMP[1], IMM[0] ( == 0.0)
 
 Or something along those lines. While 1 instruction less in TGSI, at least
 nv50/nvc0 are scalar and would have had to implement DP4 as
 
 mul
 mul-add
 mul-add
 mul-add
 
 versus the much more scalar-friendly OR's (in addition to the final SNE being
 gone).
 
  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 75 
 --
  1 file changed, 51 insertions(+), 24 deletions(-)
 
 diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
 b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 index bdee1f4..2afd8fb 100644
 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 @@ -1671,30 +1671,57 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
 case ir_unop_any: {
assert(ir-operands[0]-type-is_vector());
  
 -  /* After the dot-product, the value will be an integer on the
 -   * range [0,4].  Zero stays zero, and positive values become 1.0.
 -   */
 -  glsl_to_tgsi_instruction *const dp =
 - emit_dp(ir, result_dst, op[0], op[0],
 - ir-operands[0]-type-vector_elements);
 -  if (this-prog-Target == GL_FRAGMENT_PROGRAM_ARB 
 -  result_dst.type == GLSL_TYPE_FLOAT) {
 -   /* The clamping to [0,1] can be done for free in the fragment
 -* shader with a saturate.
 -*/
 -   dp-saturate = true;
 -  } else if (result_dst.type == GLSL_TYPE_FLOAT) {
 -   /* Negating the result of the dot-product gives values on the 
 range
 -* [-4, 0].  Zero stays zero, and negative values become 1.0.  
 This
 -* is achieved using SLT.
 -*/
 -   st_src_reg slt_src = result_src;
 -   slt_src.negate = ~slt_src.negate;
 -   emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, 
 st_src_reg_for_float(0.0));
 -  }
 -  else {
 - /* Use SNE 0 if integers are being used as boolean values. */
 - emit(ir, TGSI_OPCODE_SNE, result_dst, result_src, 
 st_src_reg_for_int(0));
 +  if (native_integers) {
 + st_src_reg accum = op[0];
 + accum.swizzle = SWIZZLE_;
 + /* OR all the components together, since they should be either 0 or 
 ~0
 +  */
 + assert(ir-operands[0]-type-is_boolean());
 + switch (ir-operands[0]-type-vector_elements) {
 + case 4:
 +op[0].swizzle = SWIZZLE_;
 +emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
 +accum = st_src_reg(result_dst);
 +/* fallthrough */
 + case 3:
 +op[0].swizzle = SWIZZLE_;
 +emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
 +accum = st_src_reg(result_dst);
 +/* fallthrough */
 + case 2:
 +op[0].swizzle = SWIZZLE_;
 +

Re: [Mesa-dev] [PATCH] mesa/st: provide native integers implementation of ir_unop_any

[Marek Olšák]

This looks good to me.

Marek

On Thu, May 8, 2014 at 3:18 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
 Previously, ir_unop_any was implemented via a dot-product call, which
 uses floating point multiplication and addition. The multiplication was
 completely pointless, and the addition can just as well be done with an
 or. Since we know that the inputs are booleans, they must already be in
 canonical 0/~0 format, and the final SNE can also be avoided.

 Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
 ---

 I need to take this through a full piglit run, but the basic tests seem to
 work out as expected. This is the result of a compilation of
 fs-op-eq-mat4-mat4:

 FRAG
 PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
 DCL OUT[0], COLOR
 DCL CONST[0..7]
 DCL TEMP[0..4], LOCAL
 IMM[0] FLT32 {0., 1., 0., 0.}
   0: MOV TEMP[0].yzw, IMM[0].
   1: FSNE TEMP[1], CONST[4], CONST[0]
   2: OR TEMP[1].x, TEMP[1]., TEMP[1].
   3: OR TEMP[1].y, TEMP[1]., TEMP[1].
   4: OR TEMP[1].x, TEMP[1]., TEMP[1].
   5: FSNE TEMP[2], CONST[5], CONST[1]
   6: OR TEMP[2].x, TEMP[2]., TEMP[2].
   7: OR TEMP[2].y, TEMP[2]., TEMP[2].
   8: OR TEMP[2].x, TEMP[2]., TEMP[2].
   9: FSNE TEMP[3], CONST[6], CONST[2]
  10: OR TEMP[3].x, TEMP[3]., TEMP[3].
  11: OR TEMP[3].y, TEMP[3]., TEMP[3].
  12: OR TEMP[3].x, TEMP[3]., TEMP[3].
  13: FSNE TEMP[4], CONST[7], CONST[3]
  14: OR TEMP[4].x, TEMP[4]., TEMP[4].
  15: OR TEMP[4].y, TEMP[4]., TEMP[4].
  16: OR TEMP[4].x, TEMP[4]., TEMP[4].
  17: OR TEMP[1].x, TEMP[1]., TEMP[4].   ---
  18: OR TEMP[1].x, TEMP[1], TEMP[3].---
  19: OR TEMP[1].x, TEMP[1], TEMP[2].---
  20: NOT TEMP[1].x, TEMP[1].
  21: AND TEMP[0].x, TEMP[1]., IMM[0].
  22: MOV OUT[0], TEMP[0]
  23: END

 The three instructions with arrows are the result of my new logic. I wonder if
 it's cause for concern that I'm not setting a swizzle mask on the
 src... probably a bit, but it works out here. Is there a writemask -
 swizzle converter somewhere? The old instructions would have been

 DP4 TEMP[1], TEMP[1], TEMP[1]
 SNE TEMP[1], TEMP[1], IMM[0] ( == 0.0)

 Or something along those lines. While 1 instruction less in TGSI, at least
 nv50/nvc0 are scalar and would have had to implement DP4 as

 mul
 mul-add
 mul-add
 mul-add

 versus the much more scalar-friendly OR's (in addition to the final SNE being
 gone).

  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 75 
 --
  1 file changed, 51 insertions(+), 24 deletions(-)

 diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
 b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 index bdee1f4..2afd8fb 100644
 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
 @@ -1671,30 +1671,57 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
 case ir_unop_any: {
assert(ir-operands[0]-type-is_vector());

 -  /* After the dot-product, the value will be an integer on the
 -   * range [0,4].  Zero stays zero, and positive values become 1.0.
 -   */
 -  glsl_to_tgsi_instruction *const dp =
 - emit_dp(ir, result_dst, op[0], op[0],
 - ir-operands[0]-type-vector_elements);
 -  if (this-prog-Target == GL_FRAGMENT_PROGRAM_ARB 
 -  result_dst.type == GLSL_TYPE_FLOAT) {
 - /* The clamping to [0,1] can be done for free in the fragment
 -  * shader with a saturate.
 -  */
 - dp-saturate = true;
 -  } else if (result_dst.type == GLSL_TYPE_FLOAT) {
 - /* Negating the result of the dot-product gives values on the 
 range
 -  * [-4, 0].  Zero stays zero, and negative values become 1.0.  
 This
 -  * is achieved using SLT.
 -  */
 - st_src_reg slt_src = result_src;
 - slt_src.negate = ~slt_src.negate;
 - emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, 
 st_src_reg_for_float(0.0));
 -  }
 -  else {
 - /* Use SNE 0 if integers are being used as boolean values. */
 - emit(ir, TGSI_OPCODE_SNE, result_dst, result_src, 
 st_src_reg_for_int(0));
 +  if (native_integers) {
 + st_src_reg accum = op[0];
 + accum.swizzle = SWIZZLE_;
 + /* OR all the components together, since they should be either 0 or 
 ~0
 +  */
 + assert(ir-operands[0]-type-is_boolean());
 + switch (ir-operands[0]-type-vector_elements) {
 + case 4:
 +op[0].swizzle = SWIZZLE_;
 +emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
 +accum = st_src_reg(result_dst);
 +/* fallthrough */
 + case 3:
 +op[0].swizzle = SWIZZLE_;
 +emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
 +accum = st_src_reg(result_dst);
 +/* fallthrough */
 + 

[Mesa-dev] [Bug 77493] lp_test_arit fails with llvm = llvm-3.5svn r206094

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77493

--- Comment #2 from Vinson Lee v...@freedesktop.org ---
mesa: 74388dd24bc7fdb9e62ec18096163f5426e03fbf (master 10.3.0-devel)

lp_test_arit is still failing with llvm-3.5.0svn.

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Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] i965: Fix depth (array slices) computation for 1D_ARRAY render targets.

[Chris Forbes]

This won't work correctly with 1D array views which constrain NumLayers.

On Thu, May 8, 2014 at 9:35 AM, Kenneth Graunke kenn...@whitecape.org wrote:
 1D array targets store the number of slices in the Height field.

 Fixes Piglit's spec/!OpenGL 3.2/layered-rendering/clear-color-all-types
 1d_array single_level, at least when used with Meta clears.

 Cc: 10.2 10.1 10.0 mesa-sta...@lists.freedesktop.org
 Signed-off-by: Kenneth Graunke kenn...@whitecape.org
 ---
  src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 ++
  src/mesa/drivers/dri/i965/gen8_surface_state.c| 3 +++
  2 files changed, 5 insertions(+)

 diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c 
 b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
 index d71a1d1..f051024 100644
 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
 +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
 @@ -459,6 +459,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 const uint8_t mocs = GEN7_MOCS_L3;
 GLenum gl_target = rb-TexImage ?
   rb-TexImage-TexObject-Target : GL_TEXTURE_2D;
 +   if (gl_target == GL_TEXTURE_1D_ARRAY)
 +  depth = MAX2(rb-Height, 1);

 uint32_t surf_index =
brw-wm.prog_data-binding_table.render_target_start + unit;
 diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c 
 b/src/mesa/drivers/dri/i965/gen8_surface_state.c
 index 564d275..f00b354 100644
 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
 +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
 @@ -281,6 +281,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 GLenum gl_target =
rb-TexImage ? rb-TexImage-TexObject-Target : GL_TEXTURE_2D;

 +   if (gl_target == GL_TEXTURE_1D_ARRAY)
 +  depth = MAX2(rb-Height, 1);
 +
 uint32_t surf_index =
brw-wm.prog_data-binding_table.render_target_start + unit;

 --
 1.9.2

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[Mesa-dev] [Bug 73846] [llvmpipe] lp_test_format fails with llvm-3.5svn = r199602

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=73846

--- Comment #2 from Vinson Lee v...@freedesktop.org ---
mesa: 74388dd24bc7fdb9e62ec18096163f5426e03fbf (master 10.3.0-devel)
llvm: 3.5.0svn r208355

lp_test_format is still failing with latest mesa and llvm.

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Re: [Mesa-dev] [PATCH] st/xa: Fix performance regression introduced by commit Cache render target surface

[Rob Clark]

On Thu, May 8, 2014 at 3:15 AM, Thomas Hellstrom thellst...@vmware.com wrote:
 The mentioned commit has the nasty side-effect of turning off accelerated
 copies.

 Cc: 10.1 10.2 mesa-sta...@lists.freedekstop.org
 Signed-off-by: Thomas Hellstrom thellst...@vmware.com

Reviewed-by: Rob Clark robdcl...@gmail.com

 ---
  src/gallium/state_trackers/xa/xa_context.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/src/gallium/state_trackers/xa/xa_context.c 
 b/src/gallium/state_trackers/xa/xa_context.c
 index 37de45b..df3043c 100644
 --- a/src/gallium/state_trackers/xa/xa_context.c
 +++ b/src/gallium/state_trackers/xa/xa_context.c
 @@ -223,7 +223,7 @@ XA_EXPORT int
  xa_copy_prepare(struct xa_context *ctx,
 struct xa_surface *dst, struct xa_surface *src)
  {
 -if (src == dst || ctx-srf != NULL)
 +if (src == dst)
 return -XA_ERR_INVAL;

  if (src-tex-format != dst-tex-format) {
 --
 1.8.3.2
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[Mesa-dev] [PATCH 2/3] gallium: replace pipe_type enum with tgsi_type enum

[Brian Paul]

The only place the enum pipe_type was used is for the TGSI sampler
view return type.  So make it a TGSI type.
---
 src/gallium/auxiliary/tgsi/tgsi_build.c|8 
 src/gallium/auxiliary/tgsi/tgsi_strings.c  |3 ++-
 src/gallium/auxiliary/tgsi/tgsi_strings.h  |2 +-
 src/gallium/auxiliary/tgsi/tgsi_text.c |4 ++--
 src/gallium/include/pipe/p_format.h|9 -
 src/gallium/include/pipe/p_shader_tokens.h |   17 +
 6 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c 
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 7621b6a..1e1ae18 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -297,10 +297,10 @@ tgsi_default_declaration_sampler_view(void)
struct tgsi_declaration_sampler_view dsv;
 
dsv.Resource = TGSI_TEXTURE_BUFFER;
-   dsv.ReturnTypeX = PIPE_TYPE_UNORM;
-   dsv.ReturnTypeY = PIPE_TYPE_UNORM;
-   dsv.ReturnTypeZ = PIPE_TYPE_UNORM;
-   dsv.ReturnTypeW = PIPE_TYPE_UNORM;
+   dsv.ReturnTypeX = TGSI_TYPE_UNORM;
+   dsv.ReturnTypeY = TGSI_TYPE_UNORM;
+   dsv.ReturnTypeZ = TGSI_TYPE_UNORM;
+   dsv.ReturnTypeW = TGSI_TYPE_UNORM;
 
return dsv;
 }
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 5b6e47f..e381bda 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -123,7 +123,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
VS_PROHIBIT_UCPS
 };
 
-const char *tgsi_type_names[5] =
+const char *tgsi_type_names[TGSI_TYPE_COUNT] =
 {
UNORM,
SNORM,
@@ -186,6 +186,7 @@ tgsi_strings_check(void)
STATIC_ASSERT(Elements(tgsi_property_names) == TGSI_PROPERTY_COUNT);
STATIC_ASSERT(Elements(tgsi_primitive_names) == PIPE_PRIM_MAX);
STATIC_ASSERT(Elements(tgsi_interpolate_names) == TGSI_INTERPOLATE_COUNT);
+   STATIC_ASSERT(Elements(tgsi_type_names) == TGSI_TYPE_COUNT);
(void) tgsi_processor_type_names;
(void) tgsi_type_names;
(void) tgsi_immediate_type_names;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h 
b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index 3477d50..8214a61 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
@@ -46,7 +46,7 @@ extern const char *tgsi_texture_names[TGSI_TEXTURE_COUNT];
 
 extern const char *tgsi_property_names[TGSI_PROPERTY_COUNT];
 
-extern const char *tgsi_type_names[5];
+extern const char *tgsi_type_names[TGSI_TYPE_COUNT];
 
 extern const char *tgsi_interpolate_names[TGSI_INTERPOLATE_COUNT];
 
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 2b2e7d5..6fbf70c 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1209,7 +1209,7 @@ static boolean parse_declaration( struct translate_ctx 
*ctx )
  ++cur;
  eat_opt_white( cur );
  for (j = 0; j  4; ++j) {
-for (i = 0; i  PIPE_TYPE_COUNT; ++i) {
+for (i = 0; i  TGSI_TYPE_COUNT; ++i) {
if (str_match_nocase_whole(cur, tgsi_type_names[i])) {
   switch (j) {
   case 0:
@@ -1230,7 +1230,7 @@ static boolean parse_declaration( struct translate_ctx 
*ctx )
   break;
}
 }
-if (i == PIPE_TYPE_COUNT) {
+if (i == TGSI_TYPE_COUNT) {
if (j == 0 || j   2) {
   report_error(ctx, Expected type name);
   return FALSE;
diff --git a/src/gallium/include/pipe/p_format.h 
b/src/gallium/include/pipe/p_format.h
index a7fdcd0..b438134 100644
--- a/src/gallium/include/pipe/p_format.h
+++ b/src/gallium/include/pipe/p_format.h
@@ -35,15 +35,6 @@ extern C {
 
 #include p_config.h
 
-enum pipe_type {
-   PIPE_TYPE_UNORM = 0,
-   PIPE_TYPE_SNORM,
-   PIPE_TYPE_SINT,
-   PIPE_TYPE_UINT,
-   PIPE_TYPE_FLOAT,
-   PIPE_TYPE_COUNT
-};
-
 /**
  * Texture/surface image formats (preliminary)
  */
diff --git a/src/gallium/include/pipe/p_shader_tokens.h 
b/src/gallium/include/pipe/p_shader_tokens.h
index d095bd3..bd71bce 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -187,12 +187,21 @@ struct tgsi_declaration_resource {
unsigned Padding : 22;
 };
 
+enum tgsi_type {
+   TGSI_TYPE_UNORM = 0,
+   TGSI_TYPE_SNORM,
+   TGSI_TYPE_SINT,
+   TGSI_TYPE_UINT,
+   TGSI_TYPE_FLOAT,
+   TGSI_TYPE_COUNT
+};
+
 struct tgsi_declaration_sampler_view {
unsigned Resource: 8; /** one of TGSI_TEXTURE_ */
-   unsigned ReturnTypeX : 6; /** one of enum pipe_type */
-   unsigned ReturnTypeY : 6; /** one of enum pipe_type */
-   unsigned ReturnTypeZ : 6; /** one of enum pipe_type */
-   unsigned ReturnTypeW : 6; /** one of enum pipe_type */
+   unsigned ReturnTypeX : 6; /** one of enum tgsi_type */
+   unsigned ReturnTypeY : 6; /** one of enum tgsi_type */
+ 

[Mesa-dev] [PATCH 3/3] gallium: update comment for enum pipe_format

[Brian Paul]

---
 src/gallium/include/pipe/p_format.h |7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/gallium/include/pipe/p_format.h 
b/src/gallium/include/pipe/p_format.h
index b438134..ea16899 100644
--- a/src/gallium/include/pipe/p_format.h
+++ b/src/gallium/include/pipe/p_format.h
@@ -36,13 +36,8 @@ extern C {
 #include p_config.h
 
 /**
- * Texture/surface image formats (preliminary)
+ * Formats for textures, surfaces and vertex data
  */
-
-/* KW: Added lots of surface formats to support vertex element layout
- * definitions, and eventually render-to-vertex-buffer.
- */
-
 enum pipe_format {
PIPE_FORMAT_NONE= 0,
PIPE_FORMAT_B8G8R8A8_UNORM  = 1,
-- 
1.7.10.4

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[Mesa-dev] [PATCH 1/3] tgsi: rename TGSI_TYPE_x - TGSI_OPCODE_TYPE_x

[Brian Paul]

To avoid conflicts with coming TGSI_TYPE_x enums.
---
 src/gallium/auxiliary/gallivm/lp_bld_tgsi.c|   26 +-
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c|   54 ++--
 src/gallium/auxiliary/tgsi/tgsi_info.c |   14 ++---
 src/gallium/auxiliary/tgsi/tgsi_info.h |   12 ++---
 src/gallium/drivers/ilo/shader/toy_tgsi.c  |   12 ++---
 src/gallium/drivers/radeon/radeon_llvm.h   |8 +--
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|8 +--
 7 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index 51cb54c..9464348 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -315,15 +315,15 @@ lp_build_emit_fetch(
 
if (reg-Register.Absolute) {
   switch (stype) {
-  case TGSI_TYPE_FLOAT:
-  case TGSI_TYPE_DOUBLE:
-  case TGSI_TYPE_UNTYPED:
+  case TGSI_OPCODE_TYPE_FLOAT:
+  case TGSI_OPCODE_TYPE_DOUBLE:
+  case TGSI_OPCODE_TYPE_UNTYPED:
   /* modifiers on movs assume data is float */
  res = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ABS, res);
  break;
-  case TGSI_TYPE_UNSIGNED:
-  case TGSI_TYPE_SIGNED:
-  case TGSI_TYPE_VOID:
+  case TGSI_OPCODE_TYPE_UNSIGNED:
+  case TGSI_OPCODE_TYPE_SIGNED:
+  case TGSI_OPCODE_TYPE_VOID:
   default:
  /* abs modifier is only legal on floating point types */
  assert(0);
@@ -333,20 +333,20 @@ lp_build_emit_fetch(
 
if (reg-Register.Negate) {
   switch (stype) {
-  case TGSI_TYPE_FLOAT:
-  case TGSI_TYPE_UNTYPED:
+  case TGSI_OPCODE_TYPE_FLOAT:
+  case TGSI_OPCODE_TYPE_UNTYPED:
  /* modifiers on movs assume data is float */
  res = lp_build_negate( bld_base-base, res );
  break;
-  case TGSI_TYPE_DOUBLE:
+  case TGSI_OPCODE_TYPE_DOUBLE:
  /* no double build context */
  assert(0);
  break;
-  case TGSI_TYPE_SIGNED:
-  case TGSI_TYPE_UNSIGNED:
+  case TGSI_OPCODE_TYPE_SIGNED:
+  case TGSI_OPCODE_TYPE_UNSIGNED:
  res = lp_build_negate( bld_base-int_bld, res );
  break;
-  case TGSI_TYPE_VOID:
+  case TGSI_OPCODE_TYPE_VOID:
   default:
  assert(0);
  break;
@@ -381,7 +381,7 @@ lp_build_emit_fetch_texoffset(
struct tgsi_full_src_register reg;
unsigned swizzle;
LLVMValueRef res;
-   enum tgsi_opcode_type stype = TGSI_TYPE_SIGNED;
+   enum tgsi_opcode_type stype = TGSI_OPCODE_TYPE_SIGNED;
 
/* convert offset register to ordinary register so can use normal emit 
funcs */
memset(reg, 0, sizeof(reg));
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 2b47fc2..4bf9f23 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1148,18 +1148,18 @@ stype_to_fetch(struct lp_build_tgsi_context * bld_base,
struct lp_build_context *bld_fetch;
 
switch (stype) {
-   case TGSI_TYPE_FLOAT:
-   case TGSI_TYPE_UNTYPED:
+   case TGSI_OPCODE_TYPE_FLOAT:
+   case TGSI_OPCODE_TYPE_UNTYPED:
   bld_fetch = bld_base-base;
   break;
-   case TGSI_TYPE_UNSIGNED:
+   case TGSI_OPCODE_TYPE_UNSIGNED:
   bld_fetch = bld_base-uint_bld;
   break;
-   case TGSI_TYPE_SIGNED:
+   case TGSI_OPCODE_TYPE_SIGNED:
   bld_fetch = bld_base-int_bld;
   break;
-   case TGSI_TYPE_VOID:
-   case TGSI_TYPE_DOUBLE:
+   case TGSI_OPCODE_TYPE_VOID:
+   case TGSI_OPCODE_TYPE_DOUBLE:
default:
   assert(0);
   bld_fetch = NULL;
@@ -1275,7 +1275,7 @@ emit_fetch_constant(
   res = lp_build_broadcast_scalar(bld_base-base, scalar);
}
 
-   if (stype == TGSI_TYPE_SIGNED || stype == TGSI_TYPE_UNSIGNED) {
+   if (stype == TGSI_OPCODE_TYPE_SIGNED || stype == TGSI_OPCODE_TYPE_UNSIGNED) 
{
   struct lp_build_context *bld_fetch = stype_to_fetch(bld_base, stype);
   res = LLVMBuildBitCast(builder, res, bld_fetch-vec_type, );
}
@@ -1336,9 +1336,9 @@ emit_fetch_immediate(
   res = bld-immediates[reg-Register.Index][swizzle];
}
 
-   if (stype == TGSI_TYPE_UNSIGNED) {
+   if (stype == TGSI_OPCODE_TYPE_UNSIGNED) {
   res = LLVMBuildBitCast(builder, res, bld_base-uint_bld.vec_type, );
-   } else if (stype == TGSI_TYPE_SIGNED) {
+   } else if (stype == TGSI_OPCODE_TYPE_SIGNED) {
   res = LLVMBuildBitCast(builder, res, bld_base-int_bld.vec_type, );
}
return res;
@@ -1393,9 +1393,9 @@ emit_fetch_input(
 
assert(res);
 
-   if (stype == TGSI_TYPE_UNSIGNED) {
+   if (stype == TGSI_OPCODE_TYPE_UNSIGNED) {
   res = LLVMBuildBitCast(builder, res, bld_base-uint_bld.vec_type, );
-   } else if (stype == TGSI_TYPE_SIGNED) {
+   } else if (stype == TGSI_OPCODE_TYPE_SIGNED) {
   res = LLVMBuildBitCast(builder, res, bld_base-int_bld.vec_type, 

[Mesa-dev] [PATCH] glsl: Rename linker's is_varying_var

[Chris Forbes]

Both the ast-IR and linker have functions with this name, but different
behavior.

Rename the linker's version to var_counts_against_varying_limit to be
closer to what it is actually used for.

Suggested by Ian a while back.

Signed-off-by: Chris Forbes chr...@ijw.co.nz
---

Note that there's actually a bug lurking in here -- check_against_output_limit 
won't actually count anything, since it requires var-data.mode == 
ir_var_shader_out and stage != MESA_SHADER_FRAGMENT.

 src/glsl/link_varyings.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp
index ac38a2f..71998df 100644
--- a/src/glsl/link_varyings.cpp
+++ b/src/glsl/link_varyings.cpp
@@ -992,7 +992,7 @@ varying_matches::match_comparator(const void *x_generic, 
const void *y_generic)
  * varyings, but excludes variables such as gl_FrontFacing and gl_FragCoord.
  */
 static bool
-is_varying_var(gl_shader_stage stage, const ir_variable *var)
+var_counts_against_varying_limit(gl_shader_stage stage, const ir_variable *var)
 {
/* Only fragment shaders will take a varying variable as an input */
if (stage == MESA_SHADER_FRAGMENT 
@@ -1462,7 +1462,7 @@ check_against_output_limit(struct gl_context *ctx,
   ir_variable *const var = ((ir_instruction *) node)-as_variable();
 
   if (var  var-data.mode == ir_var_shader_out 
-  is_varying_var(producer-Stage, var)) {
+  var_counts_against_varying_limit(producer-Stage, var)) {
  output_vectors += var-type-count_attribute_slots();
   }
}
@@ -1501,7 +1501,7 @@ check_against_input_limit(struct gl_context *ctx,
   ir_variable *const var = ((ir_instruction *) node)-as_variable();
 
   if (var  var-data.mode == ir_var_shader_in 
-  is_varying_var(consumer-Stage, var)) {
+  var_counts_against_varying_limit(consumer-Stage, var)) {
  input_vectors += var-type-count_attribute_slots();
   }
}
-- 
1.9.2

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[Mesa-dev] [PATCH 1/2] configure.ac: Add LLVM_VERSION_PATCH to DEFINES

[Tom Stellard]

---
 configure.ac | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index d6f21ea..c68db00 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1605,6 +1605,12 @@ if test x$enable_gallium_llvm = xyes; then
 AC_COMPUTE_INT([LLVM_VERSION_MINOR], [LLVM_VERSION_MINOR],
 [#include ${LLVM_INCLUDEDIR}/llvm/Config/llvm-config.h])
 
+dnl In LLVM 3.4.1 patch level was defined in config.h and not
+dnl llvm-config.h
+AC_COMPUTE_INT([LLVM_VERSION_PATCH], [LLVM_VERSION_PATCH],
+[#include ${LLVM_INCLUDEDIR}/llvm/Config/config.h],
+LLVM_VERSION_PATCH=0) dnl Default if LLVM_VERSION_PATCH not found
+
 if test -n ${LLVM_VERSION_MAJOR}; then
 LLVM_VERSION_INT=${LLVM_VERSION_MAJOR}0${LLVM_VERSION_MINOR}
 else
@@ -1627,7 +1633,7 @@ if test x$enable_gallium_llvm = xyes; then
 LLVM_COMPONENTS=${LLVM_COMPONENTS} option
 fi
 fi
-DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
+DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT 
-DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH
 MESA_LLVM=1
 
 dnl Check for Clang internal headers
-- 
1.8.1.5

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[Mesa-dev] [PATCH 2/2] radeonsi: Enable geometry shaders with LLVM 3.4.1

[Tom Stellard]

---

I tested this patch with LLVM 3.4, 3.4.1, and 3.5 and observed the
correct behavior for all three versions.

 src/gallium/drivers/radeonsi/si_descriptors.c |  4 ++--
 src/gallium/drivers/radeonsi/si_pipe.c|  4 ++--
 src/gallium/drivers/radeonsi/si_pipe.h|  4 
 src/gallium/drivers/radeonsi/si_state.c   | 10 +-
 4 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 0c58d5f..77bc034 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -152,7 +152,7 @@ static void si_update_descriptors(struct si_context *sctx,
7 + /* copy */
(4 + desc-element_dw_size) * 
util_bitcount(desc-dirty_mask) + /* update */
4; /* pointer update */
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
if (desc-shader_userdata_reg = 
R_00B130_SPI_SHADER_USER_DATA_VS_0 
desc-shader_userdata_reg  
R_00B230_SPI_SHADER_USER_DATA_GS_0)
desc-atom.num_dw += 4; /* second pointer update */
@@ -177,7 +177,7 @@ static void si_emit_shader_pointer(struct si_context *sctx,
radeon_emit(cs, va);
radeon_emit(cs, va  32);
 
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
if (desc-shader_userdata_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 
desc-shader_userdata_reg  R_00B230_SPI_SHADER_USER_DATA_GS_0) {
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 24068e3..fc84bda 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -225,7 +225,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
return 4;
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
-   return HAVE_LLVM = 0x0305 ? 330 : 140;
+   return (LLVM_SUPPORTS_GEOM_SHADERS) ? 330 : 140;
 
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen-b.info.vram_size, 0x);
@@ -308,7 +308,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, 
unsigned shader, enu
case PIPE_SHADER_VERTEX:
break;
case PIPE_SHADER_GEOMETRY:
-#if HAVE_LLVM  0x0305
+#if !(LLVM_SUPPORTS_GEOM_SHADERS)
return 0;
 #endif
break;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index a74bbcf..4a5f291 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -39,6 +39,10 @@
 
 #define SI_MAX_DRAW_CS_DWORDS 18
 
+#define LLVM_SUPPORTS_GEOM_SHADERS \
+   ((HAVE_LLVM = 0x0305) || \
+   (HAVE_LLVM == 0x0304  LLVM_VERSION_PATCH = 1))
+
 struct si_pipe_compute;
 
 struct si_screen {
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index d25dc60..ab846b8 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2174,7 +2174,7 @@ static void *si_create_fs_state(struct pipe_context *ctx,
return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 }
 
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
 
 static void *si_create_gs_state(struct pipe_context *ctx,
const struct pipe_shader_state *state)
@@ -2204,7 +2204,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, 
void *state)
sctx-vs_shader = sel;
 }
 
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
 
 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
 {
@@ -2272,7 +2272,7 @@ static void si_delete_vs_shader(struct pipe_context *ctx, 
void *state)
si_delete_shader_selector(ctx, sel);
 }
 
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
 
 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
 {
@@ -2769,7 +2769,7 @@ static void si_bind_vs_sampler_states(struct pipe_context 
*ctx, unsigned count,
si_set_sampler_states(sctx, pm4, count, states,
  sctx-samplers[PIPE_SHADER_VERTEX],
  R_00B130_SPI_SHADER_USER_DATA_VS_0);
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
si_set_sampler_states(sctx, pm4, count, states,
  sctx-samplers[PIPE_SHADER_VERTEX],
  R_00B330_SPI_SHADER_USER_DATA_ES_0);
@@ -3001,7 +3001,7 @@ void si_init_state_functions(struct si_context *sctx)
sctx-b.b.bind_fs_state = si_bind_ps_shader;
sctx-b.b.delete_vs_state = si_delete_vs_shader;
sctx-b.b.delete_fs_state = si_delete_ps_shader;
-#if HAVE_LLVM = 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
sctx-b.b.create_gs_state = si_create_gs_state;

[Mesa-dev] [PATCH] i965: Fix GPU hangs on Broadwell in shaders with some control flow.

[Kenneth Graunke]

According to the documentation, we need to set the source 0 register
type to IMM for flow control instructions that have both JIP and UIP.

Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

Cc: 10.2 mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
 src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp 
b/src/mesa/drivers/dri/i965/gen8_generator.cpp
index dd434a7..faca9c0 100644
--- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
@@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate)
 {
gen8_instruction *inst = next_inst(BRW_OPCODE_IF);
gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
+   gen8_set_src0(brw, inst, brw_imm_d(0));
gen8_set_exec_size(inst, default_state.exec_size);
gen8_set_pred_control(inst, predicate);
gen8_set_mask_control(inst, BRW_MASK_ENABLE);
@@ -435,6 +436,7 @@ gen8_generator::ELSE()
 {
gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE);
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+   gen8_set_src0(brw, inst, brw_imm_d(0));
gen8_set_mask_control(inst, BRW_MASK_ENABLE);
push_if_stack(inst);
return inst;
@@ -456,6 +458,7 @@ gen8_generator::ENDIF()
 
gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF);
gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE);
+   gen8_set_src0(brw, endif_inst, brw_imm_d(0));
patch_IF_ELSE(if_inst, else_inst, endif_inst);
 
return endif_inst;
@@ -577,8 +580,7 @@ gen8_generator::BREAK()
 {
gen8_instruction *inst = next_inst(BRW_OPCODE_BREAK);
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-   gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-   gen8_set_src1(brw, inst, brw_imm_d(0));
+   gen8_set_src0(brw, inst, brw_imm_d(0));
gen8_set_exec_size(inst, default_state.exec_size);
return inst;
 }
@@ -588,8 +590,7 @@ gen8_generator::CONTINUE()
 {
gen8_instruction *inst = next_inst(BRW_OPCODE_CONTINUE);
gen8_set_dst(brw, inst, brw_ip_reg());
-   gen8_set_src0(brw, inst, brw_ip_reg());
-   gen8_set_src1(brw, inst, brw_imm_d(0));
+   gen8_set_src0(brw, inst, brw_imm_d(0));
gen8_set_exec_size(inst, default_state.exec_size);
return inst;
 }
@@ -601,8 +602,7 @@ gen8_generator::WHILE()
gen8_instruction *while_inst = next_inst(BRW_OPCODE_WHILE);
 
gen8_set_dst(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-   gen8_set_src0(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-   gen8_set_src1(brw, while_inst, brw_imm_ud(0));
+   gen8_set_src0(brw, while_inst, brw_imm_d(0));
gen8_set_jip(while_inst, 16 * (do_inst - while_inst));
gen8_set_exec_size(while_inst, default_state.exec_size);
 
@@ -614,7 +614,7 @@ gen8_generator::HALT()
 {
gen8_instruction *inst = next_inst(BRW_OPCODE_HALT);
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-   gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+   gen8_set_src0(brw, inst, brw_imm_d(0));
gen8_set_exec_size(inst, default_state.exec_size);
gen8_set_mask_control(inst, BRW_MASK_DISABLE);
return inst;
-- 
1.9.1

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Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] i965: Fix depth (array slices) computation for 1D_ARRAY render targets.

[Kenneth Graunke]

On 05/08/2014 02:48 PM, Chris Forbes wrote:
 This won't work correctly with 1D array views which constrain NumLayers.

Right, and I guess your change to use irb-num_layers makes this
irrelevant.  I already pushed it, but feel free to revert it before
pushing your code...

--Ken




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[Mesa-dev] [PATCH v2] mesa/st: provide native integers implementation of ir_unop_any

[Ilia Mirkin]

Previously, ir_unop_any was implemented via a dot-product call, which
uses floating point multiplication and addition. The multiplication was
completely pointless, and the addition can just as well be done with an
or. Since we know that the inputs are booleans, they must already be in
canonical 0/~0 format, and the final SNE can also be avoided.

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---

v1 - v2:
 - set swizzle mask on accum
 - set swizzle mask on op

Roland, Marek, the changes are relatively small compared to v1, but would be
nice to have another look if you don't mind.

Amazingly, only one test failed without those -- glsl-fs-any. All the other
any_*'s don't need this logic because they start out with a FSNE/etc which
takes care of the op's swizzles.

This is what the glsl-fs-any shader looks like:

uniform vec2 args;

void main()
{
bvec2 argsb = bvec2(args);

bvec2 v_true = bvec2(argsb.xx);
bvec2 v_some = bvec2(argsb.xy);
bvec2 v_none = bvec2(argsb.yy);
bool true1 = any(v_true);
bool true2 = any(v_some);
bool false1 = any(v_none);
gl_FragColor = vec4(float(true1), float(true2), float(false1), 0.0);
}

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {0., 1., 0., 0.}
  0: FSNE TEMP[0].xy, CONST[0].xyyy, IMM[0].
  1: MOV TEMP[1].w, IMM[0].
  2: OR TEMP[2].x, TEMP[0]., TEMP[0].
  3: AND TEMP[1].x, TEMP[2]., IMM[0].
  4: OR TEMP[2].x, TEMP[0]., TEMP[0].
  5: AND TEMP[2].x, TEMP[2]., IMM[0].
  6: MOV TEMP[1].y, TEMP[2].
  7: OR TEMP[0].x, TEMP[0]., TEMP[0].
  8: AND TEMP[0].x, TEMP[0]., IMM[0].
  9: MOV TEMP[1].z, TEMP[0].
 10: MOV OUT[0], TEMP[1]
 11: END

Any half-decent optimizing backend should have no trouble removing the or a,
a types of things too, whereas that might have been trickier with a DP2 +
FSNE.

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 100 ++---
 1 file changed, 76 insertions(+), 24 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index bdee1f4..1a37ba9 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1671,30 +1671,82 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
case ir_unop_any: {
   assert(ir-operands[0]-type-is_vector());
 
-  /* After the dot-product, the value will be an integer on the
-   * range [0,4].  Zero stays zero, and positive values become 1.0.
-   */
-  glsl_to_tgsi_instruction *const dp =
- emit_dp(ir, result_dst, op[0], op[0],
- ir-operands[0]-type-vector_elements);
-  if (this-prog-Target == GL_FRAGMENT_PROGRAM_ARB 
-  result_dst.type == GLSL_TYPE_FLOAT) {
- /* The clamping to [0,1] can be done for free in the fragment
-  * shader with a saturate.
-  */
- dp-saturate = true;
-  } else if (result_dst.type == GLSL_TYPE_FLOAT) {
- /* Negating the result of the dot-product gives values on the 
range
-  * [-4, 0].  Zero stays zero, and negative values become 1.0.  
This
-  * is achieved using SLT.
-  */
- st_src_reg slt_src = result_src;
- slt_src.negate = ~slt_src.negate;
- emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, 
st_src_reg_for_float(0.0));
-  }
-  else {
- /* Use SNE 0 if integers are being used as boolean values. */
- emit(ir, TGSI_OPCODE_SNE, result_dst, result_src, 
st_src_reg_for_int(0));
+  if (native_integers) {
+ int dst_swizzle = 0, op0_swizzle, i;
+ st_src_reg accum = op[0];
+
+ op0_swizzle = op[0].swizzle;
+ accum.swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 0),
+   GET_SWZ(op0_swizzle, 0),
+   GET_SWZ(op0_swizzle, 0),
+   GET_SWZ(op0_swizzle, 0));
+ for (i = 0; i  4; i++) {
+if (result_dst.writemask  (1  i)) {
+   dst_swizzle = MAKE_SWIZZLE4(i, i, i, i);
+   break;
+}
+ }
+ assert(i != 4);
+ assert(ir-operands[0]-type-is_boolean());
+
+ /* OR all the components together, since they should be either 0 or ~0
+  */
+ switch (ir-operands[0]-type-vector_elements) {
+ case 4:
+op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 3),
+  GET_SWZ(op0_swizzle, 3),
+  GET_SWZ(op0_swizzle, 3),
+  GET_SWZ(op0_swizzle, 3));
+emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+accum = st_src_reg(result_dst);
+accum.swizzle = dst_swizzle;
+/* 

Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs on Broadwell in shaders with some control flow.

[Matt Turner]

On Thu, May 8, 2014 at 4:44 PM, Kenneth Graunke kenn...@whitecape.org wrote:
 According to the documentation, we need to set the source 0 register
 type to IMM for flow control instructions that have both JIP and UIP.

 Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
 Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

 Cc: 10.2 mesa-sta...@lists.freedesktop.org
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
 Signed-off-by: Kenneth Graunke kenn...@whitecape.org
 ---
  src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

 diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp 
 b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 index dd434a7..faca9c0 100644
 --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 @@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate)
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_IF);
 gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), 
 BRW_REGISTER_TYPE_D)));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_exec_size(inst, default_state.exec_size);
 gen8_set_pred_control(inst, predicate);
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 @@ -435,6 +436,7 @@ gen8_generator::ELSE()
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE);
 gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 push_if_stack(inst);
 return inst;
 @@ -456,6 +458,7 @@ gen8_generator::ENDIF()

 gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF);
 gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE);
 +   gen8_set_src0(brw, endif_inst, brw_imm_d(0));

Else and endif don't have UIP, so they don't need this.

With those hunks removed:

Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs on Broadwell in shaders with some control flow.

[Kenneth Graunke]

On 05/08/2014 05:34 PM, Matt Turner wrote:
 On Thu, May 8, 2014 at 4:44 PM, Kenneth Graunke kenn...@whitecape.org wrote:
 According to the documentation, we need to set the source 0 register
 type to IMM for flow control instructions that have both JIP and UIP.

 Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
 Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

 Cc: 10.2 mesa-sta...@lists.freedesktop.org
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
 Signed-off-by: Kenneth Graunke kenn...@whitecape.org
 ---
  src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

 diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp 
 b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 index dd434a7..faca9c0 100644
 --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 @@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate)
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_IF);
 gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), 
 BRW_REGISTER_TYPE_D)));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_exec_size(inst, default_state.exec_size);
 gen8_set_pred_control(inst, predicate);
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 @@ -435,6 +436,7 @@ gen8_generator::ELSE()
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE);
 gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 push_if_stack(inst);
 return inst;
 @@ -456,6 +458,7 @@ gen8_generator::ENDIF()

 gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF);
 gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE);
 +   gen8_set_src0(brw, endif_inst, brw_imm_d(0));
 
 Else and endif don't have UIP, so they don't need this.
 
 With those hunks removed:
 
 Reviewed-by: Matt Turner matts...@gmail.com

It's probably not necessary, but I figured consistency would be best.
Would it be okay to leave it as is?

--Ken



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Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs on Broadwell in shaders with some control flow.

[Matt Turner]

On Thu, May 8, 2014 at 5:45 PM, Kenneth Graunke kenn...@whitecape.org wrote:
 On 05/08/2014 05:34 PM, Matt Turner wrote:
 On Thu, May 8, 2014 at 4:44 PM, Kenneth Graunke kenn...@whitecape.org 
 wrote:
 According to the documentation, we need to set the source 0 register
 type to IMM for flow control instructions that have both JIP and UIP.

 Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
 Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

 Cc: 10.2 mesa-sta...@lists.freedesktop.org
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
 Signed-off-by: Kenneth Graunke kenn...@whitecape.org
 ---
  src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

 diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp 
 b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 index dd434a7..faca9c0 100644
 --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
 +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
 @@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate)
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_IF);
 gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), 
 BRW_REGISTER_TYPE_D)));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_exec_size(inst, default_state.exec_size);
 gen8_set_pred_control(inst, predicate);
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 @@ -435,6 +436,7 @@ gen8_generator::ELSE()
  {
 gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE);
 gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 +   gen8_set_src0(brw, inst, brw_imm_d(0));
 gen8_set_mask_control(inst, BRW_MASK_ENABLE);
 push_if_stack(inst);
 return inst;
 @@ -456,6 +458,7 @@ gen8_generator::ENDIF()

 gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF);
 gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE);
 +   gen8_set_src0(brw, endif_inst, brw_imm_d(0));

 Else and endif don't have UIP, so they don't need this.

 With those hunks removed:

 Reviewed-by: Matt Turner matts...@gmail.com

 It's probably not necessary, but I figured consistency would be best.
 Would it be okay to leave it as is?

I think applying a work around when it's not needed is confusing.

But whatever.
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Re: [Mesa-dev] [PATCH 1/2] configure.ac: Add LLVM_VERSION_PATCH to DEFINES

[Michel Dänzer]

These changes should also go to stable. With that, both are

Reviewed-by: Michel Dänzer michel.daen...@amd.com


-- 
Earthling Michel Dänzer|  http://www.amd.com
Libre software enthusiast  |Mesa and X developer
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Re: [Mesa-dev] [PATCH 1/2] configure.ac: Add LLVM_VERSION_PATCH to DEFINES

[Michel Dänzer]

On 09.05.2014 11:23, Michel Dänzer wrote:
 
 These changes should also go to stable.

BTW, I mean:

CC: 10.1 10.2 mesa-sta...@lists.freedesktop.org

Otherwise it will only be considered for the 10.2 branch at this point.


-- 
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Libre software enthusiast  |Mesa and X developer
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Re: [Mesa-dev] [PATCH] ilo: destroy the mutex, if winsys creation fails

[Chia-I Wu]

On Fri, May 9, 2014 at 2:09 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
 Cc: Chia-I Wu olva...@gmail.com
 Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-by: Chia-I Wu olva...@gmail.com

 ---
  src/gallium/winsys/intel/drm/intel_drm_winsys.c | 1 +
  1 file changed, 1 insertion(+)

 diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c 
 b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
 index d34246a..00c4a46 100644
 --- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
 +++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
 @@ -181,6 +181,7 @@ intel_winsys_create_for_fd(int fd)
 pipe_mutex_init(winsys-mutex);

 if (!probe_winsys(winsys)) {
 +  pipe_mutex_destroy(winsys-mutex);
drm_intel_bufmgr_destroy(winsys-bufmgr);
FREE(winsys);
return NULL;
 --
 1.9.2




-- 
o...@lunarg.com
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