On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Although the horizontal and vertical alignment fields are ignored here,
0 is a reserved value for them and
On 25/06/15 01:13, Dave Airlie wrote:
-fno-strict-aliasing:with strict aliasing:
libGL.so 699188 699188(no change)
*_dri.so 9575876 9563104(-2772)
Use the size command to get the actual text segment size,
otherwise
Before, we were using a hack where when we converted out of SSA, we set
a parent_instr field of the nir_register to indicate that the register
was actually an SSA value. But in the future, we want to handle SSA
values directly, and right now we're creating an extra nir_register for
everything,
It's now unused.
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 2116f60..b33c9c5 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -565,16 +565,6 @@
On Tue, Jun 23, 2015 at 2:09 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Thu, Jun 18, 2015 at 05:51:37PM -0700, Jason Ekstrand wrote:
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
On Thu, Jun 25, 2015 at 5:08 AM, Marta Lofstedt
marta.lofst...@linux.intel.com wrote:
From: Marta Lofstedt marta.lofst...@intel.com
v4 : only expose GL_ARB_texture_multisample enums
for gles 3.1 and desktop GL.
I was suspicious of this logic. Based on my reading of the code, what
your
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d4cc43d..d94a842 100644
---
From: Dave Airlie airl...@redhat.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeonsi/si_shader.c| 5 +
src/gallium/drivers/radeonsi/si_shader.h| 1 +
src/gallium/drivers/radeonsi/si_state.c | 1 -
On 06/25/2015 02:36 PM, Marek Olšák wrote:
What's the point of drawing a HUD pane if a query cannot be created?
With my series which adds support for global performance counters on
NV50, query_create() may fail if we want to monitor *two* different
query types with the HUD.
This limitation
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #23 from Furkan fal...@gmail.com ---
Still there for me.
I'm using Ubuntu 15.04, Chrome 43.0.2357.130, Linux 4.1, and Mesa
10.7~git1506250730.d1663c~gd~v from oibaf ppa.
--
You are receiving this mail because:
You are the QA
v2: Use macros for HW binding table edits (Topi)
v3: Add Broadwell support.
v4: Make hardware binding table bit definitions even more clearer (Ken)
Cc: kenn...@whitecape.org
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by:
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
execbuffer flags.
v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface
Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots for individual binding table indices. The hardware
accumulates
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Cc: kenn...@whitecape.org
Signed-off-by: Abdiel Janulgue
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Time for another rebase, yet again. My previous patches were getting stale...
Changes since last posting:
- Always inspect the getparam.value in the I915_PARAM_HAS_RESOURCE_STREAMER
ioctl as suggested by Chris Wilson.
___
mesa-dev mailing list
-Original Message-
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
Behalf Of Matt Turner
Sent: Tuesday, June 23, 2015 11:05 PM
To: Marta Lofstedt
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] mesa : NULL check InfoLog
On Tue, Jun 23, 2015 at
This documentation was only written for TEMPs. I agree that TEMP
indexing doesn't necessarily need arrays to work, but INPUT and OUTPUT
indexing always needs them.
Marek
On Thu, Jun 25, 2015 at 1:31 AM, Rob Clark robdcl...@gmail.com wrote:
tgsi.rst currently says:
If no ArrayID is
Hi,
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export LIBGL_ALWAYS_SOFTWARE=1; time glmark2)
For Intel driver, INTEL_NO_HW=1 could be used.
(Do other drivers have something similar?)
-fno-strict-aliasing:
glmark2 Score: 244
real5m34.707s
user11m36.192s
What's the point of drawing a HUD pane if a query cannot be created?
Can we detect this during initialization?
Marek
On Wed, Jun 24, 2015 at 9:26 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:
The HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL
On 25/06/15 14:32, Eero Tamminen wrote:
Hi,
On 06/25/2015 03:53 PM, Davin McCall wrote:
On 25/06/15 12:27, Eero Tamminen wrote:
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export LIBGL_ALWAYS_SOFTWARE=1; time glmark2)
For Intel driver, INTEL_NO_HW=1 could be
Gallium should be alright. We'll let you know if we find a regression,
but I don't think there will be any.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Thu, Jun 25, 2015 at 2:45 AM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Tue, Jun 23, 2015 at 3:34 AM, Iago Toral Quiroga
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #21 from Jose P. lbdkm...@sharklasers.com ---
This seems to have been fixed, I can't see the corruption anymore. I'm using
Chromium 43.0.2357.81 on Ubuntu 14.04 (64-bit) and Mesa 10.7.0-devel
(git-20dca37 2015-06-23 trusty-oibaf-ppa).
I've got 32-bit libs building on 64-bit Ubuntu and Fedora. But I've
found a weird problem.
On Fedora 22, for example, Mesa's make install creates a
/usr/lib/libGL.la file which contains the line:
dependency_libs=' -L/usr/lib -lexpat -L/usr/lib64 /usr/lib64/libglapi.la
-lXext -lXdamage
hmm, well I still think tgsi.rst should get some clarification, if for
no other reason than I misunderstood it (and therefore sooner or later
I guess someone else will too)..
I can take a shot at a doc patch..
BR,
-R
On Thu, Jun 25, 2015 at 8:00 AM, Marek Olšák mar...@gmail.com wrote:
This
Hi Eero,
On 25/06/15 12:27, Eero Tamminen wrote:
Hi,
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export LIBGL_ALWAYS_SOFTWARE=1; time glmark2)
For Intel driver, INTEL_NO_HW=1 could be used.
(Do other drivers have something similar?)
Unfortunately I do not have
Huh I see this went in already, I've noticed a problem and thought to
share it.
Currently program resource list (used by gl api shader queries) is
generated in linker, before backend LinkShader call. What this means is
that it relies on frontend optimization passes to get rid of dead inputs
From: Marta Lofstedt marta.lofst...@intel.com
When a program is compiled, but linking failed the
sh-InfoLog could be NULL. This is expoloited
by OpenGL ES 3.1 conformance tests.
V2: ralloc_strdup shProg-InfoLog
Signed-off-by: Marta Lofstedt marta.lofst...@intel.com
---
Items in the program cache consist of three things: key, the data
representing the instructions and auxiliary data representing
uniform storage. The data consisting of instructions is stored into
a drm buffer object while the key and the auxiliary data reside in
malloced section. Now the cache
Current logic re-writes the same data when existing data is found.
Not that this actually matters at the moment in practice, the
contraint for finding matching data is too severe to ever allow
data to be shared between two items in the cache.
CC: Kenneth Graunke kenn...@whitecape.org
and simplify the interface to take directly the size and to return
the offset. The routine does nothing more than allocate, it doesn't
upload anything.
CC: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
https://bugs.freedesktop.org/show_bug.cgi?id=90264
Boyan Ding stu_...@126.com changed:
What|Removed |Added
CC||stu_...@126.com
--- Comment
Hi,
On 06/25/2015 03:53 PM, Davin McCall wrote:
On 25/06/15 12:27, Eero Tamminen wrote:
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export LIBGL_ALWAYS_SOFTWARE=1; time glmark2)
For Intel driver, INTEL_NO_HW=1 could be used.
(Do other drivers have something
Previously, we were allocating the payload with different sizes per gen and
then figuring out the mlen in the generator based on gen. This meant,
among other things, that the higher level passes knew nothing about it.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 19 ---
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption. Sinc this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
builder.
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
1 file changed, 8
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d1e253a..4f56865 100644
---
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index
This makes things a little simpler, more efficient, and quite a bit more
readable.
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 45 ++--
1 file changed, 23
There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel. Instead, we should be using exec_size.
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp| 6 +++---
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 6e45fa7..aeaa1c4 100644
---
As of now, the width field is no longer used for anything. The width field
seemed like a good idea at the time but is actually entirely redundant
with the instruction's execution size. Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 --
1 file changed, 22 deletions(-)
diff --git
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
Previously we used dst.width but the two *should* be the same.
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git
In that case, feel free to push.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Thu, Jun 25, 2015 at 10:25 PM, Dave Airlie airl...@gmail.com wrote:
On 26 June 2015 at 00:26, Marek Olšák mar...@gmail.com wrote:
Hi Dave,
The change in si_shader_io_get_unique_index can be dropped. The
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott cwabbo...@gmail.com wrote:
It's now unused.
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.h | 10 --
1 file changed, 10 deletions(-)
diff --git
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
(no v4 really needed for the little nitpicks but I forgot to say this)
On 06/25/2015 12:08 PM, Marta Lofstedt wrote:
This are for the V4s.
Marta Lofstedt (6):
mesa/es3.1: enable GL_ARB_shader_image_load_store for gles3.1
mesa/es3.1:
This is a re-send of the series I did a week or two ago to remove the width
field from the fs_reg class. I really didn't want to do a re-send but
there have been enough fixes since then that I thought it was worth
re-sending. Most of these patches have already been reviewed but not all.
02:
On 26 June 2015 at 00:26, Marek Olšák mar...@gmail.com wrote:
Hi Dave,
The change in si_shader_io_get_unique_index can be dropped. The
function is only used for shaders before GS.
Ok okay I was hitting the assert in there for the layer/viewport index cases,
but if the patch you pushed to
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 30 ++
src/mesa/drivers/dri/i965/brw_fs_builder.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 --
src/mesa/drivers/dri/i965/brw_ir_fs.h | 9
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 42
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 58 +--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 143
Shortly, offset() will depend on the builder so we need it moved to some
place where it has access to that.
---
src/mesa/drivers/dri/i965/brw_fs.h| 21 +
src/mesa/drivers/dri/i965/brw_ir_fs.h | 21 -
2 files changed, 21 insertions(+), 21 deletions(-)
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one register.
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
This doesn't affect instructions allocated using the builder.
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
On Thu, Jun 25, 2015 at 4:26 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeonsi/si_shader.c| 5 +
src/gallium/drivers/radeonsi/si_shader.h| 1 +
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott cwabbo...@gmail.com wrote:
We already don't convert constants out of SSA, and in our backend we'd
like to have only one way of saying something is still in SSA.
The one tricky part about this is that we may now leave some undef
instructions
Yes, please! It was nice at the time, but it was always a hack.
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott cwabbo...@gmail.com wrote:
It's no longer used
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.c
On Thu, Jun 25, 2015 at 08:40:33AM -0700, Nanley Chery wrote:
On Thu, Jun 25, 2015 at 12:37 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery nanleych...@gmail.com
wrote:
https://bugs.freedesktop.org/show_bug.cgi?id=9
Bug ID: 9
Summary: [BYT regression]
dEQP-GLES3.functional.shaders.texture_functions.textur
elod.usamplercube_*
Product: Mesa
Version: 10.6
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott cwabbo...@gmail.com wrote:
Before, we would use registers, but set a magical parent_instr field
to indicate that it was actually purely an SSA value (i.e., it wasn't
involved in any phi nodes). Instead, just use SSA values directly, which
lets us
And, you got some shader-db stats:
total instructions in shared programs: 6078991 - 6073118 (-0.10%)
instructions in affected programs: 402221 - 396348 (-1.46%)
helped:1527
HURT: 0
GAINED:8
LOST:
_mesa_strtod and _mesa_strtof are only used from the GLSL compiler and
the ARB_[vertex|fragment]_program code, meaning that the locale doesn't
need to be initialized before the first OpenGL context gets initialized.
So let's use explicit initialization from the one-time init code instead
of
In order to save a small leak if mesa is continously loaded and
unloaded, let's free the locale when the shared object is unloaded.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
---
src/mesa/main/context.c | 12 +++-
src/util/strtod.c | 8
src/util/strtod.h | 3
Add an assert to Verify that the locale has been initialized when
we call strtod. This might help some developers sleep better at
night.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
---
src/util/strtod.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/util/strtod.c
This function only gets called while mesa is unloading, so there's
no potential of racing or multiple calls at the same time. So let's
just get rid of the locking.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
---
src/glsl/glsl_types.cpp | 8
1 file changed, 4 insertions(+), 4
All of these enums are now in use around in the code, so there's no need
to explicitly use them here any more.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
---
src/mesa/main/context.c | 27 ---
1 file changed, 27 deletions(-)
diff --git a/src/mesa/main/context.c
This function is for deleting per-screen resources, and the shader
compiler resources are not of such nature. Besides, dri shouldn't
need to even know about the presence of a shader compiler.
These resources will already be released when mesa gets unloaded,
and that should be sufficient.
There's no point in calling _mesa_destroy_shader_compiler multiple
times on exit; the resources will only be released once anyway.
So let's move the atexit-call into the part that is only called
once.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
---
src/mesa/main/context.c | 7 ++-
1
Back in March[1], I sent a patch porting _mesa_strto[df] to
C rather than C++. I fixed up the patch according to the
criticism, but unfortunately I dropped the ball before I sent
out the result. So here I am, picking it back up!
This time I've taken a deeper dive into the whole init/deinit
of
Wait a moment, how did it fail with si_shader_io_get_unique_index? The
function shouldn't be called for ES with the viewport index, because
ES can't pass the output to GS. If it was called, ignoring the
viewport index in si_llvm_emit_es_epilogue should fix it.
Marek
On Thu, Jun 25, 2015 at 10:29
https://bugs.freedesktop.org/show_bug.cgi?id=91112
Bug ID: 91112
Summary: [HSW/BYT] dEQP-GLES3.functional.uniform_api.random.23
test timeout
Product: Mesa
Version: 10.6
Hardware: x86-64 (AMD64)
OS: Linux
On Thu, Jun 25, 2015 at 4:29 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Thu, Jun 25, 2015 at 4:26 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeonsi/si_shader.c| 5 +
https://bugs.freedesktop.org/show_bug.cgi?id=91106
Julien Isorce julien.iso...@gmail.com changed:
What|Removed |Added
CC|
On 6/24/2015 4:51 AM, Ben Widawsky wrote:
Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev,
and no longer read intel-gfx. I'm probably one of the sensible people to look at
this...
On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote:
Gen8+ supports
On 3 June 2015 at 14:27, Francisco Jerez curroje...@riseup.net wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
Hi Tom,
On 31 March 2015 at 15:29, Francisco Jerez curroje...@riseup.net wrote:
Tom Stellard thomas.stell...@amd.com writes:
v2:
- Only call notification for build errors
Hi gents,
On 9 June 2015 at 14:09, Francisco Jerez curroje...@riseup.net wrote:
Francisco Jerez curroje...@riseup.net writes:
Tapani Pälli tapani.pa...@intel.com writes:
Desktop GLSL 130 and GLSL ES 300 allow sampler array indexing where
index can contain a loop induction variable. This
On Thu, Jun 25, 2015 at 12:37 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Although the horizontal
Hi Dave,
The change in si_shader_io_get_unique_index can be dropped. The
function is only used for shaders before GS.
This looks good, but I've had a different plan for this feature:
I'd like the states to be converted into 2 atoms:
1 r600_atom for all 16 viewports
1 r600_atom for all 16
On Thu, Jun 25, 2015 at 03:19:40PM +0100, Emil Velikov wrote:
On 3 June 2015 at 14:27, Francisco Jerez curroje...@riseup.net wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
Hi Tom,
On 31 March 2015 at 15:29, Francisco Jerez curroje...@riseup.net wrote:
Tom Stellard
On 2015-06-09 22:52, Francisco Jerez wrote:
+
+ if (blocking)
+ hev().wait();
+
hard_event::wait() may fail, so this should probably be done before the
ret_object() call to avoid leaks.
Alright... C++ exceptions are a minefield. :)
Is there any reason you didn't make
the same change
On Thu, Jun 25, 2015 at 12:37 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Although the horizontal
On 2015-05-28 13:04, Grigori Goronzy wrote:
Work-group size should always be aligned to subgroup size; this is a
basic requirement, otherwise some work-items will be no-operation.
It might make sense to refine the value according to a kernel's
resource usage, but that's a possible optimization
On Thu, Jun 25, 2015 at 1:19 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
On Wed, 2015-06-24 at 11:17 -0700, Jason Ekstrand wrote:
On Sat, Jun 20, 2015 at 5:32 AM, Timothy Arceri
t_arc...@yahoo.com.au wrote:
Hi all,
The restrictions in ES make the extension easier to implement so
I
From Muchnick's Advanced Compiler Design and Implementation:
To determine which variables are live at each point in a flowgraph, we
perform a backward data-flow analysis
Previously, we were walking the blocks forwards and updating the livein and
then the liveout. However, the livein calculation
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-06-24 20:07:54, Ben Widawsky wrote:
gen8 had some special restrictions which don't seem to carry over to gen9.
Quoting the spec for SKL:
The Z_Height and Z_Width values must equal those present in
3DSTATE_DEPTH_BUFFER incremented by
Hello list,
The candidate for the Mesa 10.6.1 is now available. Currently we have:
- 22 queued
- 19 nominated (outstanding)
- and 0 rejected (obsolete) patches
The present queue consist of core mesa and glsl patches (amonst which
a Dota2 Reborn bugfix) affecting all dri drivers, nouveau
When binding a layered texture, the layer is already 0. There's no need
to special case this.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On Wed, Jun 24, 2015 at 8:07 PM, Ben Widawsky
benjamin.widaw...@intel.com wrote:
gen8 had some special restrictions which don't seem to carry over to gen9.
Quoting the spec for SKL:
The Z_Height and Z_Width values must equal those present in
3DSTATE_DEPTH_BUFFER incremented by one.
This
This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19.
No Piglit changes on Sandybridge.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 +-
1 file changed, 5
On Thu, Jun 25, 2015 at 10:08 AM, Kenneth Graunke kenn...@whitecape.org wrote:
When binding a layered texture, the layer is already 0. There's no need
to special case this.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 ++-
1
On Thu, Jun 11, 2015 at 09:04:45PM -0700, Jordan Justen wrote:
This field should always be set for gen8. In the bdw PRM, Volume 2d:
Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD
6, Bits 9:0, Number of Threads in GPGPU Thread Group:
This field should not be set to 0
We already don't convert constants out of SSA, and in our backend we'd
like to have only one way of saying something is still in SSA.
The one tricky part about this is that we may now leave some undef
instructions around if they aren't part of a phi-web, so we have to be
more careful about
It's no longer used
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.c | 1 -
src/glsl/nir/nir.h | 8
src/glsl/nir/nir_from_ssa.c | 8
3 files changed, 17 deletions(-)
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index
Before, we would use registers, but set a magical parent_instr field
to indicate that it was actually purely an SSA value (i.e., it wasn't
involved in any phi nodes). Instead, just use SSA values directly, which
lets us get rid of the hack and reduces memory usage since we're not
allocating a
On Thu, Jun 25, 2015 at 4:22 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Thu, Jun 25, 2015 at 5:08 AM, Marta Lofstedt
marta.lofst...@linux.intel.com wrote:
From: Marta Lofstedt marta.lofst...@intel.com
v4 : only expose GL_ARB_texture_multisample enums
for gles 3.1 and desktop GL.
I was
How about if I create a patch which puts the greater than 0 check into
is_power_of_two()?
(value 0) (value (value - 1)) == 0);
Thanks,
Nanley
On Wed, Jun 24, 2015 at 3:22 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Mon, Jun 22, 2015 at 4:02 PM, Nanley Chery nanleych...@gmail.com wrote:
On Thu, Jun 25, 2015 at 2:05 PM, Erik Faye-Lund kusmab...@gmail.com wrote:
This function only gets called while mesa is unloading, so there's
no potential of racing or multiple calls at the same time. So let's
just get rid of the locking.
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
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