Re: [Mesa-dev] [PATCH] amd/addrlib: limit fastcall/regparm to i386

On 22 Oct. 2016 15:51, "Jason Ekstrand" wrote: > > Wait... Why are we building the AMD driver on ARM? I know AMD has been talking about ARM-based servers, but are they actually strapping GPUs to them? PCIE on ARM somewhere. Dave. > > On Fri, Oct 21, 2016 at 1:16 AM,

Re: [Mesa-dev] [PATCH] amd/addrlib: limit fastcall/regparm to i386

Wait... Why are we building the AMD driver on ARM? I know AMD has been talking about ARM-based servers, but are they actually strapping GPUs to them? On Fri, Oct 21, 2016 at 1:16 AM, Nicolai Hähnle wrote: > On 21.10.2016 00:20, Rob Herring wrote: > >> The use of regparm

Re: [Mesa-dev] [PATCH] isl/format: Correct ASTC entries of format info table

Are there separate formats for HDR? I'm not seeing any. I guess since the HDR is a strict superset of LDR, it doesn't make much sense to have separate enums. In any case, thanks for fixing this! Reviewed-by: Jason Ekstrand Helper functions are so much better... On Fri,

[Mesa-dev] [Bug 98172] Concurrent call to glClientWaitSync results in segfault in one of the waiters.

https://bugs.freedesktop.org/show_bug.cgi?id=98172 --- Comment #42 from Suzuki, Shinji --- Sorry for the clutter. Timeout is not handled in the previous attempt. (The use of the shared completion flag seems to have potential synchronization problem because a waiter can

[Mesa-dev] [PATCH V3] i965: rewrite brw_setup_vue_interpolation()

Here brw_setup_vue_interpolation() is rewritten not to use the InterpQualifier array in gl_fragment_program which will allow us to remove it. This change also makes the code which is only used by gen4/5 more self contained as it now has its own gen5_fragment_program struct rather than storing the

[Mesa-dev] [PATCH] isl/format: Correct ASTC entries of format info table

With the isl_format_supports* helpers, we can now conveniently report support for this format on Cherry View. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925 Signed-off-by: Nanley Chery --- src/intel/isl/isl_format.c | 70

[Mesa-dev] [Bug 98308] llvmpipe crashes with glxgears (LTO related)

https://bugs.freedesktop.org/show_bug.cgi?id=98308 --- Comment #13 from Marc Dietrich --- These options fail in src/mapi (fixable by removing them there), but later they generate an internal compiler error, which I can't deal with. I attached my build script. Maybe you can

[Mesa-dev] [Bug 98308] llvmpipe crashes with glxgears (LTO related)

https://bugs.freedesktop.org/show_bug.cgi?id=98308 --- Comment #12 from Marc Dietrich --- Created attachment 127454 --> https://bugs.freedesktop.org/attachment.cgi?id=127454=edit build script -- You are receiving this mail because: You are the assignee for the bug. You are

[Mesa-dev] [PATCH 3/3] i965/gen8: Don't enable alpha test and alpha to coverage if draw bufer zero is integer type

We follow this rule at multiple places in i965 driver. This patch doesn't fix any testcase. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/gen8_blend_state.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 1/3] i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_blend_state()

No functional changes in this patch. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/gen8_blend_state.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c

[Mesa-dev] [PATCH 2/3] i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_ps_blend()

No functional changes in this patch. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/gen8_blend_state.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c

[Mesa-dev] [PATCH] glsl/mesa: remove unused namespace support from the symbol table

Namespace support seems to have been unused for a very long time. Previously the hash table entry was never removed and the symbol name wasn't freed until the symbol table was destroyed. In theory this could reduced the number of times we need to copy a string as duplicate names are reused.

[Mesa-dev] [PATCH] egl/android: implement minimal swap_buffers_with_damage

Since commit 0a606a400fe3 ("egl: add eglSwapBuffersWithDamageKHR"), Android has been broken because the function eglSwapBuffersWithDamageKHR is provided regardless of the extension being present. Also, the Android meta-EGL always advertises the extension regardless of the underlying EGL

Re: [Mesa-dev] [PATCH V2] i965: rewrite brw_setup_vue_interpolation()

On Thu, Oct 20, 2016 at 8:23 PM, Timothy Arceri < timothy.arc...@collabora.com> wrote: > Here brw_setup_vue_interpolation() is rewritten not to use the > InterpQualifier > array in gl_fragment_program which will allow us to remove it. > > This change also makes the code which is only used by

[Mesa-dev] [Bug 96737] [GLX] Xsession Log In breakage - Switch User / Switch To Greeter / VT Switch related

https://bugs.freedesktop.org/show_bug.cgi?id=96737 poma changed: What|Removed |Added Version|12.0|unspecified

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

On Fri, Oct 21, 2016 at 7:31 AM, Mike Lothian wrote: > Does this need to be target CPU rather than host? target and host should always be the same for Mesa, as far as I understand. See https://gcc.gnu.org/onlinedocs/gccint/Configure-Terms.html

Re: [Mesa-dev] [PATCH] radv: allow cmask transitions without fast clear

Reviewed-by: Bas Nieuwenhuizen On Fri, Oct 21, 2016 at 1:36 AM, Dave Airlie wrote: > From: Dave Airlie > > This fixes > dEQP-VK.pipeline.multisample.sampled_image* > > These all render to multisampled image, and then > sample

[Mesa-dev] [PATCH 1/2] vulkan/wsi/x11: fix ARGB window support

Pass the correct depth to xcb_dri3_pixmap_from_buffer_checked(). Otherwise xcb_present_pixmap() fails with a BadMatch error. Cc: "13.0" --- src/vulkan/wsi/wsi_common_x11.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git

Re: [Mesa-dev] [ANNOUNCE] mesa 13.0.0-rc1

On 20 October 2016 at 20:46, Kai Wasserbäch wrote: > Hey Emil, hey Jason, > Emil Velikov wrote on 20.10.2016 17:28: >> On 20 October 2016 at 16:20, Jason Ekstrand wrote: >>> On Oct 20, 2016 8:11 AM, "Emil Velikov"

[Mesa-dev] [PATCH 2/2] vulkan/wsi/wayland: fix ARGB window support

Use an ARGB format for the DRM buffer when the compositeAlpha field in VkSwapchainCreateInfoKHR is set to VK_COMPOSITE_ALPHA_PRE_MULTIPLIED_BIT_KHR. Cc: "13.0" --- src/vulkan/wsi/wsi_common_wayland.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-)

[Mesa-dev] [Bug 98308] llvmpipe crashes with glxgears (LTO related)

https://bugs.freedesktop.org/show_bug.cgi?id=98308 --- Comment #11 from Maciej Cencora --- I thought so. FWIW I cannot reproduce the crash on gcc 6.2. Could you re-compile mesa with -fsanitize=address and -fsanitize=undefined in C/CXX_FLAGS, and paste the output from

Re: [Mesa-dev] [PATCH] nvc0/ir: remove outdated comment about SHLADD

Reviewed-by: Ilia Mirkin On Fri, Oct 21, 2016 at 12:35 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 1 - >

Re: [Mesa-dev] [PATCH 3/3] gallium/hud: protect against and initialization race

On 10/20/2016 08:45 PM, Steven Toth wrote: > In the event that multiple threads attempt to install a graph > concurrently, protect the shared list. > > Signed-off-by: Steven Toth > --- > src/gallium/auxiliary/hud/hud_cpufreq.c | 12 ++-- >

[Mesa-dev] [PATCH] nvc0/ir: remove outdated comment about SHLADD

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 1 - src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 1 - 2 files changed, 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 2/3] gallium/hud: fix a previously allocated handle.

On 10/20/2016 08:45 PM, Steven Toth wrote: > We're missing the closedir() to the matching opendir(). > What about changing the commit title to: "gallium/hud: close a previously opened handle"? Either way: Reviewed-by: Eduardo Lima Mitev > Signed-off-by: Steven Toth

Re: [Mesa-dev] [PATCH 1/3] gallium/hud: fix a problem where objects are free'd while in use.

Didn't test it myself, but looks good: Reviewed-by: Eduardo Lima Mitev On 10/20/2016 08:45 PM, Steven Toth wrote: > Instead of trying to maintain a reference counted list of valid HUD > objects, and freeing them accordingly, creating race conditions > between unanticipated

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

On Fri, Oct 21, 2016 at 9:11 AM, Emil Velikov wrote: > On 21 October 2016 at 16:58, Jason Ekstrand wrote: > > > Will do. Do I need to add intel_icd.@host_cpu@.json to EXTRA_DIST? > > > No need, since new file will/should be regenerated as one

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

On 21 October 2016 at 16:58, Jason Ekstrand wrote: > Will do. Do I need to add intel_icd.@host_cpu@.json to EXTRA_DIST? > No need, since new file will/should be regenerated as one runs configure. >> >> With those the series is: >> Reviewed-by: Emil Velikov

[Mesa-dev] [Bug 98308] llvmpipe crashes with glxgears (LTO related)

https://bugs.freedesktop.org/show_bug.cgi?id=98308 --- Comment #10 from Marc Dietrich --- this only fixes the (unrelated) warning in comment 5, but not the crash in llvmpipe reported in this bug. -- You are receiving this mail because: You are the QA Contact for the bug. You

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

On Fri, Oct 21, 2016 at 7:31 AM, Mike Lothian wrote: > Does this need to be target CPU rather than host? > No, we want host. See also https://www.gnu.org/software/autoconf/manual/autoconf-2.65/html_node/Specifying-Target-Triplets.html > On Fri, 21 Oct 2016 at 14:53 Emil

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

On Fri, Oct 21, 2016 at 6:52 AM, Emil Velikov wrote: > Thank you very very very much for this, Jason ! > If you're happy and I'm happy, I'd say we've got ourselves a solution! > On 21 October 2016 at 01:07, Jason Ekstrand wrote: > > >

Re: [Mesa-dev] [PATCH] nvc0/ir: fix emission of SHLADD with NEG modifiers

Acked-by: Ilia Mirkin Mind double-checking the one in emitIMAD? On Fri, Oct 21, 2016 at 11:43 AM, Samuel Pitoiset wrote: > This affects GF100:GK110 chipsets, but not GM107+ where the > logic is a bit different. The emitters tried to emit sub >

[Mesa-dev] [PATCH] nvc0/ir: fix emission of SHLADD with NEG modifiers

This affects GF100:GK110 chipsets, but not GM107+ where the logic is a bit different. The emitters tried to emit sub instead of subr when src0 has a NEG modifier. This fixes the following piglit tests glsl-fs-loop-nested and glsl-vs-loop-nested. Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH 00/15] GLSL memory allocation rework for faster compilation

On 10/21/2016 04:57 PM, Eero Tamminen wrote: Hi, On 21.10.2016 14:07, Tapani Pälli wrote: I did run some valgrind comparisons with gfxbench4, your branch against Mesa master. I did not spot anything obvious related to ralloc. On i965 there's a huge load of invalid writes's and read's in

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

On Fri, Oct 21, 2016 at 4:41 PM, Roland Scheidegger wrote: > Am 21.10.2016 um 15:17 schrieb Marek Olšák: >> On Oct 21, 2016 12:06 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com >> > wrote: >>> >>> On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák

[Mesa-dev] [Bug 98308] llvmpipe crashes with glxgears (LTO related)

https://bugs.freedesktop.org/show_bug.cgi?id=98308 --- Comment #9 from Maciej Cencora --- Created attachment 127452 --> https://bugs.freedesktop.org/attachment.cgi?id=127452=edit Proposed patch Try this patch. It silences the warning for me on gcc-6.2, but I don't know if

Re: [Mesa-dev] [PATCH v2] egl: add check that eglCreateContext gets a valid config

On Thursday, 2016-10-20 19:46:19 +0100, Emil Velikov wrote: > On 20 October 2016 at 18:20, Tapani Pälli wrote: > > Fixes following dEQP test: > > > >dEQP-EGL.functional.negative_api.create_context > > > > v2: don't break EGL_KHR_no_config_context (Eric Engestrom) > > >

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

Am 21.10.2016 um 15:17 schrieb Marek Olšák: > On Oct 21, 2016 12:06 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com > > wrote: >> >> On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák > wrote: >> > This won't make it faster. >> >>

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

Does this need to be target CPU rather than host? On Fri, 21 Oct 2016 at 14:53 Emil Velikov wrote: > Thank you very very very much for this, Jason ! > > On 21 October 2016 at 01:07, Jason Ekstrand wrote: > > > drivers because they may put it

Re: [Mesa-dev] [PATCH 2/5] nvc0/ir: use levelZero flag when the lod is set to 0

Yeah, it might actually need to be arg+1, -1. I didn't test this patch too thoroughly... On Fri, Oct 21, 2016 at 9:53 AM, Samuel Pitoiset wrote: > This patch breaks a bunch of piglit tests, see a short list below: > > bin/arb_texture_barrier-blending-in-shader 512 42 1

Re: [Mesa-dev] [PATCH 00/15] GLSL memory allocation rework for faster compilation

Hi, On 21.10.2016 14:07, Tapani Pälli wrote: I did run some valgrind comparisons with gfxbench4, your branch against Mesa master. I did not spot anything obvious related to ralloc. On i965 there's a huge load of invalid writes's and read's in general but this happens on master as well so maybe

Re: [Mesa-dev] [PATCH 2/5] nvc0/ir: use levelZero flag when the lod is set to 0

This patch breaks a bunch of piglit tests, see a short list below: bin/arb_texture_barrier-blending-in-shader 512 42 1 128 7 -auto -fbo bin/arb_texture_buffer_object-formats vs core -auto -fbo bin/texelFetch 140 vs sampler2DRect -auto -fbo bin/mesa_pack_invert-readpixels -auto -fbo ... Around

Re: [Mesa-dev] [PATCH 1/3] anv: Suffix the intel_icd file with the host CPU

Thank you very very very much for this, Jason ! On 21 October 2016 at 01:07, Jason Ekstrand wrote: > drivers because they may put it in /usr/local or $HOME/.local or some > other Drop the "/usr/local or " part. The dynamic linker looks in there, by default. > more

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

On Oct 21, 2016 3:23 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com> wrote: > > On Fri, Oct 21, 2016 at 3:17 PM, Marek Olšák wrote: > > On Oct 21, 2016 12:06 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com> wrote: > >> > >> On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák

Re: [Mesa-dev] [PATCH 00/15] GLSL memory allocation rework for faster compilation

On Oct 21, 2016 1:07 PM, "Tapani Pälli" wrote: > > > > On 10/21/2016 12:51 PM, Marek Olšák wrote: >> >> On Fri, Oct 21, 2016 at 6:58 AM, Tapani Pälli wrote: >>> >>> >>> >>> On 10/20/2016 09:24 PM, Marek Olšák wrote: On Thu, Oct 20,

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

On Fri, Oct 21, 2016 at 3:17 PM, Marek Olšák wrote: > On Oct 21, 2016 12:06 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com> wrote: >> >> On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák wrote: >> > This won't make it faster. >> >> Why? > > It's obviously a micro

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

On Oct 21, 2016 12:06 PM, "Jan Ziak" <0xe2.0x9a.0...@gmail.com> wrote: > > On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák wrote: > > This won't make it faster. > > Why? It's obviously a micro optimization that adds more stuff than it benefits the runtime. I don't think that real

Re: [Mesa-dev] [PATCH 3/5] nv50/ir: it appears that OP_DISCARD can't take a join modifier

On 10/21/2016 11:18 AM, Samuel Pitoiset wrote: Reviewed-by: Samuel Pitoiset On 10/21/2016 08:30 AM, Ilia Mirkin wrote: nvdisasm does not print a .S even though the bit is set. Signed-off-by: Ilia Mirkin ---

[Mesa-dev] [Bug 98172] Concurrent call to glClientWaitSync results in segfault in one of the waiters.

https://bugs.freedesktop.org/show_bug.cgi?id=98172 --- Comment #41 from Suzuki, Shinji --- I think now I have better understanding of the problem we are dealing with here. >Not thread safe (race condition on so->fence): > screen->fence_reference(screen, >fence, NULL);

[Mesa-dev] [PATCH] mesa: fix error handling in DrawBuffers

Patch rearranges error checking so that enum checking provided via destmask happens before other checks. It needs to be done in this order because other error checks do not work properly if there were invalid enums passed. Patch also refines one existing check and it's documentation to match GLES

[Mesa-dev] [Bug 98245] GLES3.1 link negative dEQP "expected linking to fail, but passed."

https://bugs.freedesktop.org/show_bug.cgi?id=98245 --- Comment #1 from Iago Toral --- These seem to be two different issues so I think it is probably best to create two different bug reports. I have sent a patch for review that fixes the first one:

[Mesa-dev] [PATCH] glsl: add matrix layout information to interface block types

So far we have been checking that interface block definitions had matching matrix layouts by comparing the definitions of their fields, however, this does not cover the case where the interface blocks are defined with mismatching matrix layouts but don't define any field with a matrix type. In

[Mesa-dev] [Bug 98134] dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.draw_buffers wants a different GL error code

https://bugs.freedesktop.org/show_bug.cgi?id=98134 --- Comment #3 from Tapani Pälli --- (In reply to Tapani Pälli from comment #2) > Created attachment 127094 [details] [review] > fix > > This patch fixes the test. These tests fail in CI though: > >

Re: [Mesa-dev] [PATCH 00/15] GLSL memory allocation rework for faster compilation

On 10/21/2016 12:51 PM, Marek Olšák wrote: On Fri, Oct 21, 2016 at 6:58 AM, Tapani Pälli wrote: On 10/20/2016 09:24 PM, Marek Olšák wrote: On Thu, Oct 20, 2016 at 6:31 PM, Tapani Pälli wrote: On 10/20/2016 06:55 PM, Marek Olšák wrote:

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

On Fri, Oct 21, 2016 at 12:04 PM, Marek Olšák wrote: > This won't make it faster. Why? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

NAK. This won't make it faster. Marek On Fri, Oct 21, 2016 at 11:58 AM, Jan Ziak <0xe2.0x9a.0...@gmail.com> wrote: > st_validate_state() shows up in benchmarks. This patch makes it a little bit > faster in 64-bit mode. > > Signed-off-by: Jan Ziak (http://atom-symbol.net)

[Mesa-dev] [PATCH] st/mesa: use u_bit_scan64() on 64-bit CPUs

st_validate_state() shows up in benchmarks. This patch makes it a little bit faster in 64-bit mode. Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com> --- src/mesa/state_tracker/st_atom.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-)

Re: [Mesa-dev] [PATCH 00/15] GLSL memory allocation rework for faster compilation

On Fri, Oct 21, 2016 at 6:58 AM, Tapani Pälli wrote: > > > On 10/20/2016 09:24 PM, Marek Olšák wrote: >> >> On Thu, Oct 20, 2016 at 6:31 PM, Tapani Pälli >> wrote: >>> >>> On 10/20/2016 06:55 PM, Marek Olšák wrote: On Mon, Oct 17,

Re: [Mesa-dev] [PATCH] gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS

Reviewed-by: Marek Olšák Marek On Fri, Oct 21, 2016 at 9:07 AM, Ilia Mirkin wrote: > This allows the driver to signal that it can't handle random > interleaving of attributes across buffers. This is required for > ARB_transform_feedback3, and it's

Re: [Mesa-dev] [PATCH] st/mesa: cleanup and fix primitive restart for indirect draws

Reviewed-by: Marek Olšák Marek On Fri, Oct 21, 2016 at 10:18 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > There are three intended functional changes here: > > 1. OpenGL 4.5 clarifies that primitive restart should only

Re: [Mesa-dev] [PATCH 3/5] nv50/ir: it appears that OP_DISCARD can't take a join modifier

Reviewed-by: Samuel Pitoiset On 10/21/2016 08:30 AM, Ilia Mirkin wrote: nvdisasm does not print a .S even though the bit is set. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1

Re: [Mesa-dev] [PATCH 2/5] nvc0/ir: use levelZero flag when the lod is set to 0

Reviewed-by: Samuel Pitoiset On 10/21/2016 08:30 AM, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 9 + 1 file changed, 9 insertions(+) diff --git

Re: [Mesa-dev] [PATCH 1/5] nv50/ir: use levelZero for non-frag tex/txp ops

Reviewed-by: Samuel Pitoiset On 10/21/2016 08:30 AM, Ilia Mirkin wrote: radeonsi also does the same thing. I suspect that this is likely to be a no-op in reality, but it brings nouveau code closer to what the blob produces. Plus it makes sense to not try to do

Re: [Mesa-dev] [PATCH] gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS

On 21.10.2016 09:07, Ilia Mirkin wrote: This allows the driver to signal that it can't handle random interleaving of attributes across buffers. This is required for ARB_transform_feedback3, and it's initialized to whatever the previous value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for

[Mesa-dev] [PATCH] st/mesa: cleanup and fix primitive restart for indirect draws

From: Nicolai Hähnle There are three intended functional changes here: 1. OpenGL 4.5 clarifies that primitive restart should only apply with index buffers, so make that change explicit in the indirect draw path. 2. Make PrimitiveRestartFixedIndex work with indirect

Re: [Mesa-dev] [PATCH] amd/addrlib: limit fastcall/regparm to i386

On 21.10.2016 00:20, Rob Herring wrote: The use of regparm causes an error on arm/arm64 builds with clang. fastcall is allowed, but still throws a warning. As both options only have effect on 32-bit x86 builds, limit them to that case. While we haven't been particularly good at syncing things

Re: [Mesa-dev] [PATCH 7/7] tgsi/scan: scan texture offset operands

I don't feel so happy about adding the scans that don't have a clear plan of use. I see how the scan for atomic access could be interesting though. Anyway, the changes themselves look fine, so for the series: Reviewed-by: Nicolai Hähnle On 20.10.2016 20:08, Marek

[Mesa-dev] [PATCH] gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS

This allows the driver to signal that it can't handle random interleaving of attributes across buffers. This is required for ARB_transform_feedback3, and it's initialized to whatever the previous value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for nv50 where it is disabled. Note that the

Re: [Mesa-dev] [PATCH] radv: allow cmask transitions without fast clear

Acked-by: Edward O'Callaghan On 10/21/2016 10:36 AM, Dave Airlie wrote: > From: Dave Airlie > > This fixes > dEQP-VK.pipeline.multisample.sampled_image* > > These all render to multisampled image, and then > sample from it, so we must

Re: [Mesa-dev] [PATCH 5/5] nv50/ir: detect when a SLCT is equivalent to a SET

On Fri, Oct 21, 2016 at 2:39 AM, Karol Herbst wrote: > > > On 21 October 2016 8:30:33 a.m. GMT+02:00, Ilia Mirkin > wrote: >>Signed-off-by: Ilia Mirkin >>--- >>.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23

Re: [Mesa-dev] [PATCH 5/5] nv50/ir: detect when a SLCT is equivalent to a SET

On 21 October 2016 8:30:33 a.m. GMT+02:00, Ilia Mirkin wrote: >Signed-off-by: Ilia Mirkin >--- >.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23 >++ > 1 file changed, 19 insertions(+), 4 deletions(-) > >diff --git

Re: [Mesa-dev] [PATCH v2.1] i965/gen7: expose OpenGL 4.0 on Haswell

On Thu, 2016-10-20 at 16:25 -0700, Ian Romanick wrote: > On 10/20/2016 12:09 AM, Iago Toral Quiroga wrote: > > > > ARB_gpu_shader_fp64 was the last piece missing. Notice that some > > hardware and kernel combinations do not support pipelined register > > writes, which are required for some OpenGL

[Mesa-dev] [PATCH 5/5] nv50/ir: detect when a SLCT is equivalent to a SET

Signed-off-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23 ++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

[Mesa-dev] [PATCH 3/5] nv50/ir: it appears that OP_DISCARD can't take a join modifier

nvdisasm does not print a .S even though the bit is set. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

[Mesa-dev] [PATCH 2/5] nvc0/ir: use levelZero flag when the lod is set to 0

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp

[Mesa-dev] [PATCH 4/5] nv50/ir: don't carefully copy NOP values as a result of phi merging

In order to avoid impossible phi constraints, we insert moves in source BBs to allow the RA to have the flexibility it needs. However there's special logic in the RA to ignore NOPs. It's quite silly to then have logic which carefully copies NOP values into registers. Leave the LValue to be defined

[Mesa-dev] [PATCH 1/5] nv50/ir: use levelZero for non-frag tex/txp ops

radeonsi also does the same thing. I suspect that this is likely to be a no-op in reality, but it brings nouveau code closer to what the blob produces. Plus it makes sense to not try to do auto-derivatives on this. Signed-off-by: Ilia Mirkin ---

Re: [Mesa-dev] [PATCH 2/2] glsl: update default precision qualifiers when they are set in the shader

On 21/10/16 07:48, Timothy Arceri wrote: > On Thu, 2016-10-20 at 12:39 +0200, Samuel Iglesias Gonsálvez wrote: >> For that, we use gls_symbol_table::set_default_precision_qualifier() >> that >> can update an existing definition or add a new one if it doesn't >> exist. >> >> Bugzilla: