With dealing with rectangles in compressed images, you can have a width or
height that isn't a multiple of the corresponding compression block
dimension but only if that edge of your rectangle is on the edge of the
image. When we call convert_to_single_slice, it creates an 2-D image and a
set of
On 10/26/2016 08:15 AM, Timothy Arceri wrote:
On Tue, 2016-10-25 at 09:39 +0300, Tapani Pälli wrote:
SSO shader programs can be later modified by attaching/detaching
shaders and relinked, this requires IR.
Doesn't relinking recreate the IR? We can relink exiting shaders into
new programs.
On Tue, 2016-10-25 at 09:39 +0300, Tapani Pälli wrote:
> SSO shader programs can be later modified by attaching/detaching
> shaders and relinked, this requires IR.
Doesn't relinking recreate the IR? We can relink exiting shaders into
new programs. The IR is cloned from gl_shader (the compiled IR)
Reviewed-by: Timothy Arceri
I guess you don't have commit access?
On Wed, 2016-10-26 at 00:13 -0400, Rhys Kidd wrote:
> Fixes the following compile error, present when the SHA1 library is
> libgcrypt:
>
> CCLD glsl/tests/cache-test
>
On 10/26/2016 04:33 AM, Timothy Arceri wrote:
On Tue, 2016-10-25 at 13:15 -0700, Kenneth Graunke wrote:
SSO validation and other program interface queries want to see that
unsized (non-patch) TCS output/TES input arrays are implicitly sized
to gl_MaxPatchVertices.
By the time we create the
Sure. I'm not 100% clear on what async means, but I think I have the
general idea.
Reviewed-by: Jason Ekstrand
On Tue, Oct 25, 2016 at 8:13 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> We shouldn't be using ASYNC here, that
Reviewed-by: Jason Ekstrand
On Tue, Oct 25, 2016 at 8:13 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just moves this up a level as x11 will need it to
> implement things properly.
>
> Signed-off-by: Dave Airlie
Fixes the following compile error, present when the SHA1 library is libgcrypt:
CCLD glsl/tests/cache-test
glsl/.libs/libglsl.a(libmesautil_la-mesa-sha1.o): In function `call_once':
/mesa/src/util/../../include/c11/threads_posix.h:96: undefined reference to
`pthread_once'
Signed-off-by:
From: Dave Airlie
This just moves this up a level as x11 will need it to
implement things properly.
Signed-off-by: Dave Airlie
---
src/vulkan/wsi/wsi_common.h | 1 +
src/vulkan/wsi/wsi_common_wayland.c | 6 +++---
src/vulkan/wsi/wsi_common_x11.c
From: Dave Airlie
We shouldn't be using ASYNC here, that would be used
for immediate mode, so let's implement that.
Signed-off-by: Dave Airlie
---
src/vulkan/wsi/wsi_common_x11.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Woohoo! Thanks for doing all this. Series is
Reviewed-by: Jason Ekstrand
I think I would feel a tiny bit more comfortable if, for each info field,
you squashed the 2-5 corresponding patches together.
On Thu, Oct 20, 2016 at 1:47 AM, Timothy Arceri <
On Saturday, October 22, 2016 11:13:11 AM PDT Timothy Arceri wrote:
> Here brw_setup_vue_interpolation() is rewritten not to use the InterpQualifier
> array in gl_fragment_program which will allow us to remove it.
>
> This change also makes the code which is only used by gen4/5 more self
>
From: Dave Airlie
For 0 timeout, just poll for an event, and if none, return
For UINT64_MAX timeout, just wait for special event blocked
For other timeouts get the xcb fd and block on it, decreasing
the timeout if we get woken up for non-special events.
Signed-off-by: Dave
the hack was introduced to avoid an extra copying
but now with dri3 we don't need it anymore
v1.1: rebasing
Signed-off-by: Nayan Deshmukh
---
src/gallium/state_trackers/vdpau/bitmap.c| 2 -
src/gallium/state_trackers/vdpau/device.c| 50 -
On Tue, 2016-10-25 at 13:15 -0700, Kenneth Graunke wrote:
> SSO validation and other program interface queries want to see that
> unsized (non-patch) TCS output/TES input arrays are implicitly sized
> to gl_MaxPatchVertices.
>
> By the time we create the program resource lists, we've sized the
>
The next commit will use this in add_shader_variable - this just
separates out some of the mechanical changes for easier review.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/linker.cpp | 33 -
1
From: Dave Airlie
This hooks up the API to the internals for 64-bit integer uniforms.
v2: update to use non-strict aliased alternatives
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/mesa/main/uniform_query.cpp
From: Ian Romanick
It seems like maybe this should return a different type based on Gen. Q
and UQ only exist on Gen8+, but, based on the old comment, I believe
previous Gens can generate 64-bit moves.
Signed-off-by: Ian Romanick
---
From: Ian Romanick
We didn't bother with this in the regular compiler because it doesn't
change the generated code. In the stand-alone compiler, this can
clutter the output with useless variables. It's especially bad after
functions are inlined but the foo_retval
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_builder_print_visitor.cpp | 16 +---
src/compiler/glsl/standalone_scaffolding.cpp | 1 +
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git
From: Ian Romanick
If the user did not request full linking, link the shader with the
built-in functions, inline them, and eliminate them. Previous to this
you'd see all these calls to "dot" and "max" in the output. This
prevented a lot of expected optimizations and
From: Dave Airlie
This just adds the new operations and add 64-bit integer support to all
the existing cases where it is needed.
v2: fix some issues found in testing.
v2.1: add unreachable (Ian), add missing int/uint pack/unpack (Dave).
v3 (idr): Rebase on top of idr's
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/glsl_to_nir.cpp | 30 +++
src/compiler/nir/nir_lower_alu_to_scalar.c | 1 +
src/compiler/nir/nir_opcodes.py| 33
From: Dave Airlie
The intrinsic engine asserts in llvm due to this,
as we put a vec4 into a vec1, and the next instruction
isn't expecting it.
So trim the vector at the end before inserting it.
Reported-by: Christoph Haag
Cc: "13.0"
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_64bit.cpp | 11 +++
2 files changed, 12 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_64bit.cpp | 11 +++
2 files changed, 12 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
From: Ian Romanick
These functions are directly available in shaders. A #define is added
to detect the presence. This allows these functions to be tested using
piglit regardless of whether the driver uses them for lowering. The
GLSL spec says that functions and
From: Ian Romanick
These functions are directly available in shaders. A #define is added
to detect the presence. This allows these functions to be tested using
piglit regardless of whether the driver uses them for lowering. The
GLSL spec says that functions and
From: Ian Romanick
This is only in libstandalone currently because it will only be used in
the stand-alone compiler.
v2: Change the signature of the generated function. The ir_factory is
created in the generator, and an availability predicate is taken as a
parameter.
From: Dave Airlie
TODO: go back and fill this out to avoid warnings.
v1.1: move to using a normal CAP. (Marek)
Signed-off-by: Dave Airlie
Reviewed-by: Marek Olšák
---
src/gallium/include/pipe/p_defines.h | 1 +
1 file changed, 1
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/main.cpp | 1 +
src/compiler/glsl/standalone.cpp | 12
src/compiler/glsl/standalone.h | 1 +
3 files changed, 14 insertions(+)
diff --git
From: Ian Romanick
These functions are directly available in shaders. A #define is added
to detect the presence. This allows these functions to be tested using
piglit regardless of whether the driver uses them for lowering. The
GLSL spec says that functions and
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/Makefile.sources | 1 +
src/compiler/glsl/ast_function.cpp | 1 +
src/compiler/glsl/ast_to_hir.cpp | 1 +
From: Dave Airlie
Just add operations to the switch statement here.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
Reviewed-by: Iago Toral Quiroga
---
.../dri/i965/brw_fs_channel_expressions.cpp
From: Dave Airlie
This adds support for 64-bit integer constants to the parser,
ast and ir.
v2: fix a few issues found in testing.
v3: Add missing ir_constant copy contructor support.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
From: Dave Airlie
This adds support to call the new operations on conversions.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/compiler/glsl/ast_function.cpp | 75 ++
From: Ian Romanick
This change makes me wonder whether double packing should be
reimplemented as int64BitsToDouble(packInt2x32(v)). I'm a little on the
fence since not all platforms that support fp64 natively support int64.
Signed-off-by: Ian Romanick
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_reg.h | 1 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 26 +++---
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git
From: Ian Romanick
The lowering passes 64-bit integer operations will generate a lot of
these.
v2: Modify the HANDLE_PACK_UNPACK_INVERSE so that the breaks apply to
the switch instead of the 'do { } while(true)' loop.
Signed-off-by: Ian Romanick
From: Ian Romanick
Noticed while adding support for 64-bit integer types.
Signed-off-by: Ian Romanick
Cc: Jason Ekstrand
---
src/compiler/nir/nir_split_var_copies.c | 8 +---
1 file changed, 5 insertions(+), 3
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_print_visitor.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/glsl/ir_print_visitor.cpp
b/src/compiler/glsl/ir_print_visitor.cpp
index
From: Ian Romanick
If ARB_gpu_shader_int64 is supported, ARB_shader_clock also adds
clockARB() that returns a uint64_t. Rather than add new opcodes and
intrinsics for this, just wrap the existing intrinsic with a
packUint2x32.
Signed-off-by: Ian Romanick
From: Ian Romanick
These functions are directly available in shaders. A #define is added
to detect the presence. This allows these functions to be tested using
piglit regardless of whether the driver uses them for lowering. The
GLSL spec says that functions and
From: Ian Romanick
Signed-off-by: Ian Romanick
---
.../drivers/dri/i965/brw_fs_channel_expressions.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp| 21 +
2 files changed, 27 insertions(+), 2
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/Makefile.glsl.am| 1 +
src/compiler/Makefile.sources| 1 +
src/compiler/glsl/ir_optimization.h | 6 +
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/nir_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 854d64f..10f6e5d 100644
--- a/src/compiler/nir_types.h
From: Dave Airlie
Just add the boilerplate xml code.
v2 (idr): Update dispatch_sanity. Only add extension functions in core
profile.
Signed-off-by: Dave Airlie
Signed-off-by: Ian Romanick
Reviewed-by: Ian Romanick
From: Ian Romanick
The shift operations are a little weird. NIR expects both operands to
have the same size, but the shift count operand is always 32-bits in
GLSL. Upconvert to make the rest of NIR happy, and we'll assume the
driver back-end will do something
From: Dave Airlie
This adds all the conversions in the world, I'm not 100% sure of all of
these are needed, but add all of them and we can cut them down later.
v2: fix issue with packing output types.
v3 (idr): Rebase on top of idr's series to generate
From: Ian Romanick
Integer comparison functions (e.g., nir_op_ilt) are handled in the next
commit.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 --
1 file changed, 10 deletions(-)
diff --git
From: Ian Romanick
This is basically the same as happens for doubles.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 43 +---
1 file changed, 29 insertions(+), 14 deletions(-)
diff
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_link.cpp | 5 +
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
2 files changed, 6 insertions(+)
diff --git
From: Ian Romanick
It's much easier to do this in the generator rather than while coming
out of NIR. brw_type_for_nir_type doesn't know the Gen, so we'd have to
add a bunch of plumbing. The alternate fix is to not emit int64 moves
for doubles in the first place... but
From: Ian Romanick
v2: Fixup assertion in brw_reg_type_to_hw_type to allow
BRW_REGISTER_TYPE_{UQ,Q} on Gen8+.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 5 -
src/mesa/drivers/dri/i965/brw_inst.h| 8
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/nir/nir_split_var_copies.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/nir/nir_split_var_copies.c
b/src/compiler/nir/nir_split_var_copies.c
index
From: Dave Airlie
v2: add conversion opcodes.
v3 (idr): Rebase on replacemtn of TGSI_OPCODE_I2U64 with
TGSI_OPCODE_I2I64.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 217 ++---
1 file changed, 198
From: Dave Airlie
We need builder support to implement some of the builtins.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/compiler/glsl/ir_builder.cpp | 24
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/glsl_to_nir.cpp | 10 ++
src/compiler/nir/nir.c| 4
src/compiler/nir/nir.h| 2 ++
src/compiler/nir/nir_print.c | 8
4
From: Dave Airlie
Reviewed-by: Ian Romanick
---
src/mesa/program/ir_to_mesa.cpp | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index
From: Dave Airlie
This adds 64-bit integer support to some AST and IR operations where
it is needed.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/compiler/glsl/ast_to_hir.cpp | 12 ++--
From: Dave Airlie
Just add types into unsupported or double equivalent spots.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
Reviewed-by: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_fs.cpp
From: Dave Airlie
These are all the allowed 64-bit functions from ARB_gpu_shader_int64
spec.
v2: restrict int64/double functions better.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
From: Dave Airlie
As for the double code, but using the 64-bit integer conversions.
v2 (idr): Remove some spurious u2i() and i2u() operations when packing
and unpacking, repectively, int64_t varyings.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
From: Dave Airlie
Just add support in two more places in ast parsing.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/compiler/glsl/ast_to_hir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Ian Romanick
This just makes the output of the standalone compiler a little more
compact.
Signed-off-by: Ian Romanick
---
src/compiler/glsl/standalone.cpp | 34 ++
1 file changed, 34 insertions(+)
diff
Whew! Here it is! There are four main groups to this patch series.
All of this is available at:
https://cgit.freedesktop.org/~idr/mesa/log/?h=arb_gpu_shader_int64
There are some gaps in our current piglit tests. For example, I
discovered that there are no execution tests for bitwise
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 8d3eee6..67b9850 100644
---
From: Dave Airlie
This just adds the usual boilerplate in mesa core.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_validate.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/ir_validate.cpp
b/src/compiler/glsl/ir_validate.cpp
index
From: Ian Romanick
For many expressions, this is different from the printable name. The
printable name for ir_binop_add is "+", but we want "add". This is
needed for ir_builder_print_visitor.
Signed-off-by: Ian Romanick
---
From: Dave Airlie
This adds the builtins and the lexer support.
To avoid too many warnings, it adds basic support to the type in a few
other places in mesa, mostly in the trivial places.
It also adds a query to be used later for if a type is an integer 32 or 64.
From: Dave Airlie
This just adds the basic boilerplate support.
Signed-off-by: Dave Airlie
Reviewed-by: Ian Romanick
---
src/compiler/glsl/glsl_parser_extras.cpp | 1 +
src/compiler/glsl/glsl_parser_extras.h | 7 +++
2
From: Ian Romanick
This enables a sort of par-linking. The primary use for this feature is
resolving built-in functions in the stand-alone compiler.
Signed-off-by: Ian Romanick
---
src/compiler/glsl/linker.cpp | 28
Add the new memory type between the two device-local types. This makes
the list of supported memory types look like this:
1) DEVICE_LOCAL | | |
2) | HOST_VISIBLE | HOST_COHERENT |
3) DEVICE_LOCAL | HOST_VISIBLE | HOST_COHERENT |
4) |
On Tue, 2016-10-25 at 18:08 +0300, Andres Gomez wrote:
> On Mon, 2016-10-24 at 14:09 +1100, Timothy Arceri wrote:
> >
> > On Sat, 2016-10-22 at 23:09 +0300, Andres Gomez wrote:
> > >
> > >
> >
> >
> >
> >
> > >
> > > + | layout_qualifier BUFFER ';'
> > > ;
> > >
> > >
https://bugs.freedesktop.org/show_bug.cgi?id=97524
--- Comment #15 from Timothy Arceri ---
(In reply to Nicolai Hähnle from comment #10)
> I can reproduce this now. It really seems like this should be fixed in Mesa
> main, though: there is already code that checks for this
https://bugs.freedesktop.org/show_bug.cgi?id=98421
Vinson Lee changed:
What|Removed |Added
Status|NEW |RESOLVED
On 10/25/2016 04:09 PM, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 7 +++
src/mesa/main/framebuffer.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index
On Tue, Oct 25, 2016 at 7:09 PM, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
> src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
> src/mesa/drivers/dri/i965/gen7_wm_state.c
From: Marek Olšák
This is for 12.0 and older. A different commit fixes 13.0 and newer.
Cc: 11.2 12.0
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 9 +
src/mesa/main/framebuffer.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index f19f3af..3aff102 100644
---
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 7 +++
src/mesa/main/framebuffer.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index e1505fa..f19f3af 100644
---
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
src/mesa/drivers/dri/i965/gen7_wm_state.c| 5 +++--
src/mesa/drivers/dri/i965/gen8_depth_state.c | 4 ++--
4 files changed, 10
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index 46a6f64..e1505fa 100644
--- a/src/mesa/main/framebuffer.c
+++
In a situation when there are multiple render targets with alpha testing
enabled, if fragment shader doesn't write to draw buffer zero, it causes
the GPU hang on SKL. No GPU hang is seen on HSW. Simulator gives a
warning for all gen6+ h/w:
"Illegal render target write message length 0xa expected
Nayan Deshmukh wrote:
Hi Andy,
It seems that you have compiled mesa with DRI3 enabled but
vl_dri3_screen_create returns
runs when called in device.c and hence VDPAU fallbacks to using DRI2.
BTW I have sent in the v1.1 for patch 2 which play the video using dri2 in case
of a
fallback.
Patch
https://bugs.freedesktop.org/show_bug.cgi?id=98448
Ilia Mirkin changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugs.freedesktop.org/show_bug.cgi?id=98448
Bug ID: 98448
Summary: Can't init or use the opengl or 3D
Product: Mesa
Version: git
Hardware: x86 (IA32)
OS: Linux (All)
Status: NEW
Severity: blocker
On Mon, Oct 24, 2016 at 08:40:44PM -0700, Jason Ekstrand wrote:
> v2: Properly handle linear blit alignment restrictions
>
> Signed-off-by: Jason Ekstrand
> ---
> src/mesa/drivers/dri/i965/intel_blit.c | 88
> --
> 1 file changed, 73
Hi Andy,
It seems that you have compiled mesa with DRI3 enabled but
vl_dri3_screen_create returns
runs when called in device.c and hence VDPAU fallbacks to using DRI2.
BTW I have sent in the v1.1 for patch 2 which play the video using dri2 in case
of a
fallback.
Regards,
Nayan.
this avoids an extra copy which occurs in case of dri2
v1.1: fallback to dri2 if dri3 fails to initialize
Suggested-by: Christian König
Signed-off-by: Nayan Deshmukh
---
src/gallium/state_trackers/vdpau/presentation.c | 58
SSO validation and other program interface queries want to see that
unsized (non-patch) TCS output/TES input arrays are implicitly sized
to gl_MaxPatchVertices.
By the time we create the program resource lists, we've sized the arrays
to their actual size. (We try to create TCS output arrays to
The next commit will use this in add_shader_variable - this just
separates out some of the mechanical changes for easier review.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/linker.cpp | 33 -
1
Leo Liu wrote:
On 10/25/2016 02:42 PM, Andy Furniss wrote:
Christian König wrote:
Nice work, have you been able to fix all the issues you mentioned on
your last mail?
Additional to that make sure that this set also keeps DRI2 working, in
patch #2 it looks like you call the new function
On Tue, Oct 25, 2016 at 3:41 PM, Samuel Pitoiset
wrote:
> This is especially useful when switching from compute to 3D.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 11 +++
>
It's useful because it lets you avoid having to send a bunch of begins. NAK.
On Tue, Oct 25, 2016 at 3:41 PM, Samuel Pitoiset
wrote:
> It's not particularily useful to store commands which are
> going to be send few lines after.
>
> Signed-off-by: Samuel Pitoiset
And bit 4 is for ... ?
I've only ever seen the blob use the value 0x1011. You're right that
it's a bitfield, but there's all kinds of crazy caches =/
On Tue, Oct 25, 2016 at 3:41 PM, Samuel Pitoiset
wrote:
> MEM_BARRIER seems to be similar to FLUSH, thus bit 0 is for
On Wed, Oct 19, 2016 at 02:29:17PM -0700, Ben Widawsky wrote:
> On 16-10-11 22:26:33, Topi Pohjolainen wrote:
> > And fix a mangled comment while at it.
> >
> > Signed-off-by: Topi Pohjolainen
> > CC: Ben Widawsky
> > CC: Jason Ekstrand
What if instance_count = 1M? (It can happen.)
On Tue, Oct 25, 2016 at 3:41 PM, Samuel Pitoiset
wrote:
> This might help CPU-bounds applications but should not have
> any real effects for GPU-bounds ones.
>
> Signed-off-by: Samuel Pitoiset
>
MEM_BARRIER seems to be similar to FLUSH, thus bit 0 is for
flushing code while bit 12 is for constant buffers.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 2 +-
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